Datasheet SAA4977H Datasheet (Philips)

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INTEGRATED CIRCUITS

DATA SH EET

SAA4977H

Besic

Preliminary specification
File under Integrated Circuits, IC02

1998 Jul 23

Philips Semiconductors Preliminary specification

Besic SAA4977H

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING INFORMATION

6.1 Pinning

6.2 Pin description
7 FUNCTIONAL DESCRIPTION

7.1 Analog-to-digital conversion

7.2 Digital processing at 1fH level

7.3 Digital processing at 2fH level

7.4 Digital-to-analog conversion

7.5 Microprocessor

7.6 Memory controller

7.7 Line locked clock generation

7.8 Clock and sync interfacing

7.9 4:1:1 I/O interfacing

7.10 Test mode operation

7.11 I2C-bus control registers
8 LIMITING VALUES
9 THERMAL CHARACTERISTICS
10 CHARACTERISTICS
11 APPLICATION
12 PACKAGE OUTLINE
13 SOLDERING

13.1 Introduction

13.2 Reflow soldering

13.3 Wave soldering

13.4 Repairing soldered joints
14 DEFINITIONS
15 LIFE SUPPORT APPLICATIONS
16 PURCHASE OF PHILIPS I2C COMPONENTS

1998 Jul 23 2

Philips Semiconductors Preliminary specification

Besic SAA4977H

1 FEATURES

• Internal prefilter

• Clamp circuit

• Analog AGC

• Line locked PLL

• Triple YUV 8-bit Analog-to-Digital Converter (ADC)

• Synchronous No parity Eight bit Reception and

Transmission (SNERT) interface.

• Horizontal compression

• Field rate up-conversion (50 to 100 Hz or 60 to 120 Hz)

• 4:1:1 digital I/O interface

• Digital CTI (DCTI)

• Digital luminance peaking

• Triple 10-bit Digital-to-Analog Converter (DAC)

• Memory controller

• Embedded microprocessor

• 16 kbyte ROM

• 256 byte RAM

2

C-bus interface

• I

2 GENERAL DESCRIPTION

The SAA4977H is a video processing IC providing analog
YUV interfacing, video enhancing features, memory
controlling and an embedded 80C51 microprocessor core.
It is applicable especially for field rate up-conversion
(50 to 100 Hz or 60 to 120 Hz) in cooperation with a

2.9 Mbit field memory. It is designed for applications
together with:

SAA4955/56TJ, TMS4C2972/73 (serial field memories)
SAA4990H (PROZONIC)
SAA4991WP (MELZONIC).

3 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DDA(1,2,3)

V

DDD(1,2,3)

V

DDA(4,5)

V

DDD(4,5,6)

V

DDIO

I

DDA(1,2,3)

I

DDD(1,2,3)

I

DDA(4,5)

I

DDD(4,5,6)

I

DDIO

P

tot

T

amb

analog supply voltage front-end 4.75 5.0 5.25 V
digital supply voltage front-end 4.75 5.0 5.25 V
analog supply voltage back-end 3.15 3.3 3.45 V
digital supply voltage back-end 3.15 3.3 3.45 V
I/O supply voltage back-end 4.75 5.0 5.25 V
analog supply current front-end − 85 100 mA
digital supply current front-end − 65 80 mA
analog supply current back-end − 25 35 mA
digital supply current back-end − 40 55 mA
I/O supply current back-end − 110mA
total power dissipation −−1.3 W
operating ambient temperature −20 − +60 °C

4 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

SAA4977H QFP80 plastic quad flat package; 80 leads (lead length 1.95 mm);

body 14 × 20 × 2.8 mm

1998 Jul 23 3

SOT318-2

Philips Semiconductors Preliminary specification

Besic SAA4977H

5 BLOCK DIAGRAM

ll pagewidth

YI7 to YI0YO7 to YO0

UVI7 to UVI4UVO7 to UVO4

8 44 8

51 to 5845 to 38
59to62

37to34

YOUT79UOUT76VOUT

DAC

DCTI

REFORMATTER

10 BIT

UP

SAMPLING

UP

SAMPLING

BLANKING

Y-PEAKING

Y-DELAY

VARIABLE

HORIZONTAL

TRIPLE

COMPRESSION

74

SIDE-

PANELS

4 : 2 : 2TO4 : 4 : 4

4 : 1 : 1TO4 : 2 : 2

FORMATTER

RAM

ROM

SAA4977H

C-

2

I

BUS

12,

BUS

SNERT-

I/O

MICROPROCESSOR

PORT

71,

CONTROL

INTERFACE

CONTROL

INTERFACE

63,

(DISPLAY)

MEMORY CONTROL

(ACQUISITION)

MEMORY CONTROL

MGM592

1, 2

13, 10

3 to 7

68 9
72
66
64
70

24

32

20

2

3

5

2

2

SCL

SDA,

SNCL,

SNDA,

P1.5toP1.1

RST

HRD

HDFL

BLND

RE

LLD

RSTW

WE

VA

SNRST

VDFL

IE2

Fig.1 Block diagram.

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1998 Jul 23 4

DOWN

4 : 4 : 4TO4 : 1 : 1

SAMPLING

PLL

ACQUISITION

TEST

CONTROL

ADC

TRIPLE

CLAMP

28

UV

AGC

UIN

CLAMP

CORRECTION

8 BIT

ANALOG

PREFILTER
30

VIN

VARIABLE Y-DELAY

26

YIN

BLOCK

17
22
33
47

49

15

SELCLK

HA

LLA

SWC

TRST

TMS

Philips Semiconductors Preliminary specification

Besic SAA4977H

6 PINNING INFORMATION

6.1 Pinning

handbook, full pagewidth

SDA

SCL
P1.5
P1.4
P1.3
P1.2
P1.1

V

DDD5

RST

SNRST
V

DDD6
SNDA

SNCL

V

SSD4

TMS

V

SSD1

SELCLK

V

DDD1

V

DDD2

VA

V

SSA1

HA

V

DDA1

RSTW

DDA5

V

YOUT

80

79
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

SSA6

V

78

SSA5

V

77

UOUT
76

DDA4

V

75

SSA4

VOUT

V

74

73

SAA4977H

VDFL
72

HDFL
71

LLD
70

DDD4

V

69

HRD
68

DDIO

V
67

BLND
66

SSIO

V

65

IE2

64

RE

63

UVI4

62

UVI5

61

UVI6

60

UVI7

59

YI0

58

YI1

57

YI2

56

YI3

55

YI4

54

YI5

53

YI6

52

YI7

51

V

50

SSD3

TRST

49

V

48

SSD2

SWC

47

V

46

DDD3

YO7

45

YO6

44

YO5

43

YO4

42

YO3

41

25

26

27

28

29

30

31

32

DDA2

V

YIN

SSA2

V

UIN

DDA3

V

VIN

SSA3

V

WE

Fig.2 Pin configuration.

1998 Jul 23 5

33

LLA

34

UVO4

35

UVO5

36

UVO6

37

UVO7

38

YO0

39

YO1

40

YO2

MGM593

Philips Semiconductors Preliminary specification

Besic SAA4977H

6.2 Pin description
Table 1 QFP80 package

SYMBOL PIN DESCRIPTION

SDA 1 I
SCL 2 I
P1.5 3 Port 1 data input/output signal 5
P1.4 4 Port 1 data input/output signal 4
P1.3 5 Port 1 data input/output signal 3
P1.2 6 Port 1 data input/output signal 2
P1.1 7 Port 1 data input/output signal 1
V

DDD5

8 digital supply voltage 5 (3.3 V)
RST 9 microprocessor reset input
SNRST 10 SNERT restart (port 1.0)
V

DDD6

11 digital supply voltage 6 (3.3 V)
SNDA 12 SNERT data
SNCL 13 SNERT clock
V

SSD4

14 digital ground 4
TMS 15 test mode select
V

SSD1

16 digital ground 1
SELCLK 17 select acquisition clock input; internal PLL if HIGH, external clock if LOW
V
V

DDD1
DDD2

18 digital supply voltage 1 (5 V)

19 digital supply voltage 2 (5 V)
VA 20 vertical synchronization input, acquisition part
V

SSA1

21 analog ground 1
HA 22 analog/digital horizontal reference input
V

DDA1

23 analog supply voltage 1 (5 V)
RSTW 24 reset write signal output, memory 1
V

DDA2

25 analog supply voltage 2 (5 V)
YIN 26 Y analog input
V

SSA2

27 analog ground 2
UIN 28 U analog input
V

DDA3

29 analog supply voltage 3 (5 V)
VIN 30 V analog input
V

SSA3

31 analog ground 3
WE 32 write enable signal output, memory 1
LLA 33 acquisition clock input
UVO4 34 V digital output bit 0
UVO5 35 V digital output bit 1
UVO6 36 U digital output bit 0
UVO7 37 U digital output bit 1
YO0 38 Y digital output bit 0

2

C-bus serial data (P1.7)

2

C-bus serial clock (P1.6)

1998 Jul 23 6

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SYMBOL PIN DESCRIPTION

YO1 39 Y digital output bit 1
YO2 40 Y digital output bit 2
YO3 41 Y digital output bit 3
YO4 42 Y digital output bit 4
YO5 43 Y digital output bit 5
YO6 44 Y digital output bit 6
YO7 45 Y digital output bit 7 (MSB)
V

DDD3

SWC 47 serial write clock output
V

SSD2

TRST 49 test reset, active LOW
V

SSD3

YI7 51 Y digital input bit 7 (MSB)
YI6 52 Y digital input bit 6
YI5 53 Y digital input bit 5
YI4 54 Y digital input bit 4
YI3 55 Y digital input bit 3
YI2 56 Y digital input bit 2
YI1 57 Y digital input bit 1
YI0 58 Y digital input bit 0
UVI7 59 U digital input bit 1
UVI6 60 U digital input bit 0
UVI5 61 V digital input bit 1
UVI4 62 V digital input bit 0
RE 63 read enable signal output, memory 1
IE2 64 input enable signal output, memory 2
V

SSIO

BLND 66 horizontal blanking signal output, display part
V

DDIO

HRD 68 horizontal reference signal output, deflection part
V

DDD4

LLD 70 display clock input
HDFL 71 horizontal synchronization signal output, deflection part
VDFL 72 vertical synchronization signal output, deflection part
V

SSA4

VOUT 74 V analog output
V

DDA4

UOUT 76 U analog output
V

SSA5

46 digital supply voltage 3 (5 V)

48 digital ground 2

50 digital ground 3

65 I/O ground

67 I/O supply voltage (5 V)

69 digital supply voltage 4 (3.3 V)

73 analog ground 4

75 analog supply voltage 4 (3.3 V)

77 analog ground 5

1998 Jul 23 7

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SYMBOL PIN DESCRIPTION

V

SSA6

YOUT 79 Y analog output
V

DDA5

78 analog ground 6

80 analog supply voltage 5 (3.3 V)

7 FUNCTIONAL DESCRIPTION

7.1 Analog-to-digital conversion

7.1.1 C

LAMP CIRCUIT, CLAMPING Y TO DIGITAL LEVEL 16

AND UV TO 0 (2’S COMPLEMENT)

A clamp circuit is applied for each input channel, to map
the colourless black level in each video line (on the sync
back porch) to level 16 for Y and to the centre level of the
converters for U and V. During the clamp period, an
internally generated clamp pulse is used to switch on the
clamp action. An operational transconductance amplifier
like construction, which references to voltage reference
points in the ladders of the ADCs, will provide a current on
the input of the YUV signals, in order to bring the signals
to the correct DC value. This current is proportional to the
DC error, but is limited to ±100 µA. When the clamping
action is off, the residual clamp current should be very low
in order not to drift away within a video line.

7.1.2 G

AIN ELEMENTS FOR AUTOMATIC GAIN CONTROL

A variable amplifier is used to map the possible YUV input
range to the ADC range. A rise of 6 dB up to a drop fall of
6 dB w.r.t. the nominal values can be achieved. The gain
setting within this range is done digitally via control
registers. For this purpose a gain setting DAC is
incorporated. The smallest step in the gain setting should
be hardly visible on the picture, which can be met with
smallest steps of 0.4%/step.

Luminance and chrominance gain settings can be
separately controlled. The reason for this split is that
U and V may be gain adjusted already, whereas
luminance is to be adjusted by the SAA4977H AGC. On
the other hand, for RGB originated sources, Y, U and V
should be adjusted with the same AGC gain.

7.1.3 A

NALOG ANTI-ALIASING PREFILTERING

A third order linear phase filter is applied on each of the Y,
U and V channels. It provides a notch on f

(16 MHz) to

CLK

strongly prevent aliasing to low frequencies, which would
be the most disturbing. The bandwidth of the filters is
designed for −3 dB at 5.6 MHz. The filters can be
bypassed if external filtering with other characteristics is
desired.

7.1.4 T

RIPLE 8-BIT ANALOG-TO-DIGITAL CONVERSION

Three identical ADCs are used to convert Y, U and V with
16 MHz data rate. A multi-step type ADC is applied here.

7.2 Digital processing at 1f

7.2.1 O

VERLOAD DETECTION

level

H

The overload detection provides information to make
efficient use of the AGC. The number of overflows per
video field in the luminance channel is accumulated by a
14-bit counter. The 8 MSBs of this counter can be read out
by the microprocessor respectively via the I2C-bus.
Overflow levels can be programmed as 216, 224,
232 and 240.

7.2.2 D

IGITAL CLAMP CORRECTION FOR UV

During 32 samples within the clamp position the clamp
error is measured and accumulated to make a low-pass
filtered value of the clamp error. Then a vertical recursive
filter is used to further low-pass this error value. This value
can be read by the microprocessor or directly be used to
correct the clamp error. It is also possible to give a fixed
correction value by the microprocessor.

7.2.3 4:4:4

CORING

TO 4:1:1DOWN-SAMPLING AND UV

The U and V samples from the ADC are low-pass filtered,
before being subsampled with a factor of 2. Coring is
applied to the subsampled signal to obtain no gain for low
amplitudes which is considered to be noise. Coring levels
can be programmed as 0 (off), ±1⁄2, ±1 and ±2 LSB.

The U and V samples from the 4 :2:2 data are low-pass
filtered again, before being subsampled a second time
with a factor of 2 and formatted to 4 :1:1 format.

7.2.4 Y-

DELAY

The Y samples can be shifted onto 8 positions w.r.t. the
UV samples. This shift is meant to account for a possible
difference in delay previous to the SAA4977H. The zero
delay setting is suitable for the nominal case of aligned
input data according to the interface format standard.
The other settings provide four samples less delay to three
sample more delay in Y.

1998 Jul 23 8

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7.2.5 HORIZONTAL COMPRESSION
For displaying 4 : 3 sources on 16 : 9 screens a horizontal

signal compression can be done by data interpolation.
Therefore two horizontal compression factors of either

4

⁄3or7⁄6 are possible. Via the I2C-bus the compression can

be switched on or off and the compression mode 16 : 9 or
14 : 9 can be selected. When the compression mode is
active, a reduced number of the interpolated data is stored
in the field memory. To achieve sufficiently high accuracy
in interpolation Variable Phase Delay filters are used
(VPD10 for luminance, a multiplexed VPD06 for UV).

7.3 Digital processing at 2f

7.3.1 4:1:1

TO 4:2:2UP-CONVERSION

level

H

An up-converter to 4:2:2 is applied with a linear
interpolation filter for creation of the extra samples. These
are combined with the original samples from the 4 :1:1
stream.

7.3.2 DCTI
The Digital Colour Transient Improvement (DCTI) is

intended for U and V signals originating from a 4 :1:1
source. Horizontal transients are detected and enhanced
without overshoots by differentiating, make absolute and
again differentiating the U and V signals separately.

This results in a 4:4:4 U and V bandwidth. To prevent
third harmonic distortion, typical for this processing, a so
called over the hill protection prevents peak signals
becoming distorted. Via the I

2

C-bus it is possible to
control: gain width (see Fig.4), threshold (i.e. immunity
against noise), selection of simple or improved first
differentiating filter (see Fig.3), limit for pixel shift range
(see Fig.5), common or separate processing of U and V
signals, hill protection mode (i.e. no discolourations in
narrow colour gaps), low-pass filtering for U and V signals
(see Fig.6) and a so called super hill mode, which avoids
discolourations in transients within a colour component.

7.3.3 Y-

PEAKING

A linear peaking is applied, which amplifies the luminance
signal in the middle and the upper ranges of the
bandwidth.

The filtering is an addition of:

• The original signal

• The original signal high-passed with maximum gain at

frequency =1⁄2fs (8 MHz)

• The original signal band-passed with centre

frequency =1⁄4fs (4 MHz)

• The original signal band-passed with centre frequency
of 2.38 MHz.

The band-passed and high-passed signals are weighted
with factors 0,

1

⁄16,2⁄16,3⁄16,4⁄16,5⁄16,6⁄16, and8⁄16, resulting

in a maximum gain difference of 2 dB at the centre
frequencies.

Coring is added to obtain no gain for low amplitudes in the
high-pass and band-pass filtered signal, which is
considered to be noise. Coring levels can be programmed
as 0 (off), ±8, ±16, ±24 to ±120 LSB w.r.t. the (signed)
11-bit filtered signal.

In addition the peaking gain can be reduced depending on
the signal amplitude, programming range 0 (no
attenuation),1⁄4,2⁄4, and4⁄4. It is also possible to make
larger undershoots than overshoots, programming range 0
(no attenuation of undershoots),1⁄4,2⁄4, and4⁄4.

7.3.4 Y-

DELAY

The Y samples can be shifted onto 8 positions w.r.t. the
UV samples. This shift is meant to account for a possible
difference in delay previous to the SAA4977H. The zero
delay setting is suitable for the nominal case of aligned
input data. The other settings provide one to seven
samples less delay in Y.

7.3.5 S

IDEPANELS AND BLANKING

Sidepanels are generated by switching Y and the 4 MSBs
of U and V to certain programmable values. The start and
stop values for the sidepanels w.r.t. the rising edge of the
HRD signal are programmable in a resolution of 4 LLD
clock cycles. In addition, a fine shift of 0 to 3 LLD clock
cycles of both values can be achieved.

Blanking is done by switching Y to value 64 at 10-bit word
and UV to value 0 (in 2’s complement). Blanking is
controlled by a composite signal HVBDA, consisting of a
horizontal part HBDA and a vertical part VBDA. Set and
reset value of the horizontal control signal HBDA are
programmable w.r.t. the rising edge of the HRD signal, set
and reset value of the vertical control signal VBDA are
programmable w.r.t. the rising edge of the VA signal.

The range of the Y output signal can be selected between
9 and 10 bits. In the case of 9 bits for the nominal signal
there is room left for undershoot and overshoot (adding up
to a total of 10 bits). In the case of selecting all 10 bits of
the luminance DAC for the nominal signal any under or
overshoot will be clipped (see Fig.11).

1998 Jul 23 9

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Besic SAA4977H

(1) dcti_ddx_sel = 1.
(2) dcti_ddx_sel = 0.

Fig.3 DCTI first differentiating filter; transfer function with variation of control signal dcti_ddx_sel.

signal

amplitude

0.8

0.6

0.4

0.2

1

0

0 0.25

handbook, halfpage

(2)(1)

0.05 0.1 0.15 0.2

MGM689

f/f

s

handbook, full pagewidth

(1) input signal.
(2) gain = 1.
(3) gain = 3.
(4) gain = 5.
(5) gain = 7.

digital
signal

amplitude

500

400

300

200

100

−100

−200

−300

−400

−500

MGM690

(1)

(4)

(5)

0

(2)

(3)

samples

Fig.4 DCTI with variation of gain setting (limit = 1).

1998 Jul 23 10

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Besic SAA4977H

handbook, full pagewidth

(1) input signal.
(2) limit = 1.
(3) limit = 2.
(4) limit = 3.

digital
signal

amplitude

500

400

300

200

100

−100

−200

−300

−400

−500

MGM691

(4)

(3)

(2)

(1)

0

samples

Fig.5 DCTI with variation of limit setting (gain = 7).

1.2

handbook, halfpage

signal

amplitude

0.8

0.4

0

0 0.5

0.1 0.2 0.3 0.4

Fig.6 DCTI post-filter transfer function.

1998 Jul 23 11

MGM692

f/f

s

Philips Semiconductors Preliminary specification

Besic SAA4977H

10

handbook, full pagewidth

signal

amplitude

(dB)

8

6

4

2

0

0 0.1 0.2 0.3 0.4

(1) β =1⁄16.
(2) β =2⁄16.
(3) β =3⁄16.
(4) β =4⁄16.
(5) β =5⁄16.
(6) β =6⁄16.
(7) β =8⁄16.

MGM594

(7)

(6)

(5)

(4)

(3)

(2)

(1)

f/f

s

0.5

Fig.7 Transfer function of the peaking high-pass filter with variation of β (α =0;τ= 0).

1998 Jul 23 12

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Besic SAA4977H

10

handbook, full pagewidth

signal

amplitude

(dB)

8

6

4

2

0

0 0.1 0.2 0.3 0.4

(1) α =1⁄16.
(2) α =2⁄16.
(3) α =3⁄16.
(4) α =4⁄16.
(5) α =5⁄16.
(6) α =6⁄16.
(7) α =8⁄16.

MGM595

(7)

(6)

(5)

(4)

(3)

(2)

(1)

f/f

s

0.5

Fig.8 Transfer function of the peaking band-pass with variation of α (β =0;τ= 0).

1998 Jul 23 13

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10

handbook, full pagewidth

signal

amplitude

(dB)

8

6

4

2

0

0 0.1 0.2 0.3 0.4

(1) τ =1⁄16.
(2) τ =2⁄16.
(3) τ =3⁄16.
(4) τ =4⁄16.
(5) τ =5⁄16.
(6) τ =6⁄16.
(7) τ =8⁄16.

MGM596

(7)

(6)

(5)

(4)

(3)

(2)

(1)

f/f

s

0.5

Fig.9 Transfer function of peaking low band-pass with variation of τ (α =0;β= 0).

1998 Jul 23 14

Philips Semiconductors Preliminary specification

Besic SAA4977H

7.4 Digital-to-analog conversion

Three identical 10-bit DACs are used to map the 4 : 4 : 4
data to analog levels.

7.5 Microprocessor

The SAA4977H contains an embedded 80C51
microprocessor core including a 256 byte RAM and
16 kbyte ROM. The microprocessor runs on a 16 MHz
clock, generated by dividing the 32 MHz display clock by a
factor of 2. For controlling internal registers a host
interface, consisting of a parallel address and data bus, is
built-in, that can be addressed as internal AUX RAM via
MOVX type of instructions.

7.5.1 I

2

C-BUS

The I2C-bus interface in the SAA4977H is used in a slave
receive and transmit mode for communication with a
central system microprocessor. The standardized bus
frequencies of both 100 kHz and 400 kHz can be dealt
with.

The I2C-bus slave address of the SAA4977H is
0110100 R/W.

For a detailed description of the transmission protocol
refer to brochure
number 9398 393 40011) and to Application note

register specification of the SAA4977H”

7.5.2 SNERT-

“The I2C-bus and how to use it”

(AN98054).

BUS

(order

“I2C-bus

A SNERT interface is built-in, which operates in a master
receive and transmit mode for communication with
peripheral circuits such as the SAA4990H or
SAA4991WP. The SNERT interface replaces the standard
UART interface. In contrast to the 80C51 UART interface
there are additional special function registers and there is
no byte separation time between address and data.

The SNERT interface transforms the parallel data from the
microprocessor into 1 Mbaud SNERT data. The
SNERT-bus consists of three signals: SNCL used as the
serial clock signal and is generated by the SNERT
interface; SNDA used as the bidirectional data line, and
SNRST used as the reset signal and is generated by the
microprocessor to indicate the start of a transmission.

The read or write operation must be set by the
microprocessor. When writing to the bus, 2 bytes are
loaded by the microprocessor: one for the address, the
other for the data.

When reading from the bus, one byte is loaded by the
microprocessor for the address, the received byte is the
data from the addressed SNERT location.

7.5.3 I/O

PORTS

A parallel 8-bit I/O port (P1) is available, where P1.0 is
used as the SNERT reset signal (SNRST), P1.1 to P1.5
can be used for application specific control signals, and
P1.6 and P1.7 are used as I2C-bus signals (SCL and
SDA).

7.5.4 W

ATCHDOG TIMER

The microprocessor contains an internal Watchdog Timer,
which can be activated by setting the bit 4 in SFR PCON.
Only a synchronous reset will clear this bit. To prevent a
system reset the Watchdog Timer must be reloaded in
time. The Watchdog Timer is incremented every 0.75 ms.
The time interval between the timer’s reloading and the
occurrence of a reset depends on the reloaded 8-bit value.

7.6 Memory controller

The memory controller provides all necessary acquisition
clock related write signals (WE and RSTW) and display
clock related read signals (RE and IE2) to control one or
two-field memory concepts. Furthermore the drive signals
(HDFL and VDFL) for the horizontal and vertical deflection
power stages are generated. Also a horizontal blanking
pulse BLND is generated which can be used for peripheral
circuits as SAA4990H. The memory controller is
connected to the microprocessor via the host interface.
Start and stop values for all pulses, referring to the
corresponding horizontal or vertical reference signal, are
programmable under control of the internal software.
To allow user access to these control signals via the

2

I

C-bus a range of subaddresses is reserved; for a
detailed description of this user interface refer to
Application Note

SAA4977H”

“I2C-bus register specification of the

(AN98054).

7.6.1 WE
The write enable signal for field memory 1 is a composite

signal consisting of a horizontal and a vertical part.
The horizontal position w.r.t the rising edge of the HA
signal and the vertical position w.r.t the rising edge of the
VA signal are programmable.

1998 Jul 23 15

Philips Semiconductors Preliminary specification

Besic SAA4977H

7.6.2 RSTW
Reset write signal for field memory 1; this signal is derived

from the positive edge of the VA input signal and has a
pulse width of 64 µs.

7.6.3 RE
The read enable signal for field memory 1 is a composite

signal consisting of a horizontal and a vertical part.
The horizontal position w.r.t the rising edge of the HA
signal and the vertical position w.r.t the rising edge of the
VA signal are programmable.

7.6.4 IE2
Input enable signal for field memory 2, can be directly set

or reset by the microprocessor.

7.6.5 HDFL
Horizontal deflection signal for driving a deflection circuit;

this signal has a cycle time of 32 µs and a pulse width of
76 LLD clock cycles.

7.6.6 VDFL
Vertical deflection signal for driving a deflection circuit; this

signal has a cycle time of 10 ms; the start and stop value
w.r.t the rising edge of the VA signal is programmable in
steps of 16 µs.

7.7.2 PLL

CLOCK GENERATOR RUNNING AT 32 MHZ

(2048 CLOCK CYCLES PER LINE)

The basic frequency of the clock generator is 32 MHz.
The type of PLL is known as ‘Petra PLL’. This is a purely
analog clock generator, with analog frequency control via
a loop filter on the measured phase error.

7.7.3 D

IVIDE-BY-2 FOR MASTER CLOCK 16 MHZ

A simple clock divider is used to generate 16 MHz out of
32 MHz. The advantage of this construction is the inherent
50% duty cycle on the acquisition clock.

7.7.4 D

IVIDE BY ANOTHER 1024 TO GENERATE LINE

FREQUENT

, CLOCK SYNCHRONOUS H

ref

SIGNAL

The video lines contain 1024 clock cycles of 16 MHz.
Therefore, frequency division by 1024 creates a 50% duty
cycle line frequent signal H

ref

.

7.8 Clock and sync interfacing

Typically the circuit operates as a two clock system, i.e.
LLA is supplied with a 16 MHz clock and LLD with a
32 MHz clock.

The line locked display clock LLD must be provided by the
application. Also a line frequent signal must be provided by
the application at pin HA. A vertical 50 or 60 Hz
synchronization signal has to be applied on pin VA.

7.6.7 BLND
Horizontal blanking signal for peripheral circuits e.g.

SAA4990H, start and stop values w.r.t. the rising edge of
HRD are programmable.

7.7 Line locked clock generation

7.7.1 P

HASE COMPARISON OF HA RISING EDGE WITH

GENERATED

H

ref

SIGNAL

The HA signal, which has a nominal period of 64 µs, is
used as a timing reference for the line locked acquisition
clock system. This HA signal may vary in position from
application to application, related to the active video part.
The phase comparator measures the delay between the
HA and the internally generated, clock synchronous H

ref

signal.

It is also possible to use an external line locked acquisition
clock, which must be provided at pin LLA. This operation
mode can be selected by the SELCLK pin. When using the
external acquisition clock the HA signal must be
synchronous to the acquisition clock.

A display clock synchronous line frequent signal is put out
at pin HRD providing a duty factor of 50%. The rising edge
of HRD is also the reference for display related control
signals as BLND, RE, HDAV and HBDA.

The acquisition clock is buffered internally and put out as
serial write clock (SWC) for supplying the field memory.

1998 Jul 23 16

Philips Semiconductors Preliminary specification

Besic SAA4977H

7.9 4:1:1 I/O interfacing
Table 2 Digital input and output bus format

OUTPUT

PIN

YO7 Y07 Y17 Y27 Y37 YI7
YO6 Y06 Y16 Y26 Y36 YI6
YO5 Y05 Y15 Y25 Y35 YI5
YO4 Y04 Y14 Y24 Y34 YI4
YO3 Y03 Y13 Y23 Y33 YI3
YO2 Y02 Y12 Y22 Y32 YI2

Y01 Y01 Y11 Y21 Y31 YI1

YO0 Y00 Y10 Y20 Y30 YI0
UVO7 U07 U05 U03 U01 UVI7
UVO6 U06 U04 U02 U00 UVI6
UVO5 V07 V05 V03 V01 UVI5
UVO4 V06 V04 V02 V00 UVI4

The first phase of the 4:1:1 YUV dataword is available
on the output bus one SWC clock cycle after the rising
edge of the WE signal. The start position, when the first
phase of the 4:1:1 YUV data word is expected on the
input bus, can be defined by the internal control signal
HDAV.

4:1:1 FORMAT

INPUT

PIN

The luminance output signal is in 8-bit straight binary
format, whereas U and V input signals are in
2’s complement format. Also the luminance input signal is
expected in 8-bit straight binary format, whereas U and V
input signals are expected in 2’s complement format. The
U and V input signals are inverted if the corresponding
control bit uv_inv is set via the I

7.10 Test mode operation

The SAA4977H provides a test mode function which
should not be entered by the customer. If the
is driven HIGH, different test modes can be selected by
applying a HIGH to the TMS input for a defined number of
LLD clock cycles. To exit the test mode TMS and TRST
must be driven LOW.

2

C-bus.

TRST input

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Philips Semiconductors Preliminary specification

Besic SAA4977H

7.11 I2C-bus control registers
ADDRESS BIT NAME DESCRIPTION

Subaddress 00H to 2FH: reserved; note 1
Subaddress 30H to 32H (AGC)

30H 0 to 7 AGC_Y AGC gain for Y channel (2’s complement relative to 0 dB): upper 8 bits
31H 0 to 7 AGC_UV AGC gain for U and V channel (2’s complement relative to 0 dB): upper 8 bits
32H 0 AGC_Y AGC gain for Y channel LSB

1 AGC_UV AGC gain for UV channel LSB
2 standby_f front-end in standby mode if HIGH
3 aaf_bypass bypass for prefilter if HIGH
4to7 − reserved

Subaddress 33H (UV clamp correction)

33H 0 and 1 UVclcor_mode clamp correction mode = auto, fixed, keep, reserved

2 to 4 Uclcor_fval fixed value for clamp correction U channel
5 to 7 Vclcor_fval fixed value for clamp correction V channel

Subaddress 34H (UV coring)

34H 0 and 1 UVcoring coring level = 0, ±0.5, ±1 and ±2 LSB

2 and 3 − reserved
4 and 5 UVcl_tau vertical filtering of measured clamp
6 and 7 − reserved

Subaddress 35H (Y delay)

35H 0 to 2 ydelay_f variable Y-delay in LLA clock cycles: −4, −3, −2, −1, 0, 1, 2 and 3

3 and 4 overl_thr overload threshold: (216, 224, 232, 240)
5 fill_mem fill memory with constant value if HIGH
6 and 7 − reserved

Subaddress 36H and 37H (DCTI)

36H 0 to 2 dcti_gain DCTI gain: 0, 1, 2, 3, 4, 5, 6 and 7

3 to 6 dcti_threshold DCTI threshold: 0, 1 to 15
7 dcti_ddx_sel DCTI selection of first differentiating filter; see Fig.3

37H 0 and 1 dcti_limit DCTI limit for pixel shift range: 0, 1, 2 and 3

2 dcti_separate DCTI separate processing of U and V signals; 0 = off, 1 = on
3 dcti_protection DCTI over the hill protection; 0 = off, 1 = on
4 dcti_filteron DCTI post-filter; 0 = off, 1 = on
5 dcti_superhill DCTI super hill mode; 0 = off, 1 = on
6 and 7 − reserved

Subaddress 38H and 3AH (peaking)

38H 0 to 2 pk_alpha peaking alpha:

3 to 5 pk_beta peaking beta:
6 and 7 − reserved

1998 Jul 23 18

1

⁄16 (0, 1, 2, 3, 4, 5, 6, 8)

1

⁄16 (0, 1, 2, 3, 4, 5, 6, 8)

Philips Semiconductors Preliminary specification

Besic SAA4977H

ADDRESS BIT NAME DESCRIPTION

1

39H 0 to 2 pk_tau peaking tau:

3 and 4 pk_delta peaking amplitude dependent attenuation:
5 and 6 pk_neggain peaking attenuation of undershoots:
7 − reserved

3AH 0 to 3 pk_corthr peaking coring threshold 0,±8, ±16 to ±120 LSB

4to7 − reserved

Subaddress 3BH and 3CH (sidepanels overlay)

3BH 0 to 3 overlay_u sidepanels overlay U (4 MSB)

4 to 7 overlay_v sidepanels overlay V (4 MSB)

3CH 0 to 7 overlay_y sidepanels overlay Y (8 MSB)

Subaddress 3DH to 3FH (sidepanel position)

3DH 0 to 7 sidepanel_start sidepanel start position (8 MSB) w.r.t. the rising edge of HRD signal
3EH 0 to 7 sidepanel_stop sidepanel stop position (8 MSB) w.r.t. the rising edge of HRD signal
3FH 0 and 1 sidepanel_fdel fine delay of sidepanel signal in LLD clock cycles: 0, 1, 2 and 3

2 output_range output range (output range = 0: 9 bit for the nominal output signal,

black level: 288 and white level: 767; output range = 1: 10 bit for the nominal

output signal, black level 64 and white level 1023)
3 uv_inv inverts UV input signals: 0 = no inversion, 1 = inversion
4 to 6 ydelay_out variable Y-delay in LLD clock cycles: −7, −6, −5, −4, −3, −2, −1 and 0
7 − reserved

⁄16 (0, 1, 2, 3, 4, 5, 6, 8)

1

⁄4 (0, 1, 2, 4)

1

⁄4 (0, 1, 2, 4)

Note

1. Detailed information about the software dependent I2C-bus registers can be found in Application Note

register specification of the SAA4977H”

(AN98054).

“I2C-bus

8 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

DDA(1,2,3)

V

DDD(1,2,3)

V

DDA(4,5)

V

DDD(4,5,6)

V

DDIO

V

i

T

stg

T

amb

analog supply voltage front-end −0.5 +5.25 V
digital supply voltage front-end −0.5 +5.25 V
analog supply voltage back-end −0.5 +3.45 V
digital supply voltage back-end −0.5 +3.45 V
digital I/O supply voltage back-end −0.5 +5.25 V
input voltage for all I/O pins −0.5 +5.25 V
storage temperature −20 +150 °C
operating ambient temperature −20 +60 °C

9 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 50 K/W

1998 Jul 23 19

Philips Semiconductors Preliminary specification

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10 CHARACTERISTICS

V

DDD(1,2,3)

T

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DDA(1,2,3)

V

DDD(1,2,3)

I

DDA(1,2,3)

I

DDD(1,2,3)

V

DDA(4,5)

V

DDD(4,5,6)

V

DDIO

I

DDA(4,5)

I

DDD(4,5,6)

I

DDIO

Dissipation

P

tot

Luminance input signal (Y clamp level digital 16)

V

i(p-p)

C

i

I

LI

I

I

α

AGC(max)

G

AGC(max)

α

AGC(acc)

G

AGC(acc)

Colour difference input signals (U and V clamp level digital 128)

V

i(p-p)

C

i

I

LI

I

I

α

AGC(max)

G

AGC(max)

α

AGC(acc)

G

AGC(acc)

= 4.75 to 5.25 V; V

DDA(1,2,3)

= 4.75 to 5.25 V; V

= 0 to 60 °C; unless otherwise specified.

analog supply voltage front-end 4.75 5.0 5.25 V
digital supply voltage front-end 4.75 5.0 5.25 V
analog supply current front-end − 85 100 mA
digital supply current front-end − 65 80 mA
analog supply voltage back-end 3.15 3.3 3.45 V
digital supply voltage back-end 3.15 3.3 3.45 V
I/O supply voltage back-end 4.75 5.0 5.25 V
analog supply current back-end − 25 35 mA
digital supply current back-end − 40 55 mA
I/O supply current back-end − 110 mA

total power dissipation −−1.3 W

Y input level
(peak-to-peak value)

input capacitance − 715 pF
input leakage current clamp not active −−100 nA
input current during clamping −−±150 µA
maximum AGC attenuation 5.75 6 − dB
maximum AGC gain 5.75 6 − dB
AGC attenuation accuracy

digital
AGC gain accuracy digital − 8 − bits

U input level
(peak-to-peak value)

V input level
(peak-to-peak value)

input capacitance −−15 pF
input leakage current clamp not active −−100 nA
input current during clamping −−±150 µA
maximum AGC attenuation 5.75 6 − dB
maximum AGC gain 5.75 6 − dB
AGC attenuation accuracy

digital
AGC gain accuracy digital − 8 − bits

DDD(4,5,6)

= 3.15 to 3.45 V; V

DDA(4,5)

= 3.15 to 3.45 V;

AGC fixed at 0 dB; note 1 0.95 1.00 1.05 V

− 8 − bits

AGC fixed at 0 dB; note 1 1.29 1.34 1.39 V

AGC fixed at 0 dB; note 1 1.00 1.05 1.10 V

− 8 − bits

1998 Jul 23 20

Philips Semiconductors Preliminary specification

Besic SAA4977H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog input transfer function (sample rate 16 MHz/8 bits)

f

CLK

INL integral non linearity ramp input signal −1 − +1 LSB
DNL differential non linearity ramp input signal −0.75 − +0.75 LSB
S/N signal-to-noise ratio nominal amplitude;

HD harmonic distortion (2nd to 5th

G

dif

SVR supply voltage rejection note 2 34 −− dB

maximum sample clock 18 −− MHz

43 −− dB

0 to 8 MHz

harmonic)
differential gain f

95% amplitude;
Y at 4.3 MHz; UV at 1 MHz

= 4.4 MHz; ADC only;

CLK

−−50 −37 dB

− 12 %

at nominal AGC setting

Analog Y, U and V input filter (third order linear phase filter with notch at f

f

(−3dB)

α

(0.5)

α

sb

f

notch

t

d(g)

t

d(g)(dif)

3 dB down frequency f
attenuation at1⁄2f

(8 MHz) 7 8 − dB

CLK

= 16 MHz 5.4 5.6 5.8 MHz

CLK

stop band attenuation 30 −− dB
notch frequency 15.5 16 16.5 MHz
group delay f

= 4 MHz − 55 65 ns

CLK

differential group delay within

)

CLK

− 20 30 ns

1 to 6 MHz

Luminance output signal (output_range = 0: Y black level digital 288, white level digital 767, output_range = 1:
Y black level digital 64, white level digital 1023); see Fig.11

V

o(p-p)

Y output level

ZL=2kΩ 1.28 1.34 1.40 V

(peak-to-peak value)

R

o

R

L

C

L

output resistance − 50 100 Ω
resistive load 1 2 − kΩ
capacitive load −−25 pF

SVR supply voltage rejection note 2 34 −− dB

α

ct

crosstalk attenuation between

0 to 10 MHz 40 −− dB

outputs

S/N signal-to-noise ratio nominal amplitude;

46 −− dB

0to10MHz

Colour difference output signals (U and V digital range 0 to 1023)

V

o(p-p)

U output level

ZL=2kΩ 1.28 1.34 1.40 V

(peak-to-peak value)
V output level

Z

=2kΩ 1.28 1.34 1.40 V

L

(peak-to-peak value)

G

m(U-V)

R

o

R

L

C

L

gain matching U to V − 13 %
output resistance − 50 100 Ω
resistive load 1 2 − kΩ
capacitive load −−25 pF

SVR supply voltage rejection note 2 34 −− dB

1998 Jul 23 21

Philips Semiconductors Preliminary specification

Besic SAA4977H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

α

ct

S/N signal-to-noise ratio nominal amplitude;

Output transfer function (sample rate 32 MHz/10 bits)

INL integral non linearity −2 − +2 LSB
DNL differential non linearity −1 − +1 LSB

crosstalk attenuation between
outputs

0 to 10 MHz 40 −− dB

46 −− dB

0to10MHz

Digital output signals: YO, UVO, WE and RSTW (C

V

OH

V

OL

t

d(o)

t

h(o)

Digital output signal: SWC (C

V

OH

V

OL

t

d(o)

HIGH-level output voltage IOH= −2.0 mA 2.4 −− V
LOW-level output voltage IOL= 1.6 mA −−0.4 V
output delay time see Fig.10 −−20 ns
output hold time see Fig.10 4 −− ns

= 15 pF); timing referred to LLA clock

L

HIGH-level output voltage IOH= −2.0 mA 2.4 −− V
LOW-level output voltage IOL= 1.6 mA −−0.4 V
output delay time see Fig.10 3 − 12 ns

= 15 pF); timing referred to SWC clock

L

Digital output signal: HRD

V

OH

V

OL

Digital output signals: IE2, BLND, RE, HDFL and VDFL (C

V

OH

V

OL

t

d(o)

t

h(o)

HIGH-level output voltage IOH= −2.0 mA 2.4 −− V
LOW-level output voltage IOL= 1.6 mA −−0.4 V

= 15 pF); timing referred to LLD clock

L

HIGH-level output voltage IOH= −2.0 mA 2.4 −− V
LOW-level output voltage IOL= 1.6 mA −−0.4 V
output delay time see Fig.10 −−20 ns
output hold time see Fig.10 4 −− ns

Digital input/output signals: P1.1 to P1.5 and SNRST

V

OH

V

OL

V

IH

V

IL

HIGH-level output voltage IOH= −0.06 mA 2.4 −− V
LOW-level output voltage IOL= 1.6 mA 0 − 0.4 V
HIGH-level input voltage 2.0 − 5.5 V
LOW-level input voltage 0 − 0.8 V

Digital input signals: YI and UVI; timing referred to LLD clock

V
V
t

su(i)

t

h(i)

IH
IL

HIGH-level input voltage 2.0 − 5.5 V
LOW-level input voltage −−0.8 V
input set-up time see Fig.10 4 −− ns
input hold time see Fig.10 3 −− ns

1998 Jul 23 22

Philips Semiconductors Preliminary specification

Besic SAA4977H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital input signal: HA; timing referred to LLA clock (only when SELCLK = 0, HA used as digital horizontal
reference)

V

IH

V

IL

t

su(i)

t

h(i)

Digital input signals:

V

IH

V

IL

Digital input clock signal: LLA

f

LLA

δ

clk

V

IH

V

IL

t

r

t

f

Digital input clock signal: LLD

f

LLD

δ

clk

V

IH

V

IL

t

r

t

f

2

C-bus signal: SDA and SCL; note 3

I

V

IH

V

IL

V

OL

f

SCL

t

HD;STA

t

LOW

t

HIGH

t

SU;DAT

t

SU;DAT1

t

SU;DAT2

t

SU;STA

t

SU;STO

HIGH-level input voltage 2.0 − 5.5 V
LOW-level input voltage −−0.8 V
input set-up time see Fig.10 7 −− ns
input hold time see Fig.10 4 −− ns

TRST, TMS, RST and VA

HIGH-level input voltage 2.0 − 5.5 V
LOW-level input voltage −−0.8 V

sample clock frequency 14 16 34 MHz
clock duty factor 40 50 60 %
HIGH-level input voltage 2.4 −− V
LOW-level input voltage −−0.6 V
clock rise time see Fig.10 −−5ns
clock fall time see Fig.10 −−5ns

sample clock frequency 30 32 34 MHz
clock duty factor 40 50 60 %
HIGH-level input voltage 2.4 −− V
LOW-level input voltage −−0.6 V
clock rise time see Fig.10 −−5ns
clock fall time see Fig.10 −−5ns

HIGH-level input voltage 0.7V
LOW-level input voltage −−0.3V

−− V

DDIO

DDIO

V
LOW-level output voltage IOL= 3.0 mA −−0.4 V
SCL clock frequency −−400 kHz
hold time START condition 0.6 −− µs
SCL LOW time 1.3 −− µs
SCL HIGH time 0.6 −− µs
data set-up time 100 −− ns
data set-up time (before

0.6 −− µs

repeated START condition)
data set-up time (before STOP

0.6 −− µs

condition)
set-up time repeated START 0.6 −− µs
set-up time STOP condition 0.6 −− µs

1998 Jul 23 23

Philips Semiconductors Preliminary specification

Besic SAA4977H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SNERT-bus: SNDA and SNCL; note 4

V

OH

V

OL

V

IH

V

IL

t

su(i)

t

h(i)

t

cycle

t

h(o)

Notes

1. With AGC at −3 dB, U full ADC range is obtained at Vi= 1.89 V; with AGC at +6 dB, U full ADC range is obtained at
Vi= 0.67 V; with AGC at −3 dB, V full ADC range is obtained at Vi= 1.48 V; with AGC at +6 dB, V full ADC range is
obtained at Vi= 0.52 V.

2. Supply voltage ripple rejection, measured over a frequency range from 20 Hz to 50 kHz. This includes1⁄2fV, fV, 2fV,
fH and 2fH which are major load frequencies: SVR is relative variation of the full scale analog input for a supply
variation of 0.25 V.

3. The AC characteristics are in accordance with the I2C-bus specification for fast mode (clock frequency maximum
400 kHz). Information about the I2C-bus can be found in the brochure
9398 393 40011).

4. More information about the SNERT-bus protocol can be found in Application Note
(AN95127).

HIGH-level output voltage IOH= −2.0 mA 2.4 −− V
LOW-level output voltage IOL= 1.6 mA −−0.4 V
HIGH-level input voltage 2.0 − 5.5 V
LOW-level input voltage −−0.8 V
input set-up time 700 −− ns
input hold time 0 −− ns
SNCL cycle time − 1 −µs
output hold time 50 −− ns

“I2C-bus and how to use it”

(order number

“The SNERT-bus specification”

t

t

su(i)

r

t

h(i)

t

h(o)

handbook, full pagewidth

CLOCK

INPUT

DATA

OUTPUT

DATA

Fig.10 Timing diagram.

1998 Jul 23 24

t

d(o)

t

f

2.4 V

1.5 V

0.6 V

2.0 V

0.8 V

2.4 V

0.4 V

MGM597

Philips Semiconductors Preliminary specification

Besic SAA4977H

handbook, full pagewidth

1.00 V

INPUT 8 bit OUTPUT 10 bit

output_range = 1 output_range = 0

white 255

black 16

00

1023 1023

1.34 V

64

Fig.11 Luminance levels.

767

288
256

0

MGM598

11 APPLICATION

The SAA4977H supports two different up-converter concepts. The simple one is shown in Fig.12. In this application only
one field memory SAA4955TJ is needed for a 100 Hz conversion based on a field repetition algorithm (AABB mode).
The concept can be upgraded by a noise reduction based on a motion adaptive field recursive filter if the SAA4956TJ is
used instead of the SAA4955TJ.

The SAA4977H supports a dual-clock system. The acquisition clock is taken from the digital front-end. The display
control is based on a clock generated by an external H-PLL. By this structure the stability of the display is enhanced
compared to a one-clock system if an unstable source like a VCR is used as an input.

The second system supported by the SAA4977H is shown in Fig.13. This concept needs two field memories
(SAA4955TJ) and the signal processing IC MELZONIC (SAA4991WP). The SAA4991WP allows a vector based motion
estimation and compensation for a display of 100 Hz pictures in high-end TV sets which is free of motion artefacts.
It additionally provides a variable vertical zoom function, noise and cross colour reduction. Furthermore a multi-PIP
feature is supported making use of the field memories.

1998 Jul 23 25

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handbook, full pagewidth

D11

D10

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

YIN
UIN

VIN

+3.3 V

19, 22

3
4
5
6
7
8
9

SAA4955TJ

10
11
12
13
14

25
26

1, 2, 39, 40

+5 V

20, 21, 23

17, 18

(1)

17, 18, 19,
23, 25, 29,

46, 67

3 to 7,

10, 12,

13, 64, 66

n.c.

+5 V

45
44
43
42
41
40
39
38
37
36
35
34

79
76
74

71
72
70

10 µF

9

8.2 kΩ

D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

YOUT
UOUT
VOUT

1
2

SDA
SCL

HDFL
VDFL

+3.3 V

8, 11, 69,

75, 80

26
28
30

SWC

15

RSTW

16

WE

38
37
36
35
34
33
32
31
30
29
28
27

RE

24

HRD

47
24
32
51
52
53
54
55
56
57
58
59
60
61
62
63

20
22

68

SAA4977H

14 to 16,

21, 27, 31,

48 to 50,

33, 65, 73,

77, 78

VA

HA

(1) Alternatively SAA4956TJ.

Fig.12 Application diagram 1.

1998 Jul 23 26

DISPLAY

PLL

SRC

MGM599

Philips Semiconductors Preliminary specification

Besic SAA4977H

handbook, full pagewidth

YIN
UIN
VIN

D11
D10

D11
D10

26
28
30
47
24
32
51
52
53
54
55
56
57
58
59
60
61
62
63

12
13

20
22

68

+3.3 V

8, 11, 69,

75, 80

SAA4977H

14 to 16,

21, 27, 31,

48 to 50,

33, 65, 73,

77, 78

DISPLAY

PLL

41
40
38
37
36
35
34
33
32
31
30
29
28

11
64
66
67
68
69
70
71
72
73
74
75
76
77

2, 3, 5, 6, 7,

SWC

RSTW

WE

+5 V

1, 4, 20, 42,

46, 65, 78

SAA4991WP

22, 26, 27,
47, 60, 63,

79 to 84

8 to 10

62 45

48
49
50
51
52
53
54
55
56
57
58
59
61

44
43

25
24
23
21
19
18
17
16
15
14
13
12

D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

RE

SNDA
SNCL

n.c.

HRD

+3.3 V

+5 V

19, 22

20, 21, 23

15
3
4

D9

5

D8

6

D7

7

D6

8

D5

9

D4
D3
D2
D1
D0

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

SAA4955TJ

10
11
12
13
14

25
26

+3.3 V

19, 22

3
4
5
6
7
8
9

SAA4955TJ

10
11
12
13
14

25
26

FM1

1, 2, 39, 40

FM2

1, 2, 39, 40

17, 18

+5 V

20, 21, 23

17, 18

16

38

37

36

35

34

33

32

31

30

29

28

27

24

15

16

38

37

36

35

34

33

32

31

30

29

28

27

24

RE1

WE2

RE2

17, 18, 19,
23, 25, 29,

46, 67

3 to 7,

10, 64, 66

n.c.

+5 V

SRC

10 µF

9

8.2 kΩ

D11

45

D10

44

D9

43

D8

42

D7

41

D6

40

D5

39

D4

38

D3

37

D2

36

D1

35

D0

34
79

76
74

1
2

71
72
70

YOUT
UOUT
VOUT

SDA
SCL

HDFL
VDFL

VA

HA

Fig.13 Application diagram 2.

1998 Jul 23 27

MGM600

Philips Semiconductors Preliminary specification

Besic SAA4977H

12 PACKAGE OUTLINE

QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

c

y

X

Z

E

e

w M

p

A

A

H

E

E

2

A

A

1

64 41

65

pin 1 index

80

1

40

b

25

24

detail X

L

p

L

SOT318-2

(A )

3

θ

w M

b

e

p

Z

D

D

H

D

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

A

max.

3.2

0.25

0.05

2.90

2.65

0.25

0.45

0.30

0.25

0.14

UNIT A1A2A3bpcE

(1)

(1) (1)(1)

D

20.1

19.9

eH

H

14.1

13.9

24.2

0.8 1.95

23.6

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

IEC JEDEC EIAJ

REFERENCES

SOT318-2

1998 Jul 23 28

D

B

E

18.2

17.6

v M

A

v M

B

LL

p

1.0

0.6

0.20.2 0.1

EUROPEAN

PROJECTION

Z

D

1.0

0.6

Zywv θ

E

o

1.2

7

o

0.8

0

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Preliminary specification

Besic SAA4977H

13 SOLDERING

13.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(order code 9398 652 90011).

13.2 Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For details,
refer to the Drypack information in the

“Data Handbook
IC26; Integrated Circuit Packages; Section: Packing
Methods”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

.

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

13.4 Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

13.3 Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

1998 Jul 23 29

Philips Semiconductors Preliminary specification

Besic SAA4977H

14 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

15 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

16 PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1998 Jul 23 30

Philips Semiconductors Preliminary specification

Besic SAA4977H

NOTES

1998 Jul 23 31

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone]

Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545104/00/01/pp32 Date of release: 1998 Jul 23 Document order number: 9397 750 03258