Datasheet SAA2032GP Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA2032

Digital equalization for the tape
drive processing of the DCC system

Product specification
Supersedes data of February 1993
File under Integrated Circuits, Miscellaneous

Philips Semiconductors

February 1995

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

FEATURES

• Analog-to-digital conversion, demultiplexing,
equalization and zero crossing of time multiplexed
analog read amplifier signal

• Microcontroller interface

• Search mode envelope, label and virgin detection of the

AUX channel

• Search mode tape speed measurement

• Simplified external biassing

• Reduced power consumption

• Analog eye output

• 4 V nominal operating voltage capability.

ORDERING INFORMATION

GENERAL DESCRIPTION

Performing the Digital Equalizing function in the Digital
Compact Cassette (DCC) system, the SAA2032 is
intended for use in conjunction with the SAA2022, read
amplifier TDA1317 or TDA1318.

EXTENDED TYPE

NUMBER

SAA2032GP

Note

1. When using reflow soldering it is recommended that the Dry Packing instructions in the

are followed. The pocketbook can be ordered using the code 9398 510 34011.

PINS PIN POSITION MATERIAL CODE

44 QFP 1 plastic SOT205AG

PACKAGE

Quality Reference Pocketbook

February 1995 2

Philips Semiconductors Product specification

Digital equalization for the tape
drive processing of the DCC system

24f

VIN

43

5

CLOCK

GENERATION

V

DDAD

11 12

SAA2032

SAA2032

V

DD

3

RDCLK

2

RDSYNC

VIRGIN

LABEL

DETECTOR

SLICERFILTERDEMUXADC

37

36
38

22
23
24
25
26
27
28
29
30

LABEL

VIRGIN
AENV

CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AUX

LTENDEQ

LTCNT1
LTCNT0

LTCLK

1

44

DAC ANEYE

32
33
34
35

8, 14

V

SSA

LT

INTERFACE

V

SSAD

10

13, 17, 39

V

SS

15

31

MEA663

DIGEYE
VAL

LTDATA

Fig.1 Block diagram.

February 1995 3

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

PINNING

SYMBOL PIN DESCRIPTION

DIGEYE 1 serial data output for eye pattern
RDSYNC 2 SYNC data for Read Amplifier (push-pull output)
RDCLK 3 data clock for Read Amplifier (push-pull output)
TEST1 4 test 1; to be connected to V
VIN 5 analog time multiplexed input from Read Amplifier
REFN 6 lower reference voltage (+1 V) for ADC
REFP 7 upper reference voltage (+3.1 V) for ADC
V

SSA

8 analog ground (0 V)
BIASA 9 bias current for ADC (sinks current from V
V
V
V
V
V

SSAD

DDAD

DD

SS

SSA

10 supply ground (0 V) for ADC
11 supply voltage (+5 V) for ADC
12 supply voltage (+5 V)
13 supply ground (0 V)

14 supply ground (0 V)
ANEYE 15 analog eye voltage output
n.c. 16 not connected
V

SS

17 supply ground (0 V)
TEST4 18 test 4; do not connect
TEST5 19 test 5; do not connect
TEST6 20 test 6; do not connect
TEST7 21 test 7; do not connect
CH0 22 channel 0 output for SAA2022 (DCC Drive Signal Processing) (push-pull output)
CH1 23 channel 1 output for SAA2022 (push-pull output)
CH2 24 channel 2 output for SAA2022 (push-pull output)
CH3 25 channel 3 output for SAA2022 (push-pull output)
CH4 26 channel 4 output for SAA2022 (push-pull output)
CH5 27 channel 5 output for SAA2022 (push-pull output)
CH6 28 channel 6 output for SAA2022 (push-pull output)
CH7 29 channel 7 output for SAA2022 (push-pull output)
AUX 30 AUX channel output for SAA2022 (push-pull output)
LTDATA 31 microcontroller I/O data interface (3-state push-pull output and input; CMOS levels)
LTENDEQ 32 microcontroller interface enabling (CMOS input levels)
LTCNT1 33 microcontroller interface; mode control 1 (CMOS input levels)
LTCNT0 34 microcontroller interface; mode control 0 (CMOS input levels)
LTCLK 35 microcontroller bit-clock interface (CMOS input levels)
VIRGIN 36 search mode virgin detection output
LABEL 37 search mode label detection output
AENV 38 search mode auxiliary detection output
V

SS

39 supply ground (0 V)

SS

via 33 kΩ)

DDAD

February 1995 4

Philips Semiconductors Product specification

Digital equalization for the tape
drive processing of the DCC system

SYMBOL PIN DESCRIPTION

TEST8 40 test 8 input; to be connected to V
TEST9 41 test 9 input; to be connected to V
TEST10 42 test 10 input; to be connected to V
f24 43 clock input; typical frequency 24.576 MHz (CMOS input)
VAL 44 synchronization output for DIGEYE

f24

TEST10

DIGEYE

RDSYNC

RDCLK
TEST1

VIN
REFN
REFP

V

SSA

BIASA

V

SSAD

V

DDAD

VAL
44

43

1
2

3
4
5

6

7

8

9

10
11

42

TEST9

TEST8

41

40

SAA2032

SS

SS

SS

SS

AENV

V

39

38

LABEL

37

LTCLK

VIRGIN

36

35

LTCNT0

34

33
32
31
30
29
28
27
26
25
24
23

SAA2032

LTCNT1
LTENDEQ
LTDATA
AUX
CH7
CH6
CH5
CH4
CH3
CH2
CH1

15

14

SSA

V

16

n.c.

ANEYE

12

13

SS

DD

V

V

Fig.2 Pin configuration.

February 1995 5

18

20

22

19

TEST5

21

TEST7

TEST6

MEA661

CH0

17

SS

V

TEST4

Philips Semiconductors Product specification

Digital equalization for the tape
drive processing of the DCC system

write

and

heads

drive

capstan

TDA1319

TDA1316 or

speed control

tape

SAA2032

SAA2022

read

TDA1317 or

digital

equalizer

TDA1318

RAM

256 kbits

SAA2032

TAPE DRIVE PROCESSING

MEA695 - 2

ADC

SAA7360

codec

stereo filter

2

I S

DAC

2

I S

(sub-band)

SAA2002

SAA7323

SAA2012

DAIO

TDA1315

adaptive

scale factors

allocation and

MICROCONTROLLER

Fig.3 DCC data flow diagram.

RECORDING + PLAY BACK

input

analog

output

analog

digital input

digital output

February 1995 6

AUDIO INPUT/OUTPUT PASC PROCESSING

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

FUNCTIONAL DESCRIPTION
Operating Modes

DEQ operating modes are programmed via the LT
interface:

ORMAL

N

• A/D conversion

• Demultiplexing

• Equalization

• Zero crossing.

in this mode the SAA2032 performs the equalization and
slicing of the eight data channels and the auxiliary channel.
The eight data channels have a bit-rate of 96 kbits/s while
the auxiliary channel has a bit-rate of 12 kbits/s.

The SAA2032 input is a time-multiplexed analog signal
from the Read Amplifier. The signal contains ten time slots,
of which nine are used. The Read Amplifier and the
SAA2032 synchronize with the RDCLK and RDSYNC
signals generated by the SAA2032.

Following A/D conversion and demultiplexing the nine
channels are equalized. The encoding of the equalizing
coefficients (12 per channel) are not fixed and must be
loaded via the LT interface before operation.

The nine equalized output signals are up-sampled by a
factor of 10 with the resulting signals fed to the slicer. The
slicer output is applied to the SAA2022.

EST

T

• A/D conversion

• Demultiplexing

• Equalization

• Zero crossing

• Eye-pattern.

Same as normal mode. In addition the digital and analog
eye-pattern outputs are enabled. The eye-pattern output
corresponds to one of the equalized channel outputs.

EARCH

S

• A/D conversion

• Envelope detection

• Tape search and speed measurement.

In the search mode the analog input signal from the Read
Amplifier is not the multiplexed signal but only the auxiliary
channel signal.

Following A/D conversion the envelope of this signal is
filtered and sliced. This forms the Alternating Envelope
AENV output. The LABEL and VIRGIN outputs are
detected from this and the tape search speed measured.

FF

O
In the OFF mode the RDSYNC and RDCLK signals are

HIGH, the EYE outputs are disabled and the channel and
auxiliary outputs (CH0 to CH7 and AUX) are 3-stated.

Read Amplifier interface

The interface between the Read Amplifier and the
SAA2032 consists of three signals:

1. VIN from Read Amplifier to SAA2032; time
multiplexed data.

2. RDSYNC from SAA2032 to Read Amplifier;
synchronization between Read Amplifier multiplexer
and SAA2032 demultiplexer.

3. RDCLK from SAA2032 to Read Amplifier; data clock
for Read Amplifier multiplexer.

The multiplexed VIN output of the Read Amplifier changes
to another channel at the rising edge of RDCLK. RDSYNC
synchronizes the Read Amplifier VIN output: if RDSYNC is
HIGH, the rising edge of the RDCLK will select the AUX
channel.

Figures 4 and 5 show the relationship between the
SAA2032 and the Read Amplifier.

SAA2022 interface

The interface with the SAA2022 consists of the 9 data
output signals CH0 to CH7, AUX.

Table 1 Dependency of Read Amplifier on

operational mode.

OPERATIONAL MODE RDSYNC RDCLK

Normal YES YES
Test YES YES
Search HIGH YES
Off HIGH HIGH

Label and virgin detection interface

When the DCC player is in its search mode, the tape is
fast-wound while the head retains tape contact. The
SAA2032 can be made to operate in the search mode and
the information will be read from the auxiliary tape track.

February 1995 7

Philips Semiconductors Product specification





Digital equalization for the tape

SAA2032

drive processing of the DCC system

The following three signals are generated:

1. LABEL: label detection (HIGH if label is detected).

2. VIRGIN: virgin tape detection (HIGH if virgin tape
is detected).

3. AENV: alternating envelope (sliced envelope).

AENV, LABEL and VIRGIN are disabled in normal or off
modes. LABEL, VIRGIN and AENV are LOW.

AENV, LABEL and VIRGIN are enabled when the
SAA2032 is in search mode.

The device detects the envelope AENV of the auxiliary
track at search speeds between 3 and 50 times normal
speed. If AENV is continuously HIGH (label detection),
LABEL will be HIGH.

When AENV is continuously LOW (virgin tape detection)
VIRGIN will be HIGH.
Figures 6, 7 and 8 show the relationship between AENV,
VIRGIN and LABEL.

Labelled tape-speed calculation

When the DCC player is in its search mode, the tape
speed increases. LABEL information is encoded
throughout its length. To examine the length of a label, the

tape speed must be known. In search mode the SAA2032
assesses the speed of labelled tapes. The microcontroller
obtains this information via the LT-interface.

The speed information is encoded in 3 variables:

1. SVF Speed Validation Flag (HIGH if invalid).

2. SC (4..0) Speed counter.

3. SR (1..0) Speed Range.

51.2

SR

-----------

Search speed 2

×= x normal speed.

SC

If SC = 0 then search speed > 51.2.
With SR = 0, 1, 2 or 3 and SC = 0 to 31.
If SVF = 1 then SR and SC values are invalid.
Appendix 1 gives a table of the search mode speed

control.

Microcontroller (LT) Interface

The SAA2032 is able to exchange information with the
microcontroller via the LT-interface. The microcontroller
performs as master, the SAA2032 as slave.

Figure 9 gives the operation of the LT-interface.

RDCLK

VIN

RDSYNC

CH7 AUX

CH0 CH3 CH4 CH5 CH6 CH7 AUX

***

Fig.4 Signals on interface between Read Amplifier and SAA2032.

February 1995 8

***

CH0CH2CH1 CH1

MCD477

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

RDCLK

t

su

VIN

VIN

stable

MCD478

tsu > 80 ns; set-up time VIN before RDCLOCK HIGH.
Typical frequency for RDCLK = 3.072 MHz.
Typical frequency for RDSYNC = 307.2 kHz.

Fig.5 Timing.

signal
from
tape

t

d2

AENV

t

d1

MCD488 - 1

td1 = td2 = between 0.5 and 1.0 auxiliary block lengths.

Fig.6 Diagram of AENV signal.

February 1995 9

Philips Semiconductors Product specification

Digital equalization for the tape
drive processing of the DCC system

AENV

LABEL

t

d3

SAA2032

t

d4

MLA635 - 2

td3 = between 4 and 12 auxiliary blocks.
td4 = between 4 and 12 auxiliary blocks.

AENV

VIRGIN

Fig.7 AENV and LABEL signals.

t

d5

t

d6

MLA634 - 2

td5 = td6 = between 4 and 12 auxiliary blocks.

Fig.8 AENV and VIRGIN signals.

February 1995 10

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

LTENDEQ

LTCNT 0/1

LTCLK

LTDATA

01234567

LSB MSB

MCD479

Fig.9 Typical operation of the LT-interface.

LTCNT specification
Table 2 Four types of data exchange performed on the interface.

LTCNT1 LTCNT0 LT DATA EXCHANGE MODE FROM TO

0 0 data write µC DEQ
0 1 data read DEQ µC
1 0 address write µC DEQ
1 1 mode settings write µC DEQ

February 1995 11

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

Mode Settings Load (LTCNT = 11) (See Fig.10)
The 8-bits transmitted under ’mode settings load’ control

both the ’operation mode’ and the ’data exchange type’.

Table 3 Mode settings; ’operation mode’.

a1 a0 OPERATION MODE

0 0 normal
0 1 test
1 0 search
1 1 off

Table 4 Mode settings; ’data exchange type’.

b1 b0 DATA EXCHANGE TYPE

0 0 write coefficient data
0 1 read coefficient data
1 1 read envelope data

Remark post condition: after every communication
sequence the data exchange type must be set to “read
coefficient data”.

Address Information Load (LTCNT = 10) (See Fig.11)
A channel/tap combination can be selected through this

type of data exchange.
Co-efficient Data Load (LTCNT = 00) (See Fig.12)

This type of data exchange will overwrite the equalizer tap
coefficient of the current selected channel/tap
combination.

The coefficient data for tap <0000> of the auxiliary channel
should always be zero.

Data Read (LTCNT = 01) (See Fig.13)
This type of data exchange will send information from the

LTDATA register in the SAA2032 to the microcontroller.
Data in the LTDATA register depends upon the current
data exchange type.

LTDATA interpretation:

• coefficient data: two’s complement coefficient data

• tape speed data

– d7 = SVF flag
– d6 to d2 = SC4 to SC0
– d1, d0 = SR1, SR0.

Tape speed data format is shown in Fig.14.

MSB LSB

****

b1 b0 a1 a0

data 

exchange

type

operation

mode

Fig.10 Mode settings load (LTCNT = 11).

MCD480

February 1995 12

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

c3 c2 c1 c0 t3 t2 t1 t0

MSB LSB

c3 to c0 --> channel number <0000 to 0111>
+ auxiliary channel <1000>
t3 to t0 --> tap number <0000 .. 1011>

Fig.11 Address information load (LTCNT = 10).

d7 d6 d5 d4 d3 d2 d1 d0

MSB LSB

MCD481

MCD483

d7 d6 d5 d4 d3 d2 d1 d0

MSB LSB

Fig.12 Coefficient data load (LTCNT = 00).

d7

SVF SC (h. . .0)

d0

SR (1. . .0)

MCD482

MBC381

Fig.13 Read data (LTCNT = 01).

February 1995 13

Fig.14 Tape speed data format.

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

t

Le

LTENDEQ

t

su2

t

h1

t

su3

t

h3

0

LTCNT0/1

LTCLK

LTDATA

bit

t

su4

t

su1

tLe > 120 ns; minimum LOW time LTENDEQ before transfer.
t

> 20 ns; set-up time LTCNT0/1 before LTENDEQ HIGH.

su1

th1 > 100 ns; hold time LTCNT0/1 after LTENDEQ HIGH.
t

≥ 0 ns; set-up time LTCNT0/1 before LTCLK LOW.

su2

th2 > 20 ns; hold time LTENDEQ after LTCLK HIGH.
tLc > 120 ns; minimum LOW time LTCLK.
tHc > 120 ns; minimum HIGH time LTCLK.
t

> 200 ns; set-up time LTCLK before LTENDEQ HIGH.

su4

t

> 100 ns; set-up time LTDATA before LTCLK HIGH.

su3

th3 > 20 ns; hold time LTDATA after LTCLK HIGH.

t

h2

t

Lc

t

Hc

1

MCD485 - 1

Fig.15 Microcontroller to SAA2032 timing.

February 1995 14

Philips Semiconductors Product specification

Digital equalization for the tape
drive processing of the DCC system

t

Le

LTENDEQ

t

su2

t

h1

t

d1

LTCNT0/1

LTCLK

LTDATA

bit

t

su4

t

su1

SAA2032

t

h2

t

Lc

t

d2

0

t

Hc

t

h5

1

t

h6

MCD486 - 1

tLe > 120 ns; minimum LOW time LTENDEQ before transfer.
t

> 20 ns; set-up time LTCNT0/1 before LTENDEQ HIGH.

su1

th1 > 100 ns; hold time LTCNT0/1 after LTENDEQ HIGH.
t

≥ 0 ns; set-up time LTCNT0/1 before LTCLK LOW.

su2

th2 > 20 ns; hold time LTENDEQ after LTCLK HIGH.
tLc > 120 ns; minimum LOW time LTCLK.
tHc > 120 ns; minimum HIGH time LTCLK.
t

> 200 ns; set-up time LTCLK before LTENDEQ HIGH.

su4

td1 > 300 ns; maximum delay LTDATA after LTENDEQ HIGH.
td2 > 400 ns; maximum delay LTDATA after LTCLK HIGH.
th5 > 160 ns; hold time LTDATA after LTCLK HIGH.
th6 > 0 ns; hold time LTDA after LTENDEQ LOW.

Fig.16 SAA2032 to Microcontroller timing.

February 1995 15

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

Eye pattern output

To test equalization performance it is possible to output the
equalized channels. For this purpose one analog and two
digital output signals are provided. Selection of the EYE
pattern output is determined by the last channel address
sent to the SAA2032.

• DIGEYE: serial data line for 8-bits output value

• VAL: validation signal for data bits

• ANEYE: analog eye voltage output.

The eye outputs are enabled in test mode.

t

VAL

RDCLK

Table 5 Eye outputs.

OPERATION MODE DIGEYE ANEYE

Normal LOW HIGH
Test ENABLED ENABLED
Search LOW HIGH
Off LOW HIGH

The internal number representation in the SAA2032 is in
two's complement. The format of the selected 8-bits will be
converted to the off-set-binary format. This means that the
MSB of the two's complement number has been inverted.
This 8-bit number is shifted out via the DIGEYE output.

Figure 17 gives the eye pattern output timing.

t

eye

val

DIGEYE

LSB

RDCLK

t

t

DIGEYE

stable

data

t

= 1/4 clock period; pulse width HIGH.

val

h

clk

tsu > 60 ns; minimum set-up time data before clock.
th > 5 ns; minimum hold time data after clock.
t

= 1/f

clk

f

clk

t

eye

f

eye

.

clk

= 3.072 MHz; nominal DIGEYE clock frequency.

= 1/f

eye

.

= 307.2 kHz; nominal DIGEYE clock frequency.

Fig.17 Timing diagram.

MSB

(inverted)

t

su

LSB

MEA662 - 1

February 1995 16

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

V

I

I

SS

I

DD

I

I

I

O

P

tot

T

stg

T

amb

V

es1

V

es2

supply voltage −0.5 +6.5 V
input voltage note 1 −0.5 VDD + 0.5 V
supply current in V
supply current in V

SS

DD

−−100 mA

− 100 mA

input current −10 10 mA
output current −20 20 mA
total power dissipation − 550 mW
storage temperature −55 +150 °C
operating ambient temperature −40 +85 °C
electrostatic handling note 2 −1500 +1500 V
electrostatic handling note 3 −70 +70 V

Notes

1. Input voltage should not exceed 6.5 V unless otherwise specified.

2. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

3. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.

DC CHARACTERISTICS

V

= 3.8 to 5.5 V; T

DD

= −40 to +85 °C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DD

V

DDAD

I

DD

I

DDAD

I

OP

supply voltage 3.8 5.0 5.5 V
supply voltage for ADC note 1 3.8 5.0 5.5 V
supply current VDD= 5 V; note 2 − 22 26 mA

= 3.8 V; note 2 − 12 14 mA

V

DD

supply current for ADC V

= 5 V − 11 13 mA

DDAD

= 3.8 V − 57mA

V

DDAD

operating current note 3 1.3 1.9 3.4 mA

Inputs f24, LTCLK, LTCNT0, LTCNT1 and LTENDEQ

V

IL

V

IH

I

I

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V
input current VI = 0 V; T

V

= VDD; T

I

= 25 °C −−−10 µA

amb

= 25 °C −−10 µA

amb

DD

− V

DD

DD

Input REFP

V

refp

reference voltage 2.7 3.1 3.4 V

Input REFN

V

refn

reference voltage 0.7 1.0 1.4 V

V
V

February 1995 17

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Inputs REFP and REFN

∆V

ref

Input VIN

V

I(p-p)

I

I

Digital outputs

V

OL

V

OH

Output ANEYE

V

O

V

O

Input/output LTDATA

V

OL

V

OH

I

OZ

V

IL

V

IH

reference voltage difference

2 2.1 2.7 V

between REFP and REFN

input voltage (peak-to-peak) V

refn

− V

refp

input current −−100 µA

LOW level output voltage note 4 −−0.4 V
HIGH level output voltage note 4 VDD − 0.5 −−V

output voltage note 4 −−V

DDAD

output voltage range note 4 − 1.1 − V

LOW level output voltage IO = −3mA −−0.4 V
HIGH level output voltage IO = 2 mA VDD − 0.5 −−V
leakage current with outputs

in 3-state
LOW level input voltage −−0.3V

HIGH level input voltage 0.7V

VI = 0 V; T

= VDD; T

V

I

= 25 °C −−10 µA

amb

= 25 °C −−10 µA

amb

DD

−−V

DD

V

V

V

Notes

1. V

should never be lower than VDD− 0.2 V.

DDAD

2. For load impedances in a typical application circuit.

3. Operating reference current for the specified range of V

allowing for the tolerance on the internal resistor.

refp

4. For outputs DIGEYE, RDSYNC, RDCLK, CH0 to CH7, AUX and VAL the maximum load current is 1 mA. For ANEYE

output the maximum load current is 10 µA. For VIRGIN, LABEL and AENV the maximum load current is 2 mA.

February 1995 18

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

AC CHARACTERISTICS

V

= 3.8 to 5.5 V; T

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VIN

C

i

input capacitance −−15 pF

All digital inputs

C

i

input capacitance −−10 pF

Clock input f24

f clock frequency 23 24.576 26 MHz
t

p

pulse width LOW or HIGH 10 −−ns

Inputs LTCLK, LTENDEQ, LTCNT0 and LTCNT1

t

su

t

h

set-up time to f24 note 1 10 −−ns
hold time from f24 note 1 30 −−ns

All outputs

C

i

C

L

t

d

input capacitance −−10 pF
load capacitance −−50 pF
propagation delay time from f24 note 1 −−80 ns

Input/output LTDATA

C

i

C

L

t

d

t

su

t

h

input capacitance −−10 pF
load capacitance −−50 pF
propagation delay time from f24 −−80 ns
set-up time to f24 note 1 10 −−ns
hold time from f24 note 1 30 −−ns

= −40 to 85 °C; unless otherwise specified.

amb

Note

1. LOW-to-HIGH transition.

February 1995 19

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

CONVERTER CHARACTERISTICS

V

= 3.8 to 5.5 V; T

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog-to-Digital Converter; VIN

resolution − 7 − bits
conversation data available after − 2 × t
effective input bandwidth 6-bit resolution

differential non-linearity −−
V
V
∆V

refn

refp

ref

reference voltage at VREFN note 1 0.7 1.0 1.4 V

reference voltage at VREFP 2.7 3.1 3.4 V

reference voltage difference

between REFP and REFN
V

i

input voltage V
S+THD/N signal-to-total harmonic

distortion and noise ratio
C

i

I

I

input capacitance −−15 pF

input current (DC) note 3 −−100 µA

Digital-to-analog converter; output ANEYE

resolution − 6 − bits
V

O

V

O

output voltage note 4 −−V

output voltage range note 4 − 1.1 − V

= −40 to 85 °C; unless otherwise specified.

amb

at f

= 3.1 MHz

s

note 2 21 −−dB

−

cy

0.5 −−MHz

±0.99

LSB

2 2.1 2.7 V

refn

− V

refp

DDAD

V

V

Notes

1. V

is supplied externally.

refp

V

is derived internally and set to

refn

V

must be decoupled externally at pin 6 via a 100 nF capacitor.

refn

1

/

V

.

3

refp

2. Signal level (fs) −20 dB, at any DC level within the input voltage range.

3. The output impedance of the analog input signal source must be <150 Ω.

4. Load impedance ≥1MΩ.

February 1995 20

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

APPENDIX 1
Search Mode Speed Control Interface

In search mode the SAA2032 measures the tape speed. The tape speed is encapsulated in the variables:

• SVF Speed Validation Flag; is HIGH if NOT valid

• SC Speed Counter

• SR Speed Range.

The values in Table 6 represent the speed in multiples of the nominal tape speed of 4.76 cm/s.

Table 6 Speed in multiples of nominal tape speed.

SC[4 .. 0]

0123

0 >51.20 >102.40 >204.80 >409.60
1 51.20 102.40 204.80 409.60
2 25.60 51.20 102.40 204.80
3 17.07 34.13 68.27 136.53
4 12.80 25.60 51.20 102.40
5 10.24 20.48 40.96 81.92
6 8.53 17.07 34.13 68.27
7 7.31 14.63 29.26 58.51
8 6.40 12.80 25.60 51.20

9 5.69 11.38 22.76 45.51
10 5.12 10.24 20.48 40.96
11 4.65 9.31 18.62 37.24
12 4.27 8.53 17.07 34.13
13 3.94 7.88 15.75 31.51
14 3.66 7.31 14.63 29.26
15 3.41 6.83 13.65 27.31
16 3.20 6.40 12.80 25.60
17 3.01 6.02 12.05 24.09

SR[1 .. 0]

REMARKS

shift to higher speed range

normal working area

February 1995 21

Philips Semiconductors Product specification

Digital equalization for the tape
drive processing of the DCC system

SR[1 .. 0]

SC[4 .. 0]

0123

18 2.84 5.69 11.38 22.76
19 2.69 5.39 10.78 21.56
20 2.56 5.12 10.24 20.48
21 2.44 4.88 9.75 19.50
22 2.33 4.65 9.31 18.62
23 2.23 4.45 8.90 17.81
24 2.13 4.27 8.53 17.07
25 2.05 4.10 8.19 16.38
26 1.97 3.94 7.88 15.75
27 1.90 3.79 7.59 15.17
28 1.83 3.66 7.31 14.63
29 1.77 3.53 7.06 14.12
30 1.71 4.41 6.83 13.65
31 1.65 3.30 6.61 13.21

SAA2032

REMARKS

shift to lower speed range

February 1995 22

Philips Semiconductors Product specification

Digital equalization for the tape
drive processing of the DCC system

PACKAGE OUTLINE

seating plane

44

1

pin 1 index

0.15

19.2

18.2

S

SAA2032

S

34

2.4

33

1.8

1.0

(4x)

14.1

13.9

B

19.2

18.2

0.15 M B

2.4

1.8

A

23

(4x)

detail X

0.50

0.35

2.0

1.2

1.2

0.9

X

o

0 to 7

MBC659 - 1

2.60

2.15

0.25

0.14

11

2.3

2.1

22

0.25

0.05

12

1.0

0.50

0.35

14.1

13.9

0.15 M A

Dimensions in mm.

Fig.18 44-lead quad flat-pack; plastic (SOT205AG).

February 1995 23

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

SOLDERING
Quad flat-packs

YWAVE

B
During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended
using two waves (dual-wave), in which, in a turbulent wave
with high upward pressure is followed by a smooth laminar
wave. Using a mildly-activated flux eliminates the need for
removal of corrosive residues in most applications.

Y SOLDER PASTE REFLOW

B
Reflow soldering requires the solder paste (a suspension

of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and vapour­phase reflow. Dwell times vary between 50 and 300 s
according to method. Typical reflow temperatures range
from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

R

IRON OR PULSE

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

-HEATED SOLDER TOOL)

February 1995 24

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress rating only and operation of
the device at these or at any other conditions above those given in the Characteristics sections of the specification is
not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.

February 1995 25

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

NOTES

February 1995 26

Philips Semiconductors Product specification

Digital equalization for the tape

SAA2032

drive processing of the DCC system

NOTES

February 1995 27

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]

Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]

Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,

Tel. [phone], Fax. [phone]

Brazil: Rua do Rocio 220 - 5

CEP: 04552-903-SÃO PAULO-SP, Brazil.
P.O. Box 7383 (01064-970).
Tel. [phone], Fax. [phone]

Canada: INTEGRATED CIRCUITS:

Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 601 Milner Ave,
SCARBOROUGH, ONTARIO, M1B 1M8,
Tel. [phone] ext. 2336, Fax. [phone]

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Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

France: 4 Rue du Port-aux-Vins, BP317,

92156 SURESNES Cedex,
Tel. [phone], Fax. [phone]

Germany: P.O. Box 10 63 23, 20095 HAMBURG ,

Tel. [phone], Fax. [phone]

Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. [phone] 911, Fax. [phone]

Hong Kong: 15/F Philips Ind. Bldg., 24-28 Kung Yip St.,

KWAI CHUNG, Tel. [phone], Fax. [phone]

India: PEICO ELECTRONICS & ELECTRICALS Ltd.,

Components Dept., Shivsagar Estate, Block 'A',
Dr. Annie Besant Rd., Worli, BOMBAY 400 018,
Tel. [phone], Fax. [phone]

Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,

P.O. Box 4252, JAKARTA 12950,
Tel. [phone], Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]

Italy: Viale F. Testi, 327, 20162 MILANO,

Tel. [phone], Fax. [phone]

Japan: Philips Bldg13-37 , Kohnan 2-chome, Minato-ku, KOKIO 108,

Tel. [phone], Fax. [phone]

Korea: (Republic of) Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: Philips Components, 5900 Gateway East, Suite 200,

EL PASO, TX 79905, Tel. [phone], Fax. [phone]

Netherlands: Postbus 90050, 5600 PB EINDHOVEN,

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

th

floor, Suite 51,

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Tel. [phone], Fax. [phone]

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,

106 Valero St. Salcedo Village, P.O. Box 911, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. [phone], Fax. [phone]

Taiwan: 69, Min Sheng East Road, Sec 3, P.O. Box 22978,

TAIPEI 10446, Tel. [phone], Fax. [phone]

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60/14 MOO 11, Bangna - Trad Road Km. 3
Prakanong, BANGKOK 10260,
Tel. [phone] to 9, (2)398-2083, Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 LEVENT/ISTANBUL,

Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Limited, P.O. Box 65,

Philips House, Torrington Place, LONDON, WC1E 7HD,
Tel. [phone], Fax. [phone]

United States:INTEGRATED CIRCUITS:

811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,
P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. [phone] and [phone], Fax. [phone]

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. [phone], Fax. [phone]

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD28 © Philips Electronics N.V. 1994

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
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notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Philips Semiconductors