Datasheet SAA2003H Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAA2003

Stereo filter and codec

Preliminary specification
File under Integrated Circuits, IC01

Philips Semiconductors

May 1994

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

FEATURES

• Single-chip stereo filter and codec

• Wide operating voltage range: 2.7 to 5.5 V

• Low-power consumption: 98 mW; 3.0 V

• Sleep mode for low power and low Electromagnetic

Interference (EMI)

• Transparent serial audio data mode in sleep

• IEC 958 digital output

• Peak level detector for start of track detection or

VU meter

• Versatile fade processor; slow/fast fade, mute,
12 dB attenuation

2

• Serial audio interface for I

S or EIAJ formats

GENERAL DESCRIPTION

The SAA2003 performs the sub-band filtering and audio
frame codec functions in the Precision Adaptive Sub-band
Coding (PASC) system. It can be used as a stand-alone
decoder for playback only applications, but requires the
addition of an Adaptive Allocation and Scale Factor
processor (SAA2013) in order to perform PASC encoding
in a DCC record system.

• Error concealment

• Three-wire L3 bus microcontroller interface

• Three sample rates:

– 32 kHz
– 44.1 kHz
– 48 kHz

• Internal or external clock source

• Three programmable outputs

• Small surface mounted package (SOT307).

ORDERING INFORMATION

EXTENDED TYPE

NUMBER

SAA2003H 44 QFP

Note

1. When using reflow soldering it is recommended that the Dry Packing instructions in the

Pocketbook”

are followed. The pocketbook can be ordered using the code 9398 510 34011.

PINS PIN POSITION MATERIAL CODE

(1)

PACKAGE

plastic SOT307

“Quality Reference

May 1994 2

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

BLOCK DIAGRAM

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TEST0
TEST1

IECOP

WS

SCK

SD1
SD2

19
20

29

36
35
34
33

X22OUT

X22IN

651094113738 287 39

IEC 958
OUTPUT

BASEBAND

SERIAL

INTERFACE

AND

PEAK

DETECTOR

STEREO SUBBAND

FILTER PROCESSOR

27 8 40

X24OUT

X24IN

CLOCK GENERATOR

FS128

CLK22

6.15 MHz

FS256

43 2 3 44 1

SBMCLK

FILTERED DATA

INTERFACE

CLK24

FS256

X256

SAA2003

V

DD1VDD2VDD3

SUBBAND

SERIAL

INTERFACE

PASC CODEC

PROCESSOR

MICROCONTROLLER

INTERFACE AND CONTROL

17 18 14 15 16 41 42

32
31
30

25
24
23
22
26

21
13
12

MUTEDAC
ATTDAC
DEEMDAC

SBWS
SBCL
SBDA
SBDIR
SBEF

URDA
RESET
SLEEP

MBD618

V

SS1VSS2VSS3

FDCL

FSYNC

FDWS

FDAO

FDAI

Fig.1 Block diagram.

May 1994 3

L3DATA L3MODE SYNCDAILTCNT0

L3CLK FDIRLTCNT1

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

PINNING

SYMBOL PIN DESCRIPTION TYPE

FDAI 1 filtered data input from SAA2013 I
FDCL 2 filtered data bit clock O
FDWS 3 filtered data word select O
CLK22 4 22.5792 MHz buffered clock output O
X22OUT 5 22.5792 MHz crystal output O
X22IN 6 22.5792 MHz crystal input I
V

DD2

V

SS2

X24OUT 9 24.576 MHz crystal output O
X24IN 10 24.576 MHz crystal input I
CLK24 11 24.576 MHz buffered clock output O
SLEEP 12 sleep mode; device inactive I
RESET 13 device reset I
L3DATA 14 3-wire interface; serial data I/O
L3CLK 15 3-wire interface; bit clock I
L3MODE 16 3-wire interface; mode control I
LTCNT0 17 LT interface; control bit 0 I
LTCNT1 18 LT interface; control bit 1 I
TEST0 19 test mode select I
TEST1 20 test mode select I
URDA 21 unreliable data flag from drive processor I
SBDIR 22 sub-band data direction I
SBDA 23 sub-band serial data I/O
SBCL 24 sub-band bit clock I/O
SBWS 25 sub-band word select I/O
SBEF 26 sub-band error flag from drive processor I
V

SS1

V

DD1

IECOP 29 IEC 958 digital audio output O
DEEMDAC 30 DAC control or general purpose output O
ATTDAC 31 DAC control or general purpose output O
MUTEDAC 32 DAC control or general purpose output O
SD2 33 serial audio data to DAC O
SD1 34 serial audio data to/from DAIO and DAC I/O
SCK 35 serial audio data bit clock I/O
WS 36 serial audio data word select I/O
X256 37 master audio clock from external source I
FS256 38 master audio clock at 256 times sample frequency O
V

DD3

V

SS3

7 supply voltage (clock oscillator) −
8 supply ground (clock oscillator) −

27 digital supply ground −
28 digital supply voltage −

39 supply voltage (FS256) −
40 supply ground (FS256) −

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Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

SYMBOL PIN DESCRIPTION TYPE

FDIR 41 filter direction; encode or decode O
SYNCDAI 42 settings synchronization for DAIO O
FSYNC 43 sub-band 0 sample synchronization for SAA2013 O
FDAO 44 filtered data output to SAA2013 O

SS3

FDAO
44

FSYNC

SYNCDAI

43

42

FDIR
41

DD3

FS256

V

40

X256

V

39

38

37

WS
36

SCK
35

SD1
34

FDAI

FDCL

FDWS

CLK22

X22OUT

X22IN

V

DD2

V

SS2

X24OUT

X24IN

CLK24

1
2
3
4
5
6
7
8
9

10

11

12

13

SLEEP

RESET

14

15

L3CLK

L3DATA

SAA2003

16

17

LTCNT0

L3MODE

18

19

TEST0

LTCNT1

20

TEST1

21

URDA

22

SBDIR

SD2

33

MUTEDAC

32

ATTDAC

31

DEEMDAC

30

IECOP

29

V

28

V

27
26

SBEF
SBWS

25

SBCL

24
23

SBDA

MBD619

DD1
SS1

Fig.2 Pin configuration.

May 1994 5

May 1994 6

FUNCTIONAL DESCRIPTION

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

RAM

41464

analog

output

analog

input

IEC958

analog CC

L output

analog CC

R output

L

DAC

TDA1305

R

SFC3
SAA2003
STEREO

FILTER CODEC

2

ADAS3

SAA2013

ADAPTIVE

ALLOCATION

L

R

baseband

I S

ADC

SAA7366

DIGITAL

AUDIO I/O

TDA1315

2

filtered I S

AUDIO IN/OUT PASC PROCESSOR

sub-band

2

I S

BUFFER

64K x 4

DRP

SAA2023

OR

SAA3323

DRIVE

PROCESSOR

search data

TAPE DRIVE PROCESSING

speed control

WRAMP

TDA1381

WRITE AMP.

RDAMP

TDA1380

READ AMP.

FIXED
HEAD

CAPSTAN

DRIVE

TAPE

MECHANICS

DRIVERS

detect
switch

Fig.3 DCC system block diagram.

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SYSTEM

MICROCONTROLLER

SYSTEM CONTROL

MBD620

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

PASC processor

The PASC processor is a dedicated Digital Signal
Processor (DSP) engine which efficiently codes digital
audio data at a bit rate of 384 kbits/s without affecting the
sound quality. This is achieved using an efficient adaptive
data notation and by only encoding the information which
can be heard by the human ear.

The audio data is split into 32 equal sub-bands during
encoding. For each of the sub-bands a masking threshold
is calculated. The samples from each of the sub-bands are
included in the PASC data with an accuracy that is
determined by the available bit-pool and by the difference
between the signal power and the masking threshold for
that sub-band.

The stereo filter codec performs the splitting (encoding)
and reconstruction (decoding), including the necessary
formatting functions. During encoding, the adaptive
allocation and scaling circuit calculates the required
accuracy (bit allocation) and scale factors of the sub-band
samples.

E

NCODING (SEE FIG.4)

The incoming serial audio data is filtered into 32 sub-bands
for left and right (I and II) channels using the stereo filter
part of the SAA2003. A PASC frame is made up of left and

right (I and II) audio data for 12 samples from each of the
32 sub-bands, a total of 768 audio samples. For every
PASC frame the SAA2013 calculates a bit allocation and
scale factor table which is transferred to the SAA2003. All
the samples in a frame are scaled in accordance with the
scale factor calculated by the SAA2013. Once scaled the
samples are re-quantized to reduce the number of bits to
correspond with the allocation table calculated by the
SAA2013. Synchronization, allocation and scale factor
information is then added to provide a fully encoded PASC
data signal. These frames of data are then sent to the drive
processor IC (SAA2023 or SAA3323).

DECODING (SEE FIG.5)
In decoding mode the SAA2003 synchronizes and

recovers frames of data from the drive processor. The
recovered allocation data and the scale factors are used to
correctly re-quantize and re-scale the PASC sub-band
samples. The decoded sub-band samples, which are
represented in 24-bits two’s complement notation, are
reconstructed by the sub-band filters into a single
complete digital audio signal.

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ALLOCATION AND

SCALE FACTOR

INFORMATION

TABLE

SCALING AND

QUANTI ZATION

baseband

samples

from SAA2013

SUB-BAND

FILTER

sub-band

samples

Fig.4 Encoding mode.

May 1994 7

allocation information

and scale factor indices

SYNC AND

CODING

INFORMATION

quantified samples

FORMATTER

PASC

OUTPUT

DATA

MLB764

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

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PASC

data
input

FORMATTER

DE–

sync/coding

allocation

scale factor

quantified

samples

CONTROL

SCALE

FACTOR

ARRAY

AND ALLOCATION

DE-QUANTIZATION

MULTIPLY

OUTPUT

CONTROL

sub-band

samples

MEA804 - 1

SUB-BAND

FILTER

baseband

samples

Fig.5 Decoding mode.

Crystal oscillators

The recommended crystal oscillator configuration is shown in Fig.6. The specified component values only apply to
crystals with a low equivalent series resistance of <40 Ω.

C2 33 pF

C1 33 pF

C3 33 pF

C4 33 pF

22.5792
MHz

X1

24.576

MHz

X2

R1
1 MΩ

R2 220Ω

R4
1 MΩ

R3 1 kΩ

X22IN

X22OUT

X24IN

X24OUT

40

41
42

43

SAA2003

MBD621

Fig.6 Crystal oscillator components.

System reset

Reset must be active from system power-up for >1 ms. Reset must also be active for >1 ms after the falling edge of sleep
as shown in Fig.7.

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Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

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STANDBY

RESET

CLK24/CLK22

I/O's

ACTIVE

MODE 1 MODE 2 MODE 3 MODE 4

t

1

ACTIVE

Fig.7 Reset and sleep timing.

Table 1 Reset and sleep timing modes (see Fig.7).

t

2

t

3

ACTIVESTATIC

ACTIVE

MBD622

MODE DESCRIPTION TIMING MIN. MAX. UNIT

MODE1 standby stage 1; clocks still running t
MODE2 standby mode; clocks stopped t
MODE3 clocks running; reset active t

1
2
3

400 − ns
0 − ns
1 − ms

MODE4 normal operational mode −−−

Sleep mode

A HIGH input applied to the SLEEP pin halts all internally generated clock signals. If the transparent mode of the serial
audio interface is set before entering sleep, the data at the X256 external clock input is sent to the FS256 output and the
data at SD1 input is sent to the SD2 output. If transparent mode is not set, these two outputs are high impedance during
sleep mode.

The IECOP pin is set to high impedance during sleep mode, unless the transparent mode is selected and WS-SEL is set.

May 1994 9

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

Table 2 Transparent mode function in sleep.

PIN

TRANSPARENT

(1)

MODE

WS-SEL

(2)

PIN FUNCTION

FS256 1 X FS256
FS256 0 X high impedance
SD2 1 X SD1
SD2 0 X high impedance
IECOP 0 X high impedance
IECOP 1 0 high impedance
IECOP 1 1 WS

Notes

1. Transparent mode is controlled by bit 3 of the serial audio data interface mode control register.

2. WS-SEL is controlled by bit 3 of the codec extended settings register.

Serial audio interface

The signals between the SAA2003 and the serial audio input/output are shown in Table 3.

Table 3 Interface signals between SAA2003 and serial audio input/output.

PIN INPUT/OUTPUT FUNCTION FREQUENCY

WS bi-directional audio data word select f
SCK bi-directional audio data bit clock 64f
SD1 bi-directional serial audio data to/from DAIO and ADC −
SD2 output audio serial data to DAC −
FDIR output PASC mode encode/decode −
IECOP output alternative serial data word select for SD2 −

s

s

The word select (WS) line indicates the channel being transmitted (either left or right; I or II) and is equal in frequency to
the sampling frequency (f

).

s

Operating at a frequency of 64 × fs, the bit clock (SCK) dictates that each WS period contains 64 SD1 or SD2 data bits.
Of these bits a maximum of 36 are used to transfer data (samples may have a length up to 18 bits). Samples are
transferred most significant bit (MSB) first. Both WS and SD1/SD2 change state at the negative edge of SCK.

The serial audio data is transferred between the SAA2003 and the input/output using either the standard I2S (default) as
shown in Fig.8 or the EIAJ format as shown in Fig.9.

May 1994 10

May 1994 11

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

0123 17 18 32 33 34 3531 49 50 63012

SCL

SWS

SD1/
SD2

0123 12 13 16 17 18 1915 28 29 31012

SCL

SWS

SD1/
SD2

a. Master and slave modes; 18 bits.
b. Slave mode only; 16 bits.

MSB

left channel data right channel data

LSB

MSB

a.

14 30

left channel data right channel data

b.

LSB

LSB

MSB

MSBLSB MSBMSB

MBD623

Fig.8 Serial audio interface SD1/SD2; I2S data format.

May 1994 12

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

SCL

SWS

SD1/
SD2

SCL

SWS

SD1/
SD2

012 14 15 30 31 32 33 46 47 62 63 0 1

left channel data right channel data

MSB MSB LSB MSB

LSB MSBMSB

a.

012 16 17 30 31 32 33 48 49 62 63 0 1

left channel data right channel data

MSB MSB LSB MSB

LSB MSBMSB

b.

2

2

MBD624

a. Master mode; 18 bits.
b. Master mode (EIAJ); 16 bits.

Fig.9 Serial audio interface SD1; EIAJ data format.

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

SERIAL AUDIO INTERFACE DATA FORMATS IN ENCODING MODE
In encoding mode, the serial audio data input for the PASC processor is taken from the SD1 pin. This data is scaled by

the fade processor before being sent to the PASC processor. The output from the fade processor is sent in parallel to
the SD2 output.

Both I2S and EIAJ formats are supported.

Table 4 Serial audio data interface formats in encoding mode.

SD1 INPUT SD2 OUTPUT

FORMAT MASTER/SLAVE RESOLUTION FORMAT RESOLUTION

I2S master 18 bit I2S 18 bit

2

I

S slave 18 bit I2S 18 bit

2

I

S master 16 bit I2S 18 bit

2

S slave 16 bit I2S 16 bit

I
EIAJ
EIAJ
EIAJ
EIAJ

(1)
(1)
(1)
(1)

master 18 bit I2S 18 bit
slave 18 bit I2S 18 bit
master 16 bit I2S 18 bit
slave 16 bit I2S 18 bit

Note

1. If SD1 is used in EIAJ mode, and the data from SD2 is required, the IECOP can be re-programmed to provide a
suitable I

S

ERIAL AUDIO INTERFACE DATA FORMATS IN DECODING MODE

2

S WS signal for SD2. The IEC 958 output is not available in this mode.

In decoding mode, the output from the PASC processor, connected via the fade processor, is present at both SD1 and
SD2.

Both I2S and EIAJ formats are supported.

Table 5 SD1/SD2 output decoding formats.

FORMAT MASTER/SLAVE RESOLUTION

(1)

I2S master 18 bit

2

S slave 18 bit

I

2

I

S master 16 bit

2

I

S slave 16 bit
EIAJ master 18 bit
EIAJ master 16 bit

Note

1. The sub-band filter performs rounding to 16 or 18 bits according to the operating mode of the interface.

ERIAL AUDIO INTERFACE MODE CONTROL

S
The operating mode of the interface is programmed by the extended settings registers as shown in Table 6.

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Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

Table 6 Extended settings register.

A3 A2 A1 A0 D3 D2 D1 D0 MODE

0 0 1 0 X X X 0 16 bit operation; 16 bit rounding
0 0 1 0 X X X 1 18 bit operation; 18 bit rounding

2

0010XX0XI
0 0 1 0 X X 1 X EIAJ data format
0 0 1 0 X 0 X X peak detector input SD1
0 0 1 0 X 1 X X peak detector input SD2
0 0 1 0 0 X X X SD1/FS256 transparent mode disabled
0 0 1 0 1 X X X SD1/FS256 transparent mode enabled

Filtered data interface

The filtered data interface transfers the sub-band filtered data between the stereo filter codec and adaptive allocation and
scaling parts of the DCC chip-set, and consists of the signals as shown in Table 7.

S data format

Table 7 Filtered data interface signals.

PIN INPUT/OUTPUT FUNCTION FREQUENCY

FDCL output filtered data bit clock 64f
FDWS output filtered data word select f

s

s

FDAO output filtered data serial output −
FDAI input filtered data serial input −
FDIR output decode/encode control −
FSYNC output filtered data sync signal; band zero −

ILTERED DATA INTERFACE FORMAT

F
The filtered data is transferred over the interface in accordance with the formats illustrated in Figs 10 and 11.

handbook, full pagewidth

channel

FDWS

FDCL

left 32 bits

right

1

FDAI/
FDAO

bit :

2322212

MSB LSB

02010

0

0

Fig.10 Transfer of filtered data; SAA2003/SAA2013.

May 1994 14

7 bits

2322212

MSB

0

MLB765

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

32 bits

SBWS

SBCL

SBDA

bit :

SBEF

0001020

15 bits1

3

byte 0 byte 1 byte 2

10111

2

13141

LSBMSB

5

1

MSB

16171

202

1

8

9

1

MEA649 - 2

2
2

Fig.11 Transfer of sub-band PASC data.

Sub-band serial PASC interface

The sub-band serial interface carries the PASC serial data stream between the stereo filter codec and the drive processor
part of the DCC chip-set, and consists of the signals as shown in Table 8.

Table 8 Sub-band serial PASC interface signals.

PIN INPUT/OUTPUT FUNCTION FREQUENCY

SBDIR input sub-band data direction control −
SBDA input/output sub-band serial data −
1SBCL input/output sub-band bit clock 768 kHz
SBWS input/output sub-band word select 12 kHz
SBEF input sub-band data error flag −
URDA input unreliable data flag −

The SAA2003 generates SBWS and SBCL in both decode and encoding modes. In decode both signals can be set to
inputs (slave mode) by bit 0 of the extended settings register. The filtered data interface timing is always derived from
the 24.576 MHz clock, regardless of the audio sampling frequency.

Table 9 Extended settings register.

A3 A2 A1 A0 D3 D2 D1 D0 MODE

0 0 0 1 X X X 0 slave mode (default)
0 0 0 1 X X X 1 master mode

Stereo and 2-channel mono encoding modes are available. Stereo, joint stereo and 2-channel mono decoding modes
are available. In decoding and encoding, 48 kHz, 44.1 kHz and 32 kHz sample frequencies can be used.

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Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

SUB-BAND SERIAL PASC INTERFACE DATA FORMAT
The PASC data is transferred over the interface described

above using the format shown in Fig.11. Each period of
SBWS spans 64 periods of the bit clock, SBCL, of which
32 SBCL periods are used to transfer PASC data.

The 32 data bits transferred in one period of SBWS make
up a complete sub-band slot, as defined in the DCC
standard. The first 16 data bits (0, 1, 2, .., 15) are
transferred while SBWS is LOW, and the second 16 data
bits (16, 17, 18, .., 31) are transferred while SBWS is
HIGH.

SBEF and URDA are generated by the drive processor
during decode. The presence of the URDA flag causes the
stereo filter codec to mute the audio output data, and lose
audio frame synchronization.

The direction of SBDA is controlled by the SBDIR input,
which is connected to the drive processor.

SYNCDAI signal

SYNCDAI is a pulse of fixed duration which is generated
by the SAA2003 when any of the following conditions
occur:

• Change of bit rate

• Change of sampling frequency

• Change from encode to decode and vice-versa

• Change of FS256 clock source

2

• Change of I

S bus master

• Reset.

The SYNCDAI signal is used to synchronize the digital
audio input/output interface.

Audio peak level detector

The peak level detector continuously encodes the
maximum amplitude of the audio data samples for each
audio channel until it is reset by the action of reading out
the peak level data. The peak level data can be read by the
SAA2013, and subsequently by the system
microcontroller, or by the microcontroller directly when
SAA2013 is not used.

The peak level data is read via the L3 interface in status
read mode. The first 16 bits of status read transfer the
status bits of SAA2003. The following 32 bits contain the
peak level data. The peak level detector is reset when the
32 bits of peak level data are read.

In encode, the peak level detector can be used to monitor
the data on either SD1 (pre-fade processor) or SD2
(post fade processor). In slave EIAJ input modes the peak
detection is only possible on output SD2. In decode mode,
SD1 must be selected for peak detector input data.

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L3MODE

L3CLK

L3DATA

8150 71617 30 31 32 33 46 47

Fig.12 Peak level data format during status read.

May 1994 16

MBD625

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

Audio fade processor

The fade processor is controlled by the system microcontroller. It achieves level control, or fading, by multiplying the
audio samples with a 17 bit accuracy fade coefficient, which is selected by an 8-bit fade counter. The fade coefficients

range from 0 to 1.0 according to a

Attenuation (dB) 20 log cos–

In encode mode, audio samples are taken from input SD1 and scaled before sub-band filter processing, and sent to
output SD2.

In decode mode, audio samples are scaled following reconstruction by the sub-band filter, and sent to outputs SD1
and SD2.

Table 10 Fade processor operating modes.

MODE FUNCTION

Fade rate controls rate of automatic increments and decrements
Step down increases attenuation by one increment
Step up reduces attenuation by one increment
Full scale sets gain to unity, incrementing from current level automatically
Mute sets gain to zero, decrementing from current level automatically

−12 dB sets gain to −12 dB, decrementing or incrementing from current level automatically

1

⁄4cosine function. The attenuation for a particular fade count (FC) is given as follows:

π FC×



----------------- -



510

dB()=

where: 0 ≤ FC ≤ 255.

F

ADE PROCESSOR MODE CONTROL

The operating mode of the fade processor is controlled by two extended registers

Table 11 Fade processor mode control.

A3 A2 A1 A0 D3 D2 D1 D0 MODE

0011P3P2P1P0set fade rate
01000001step down
01000010step up
010001X0full scale slow
010001X1full scale fast
010010X0mute slow
010010X1mute fast
010011X0−12 dB slow
010011X1−12 dB fast
01000000no action

FADE RATE OPTION
The fade rate can be set to either fast or slow modes. In fast mode the attenuation changes rate at one step per audio

sample. In slow mode the rate of change of level is controlled by the fade rate bits P3 to P0. In slow mode, the fade
counter is stepped up or down according to a clock derived from the WS pin.

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Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

Table 12 Fade rate in slow and fast modes.

MODE P3 P2 P1 P0

TIME PER STEP (ms) TIME FOR 256 STEPS (ms)

32 kHz 44.1 kHz 48 kHz 32 kHz 44.1 kHz 48 kHz

Fast −−−−31.2 µs 22.7 µs 20.8 µs 8.0 5.8 5.3
Slow 00001.0 0.997 1.0 256 255 256
Slow 00012.0 1.994 2.0 512 511 512
Slow 00114.0 3.988 4.0 1024 1021 1024
Slow 01118.0 7.980 8.0 2048 2043 2048
Slow 111116.0 15.96 16.0 4096 4087 4096

IEC 958 output

The IECOP pin provides an output signal in accordance with the IEC 958/SPDIF digital audio interface format.
The function of the IECOP pin is programmed by bit 3 of the codec extended settings register; see Table 13.

Table 13 IECOP pin control.

A3 A2 A1 A0 D3 D2 D1 D0 IECOP FUNCTION

00010XXXIEC958 (default)
00011XXXI

2

S word select for SD2

The IECOP output will only function when the SAA2003 is in decode mode. The IECOP cannot be used when SAA2013
is present in the system, unless the SAA2013 is in sleep mode. The IECOP output is disabled and set to high impedance
by a reset.

L3 bus

The L3 bus is a three-wire clock synchronous data bus common to all ICs in the DCC chip-set. It consists of the L3MODE,
L3CLK and L3DATA connections. The bus has two operating modes:

• Addressing mode; selects the IC for communication and sets type of transfer.

• Data mode; is used to send and receive data and control settings.

The L3MODE and L3CLK lines are driven by the system microcontroller and L3DATA is a bi-directional line. LTCNT0
and LTCNT1 must be left unconnected when L3 mode is used.

For normal use in L3 mode, LTCNT0 and LTCNT1 are held HIGH by internal pull-up resistors. The SAA2003 responds
to serial addresses as shown in Table 14.

Table 14 SAA2003 serial addresses.

D0

(1)

D1

(1)

D2 D3 D4 D5 D6 D7

XX000100

Note

1. D0 and D1 are interpreted as LTCNT0 and LTCNT1 respectively. These two signals control the operation of the
interface as given in Table 15.

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Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

Table 15 Interface modes.

D0/LTCNT0 D1/LTCNT1 MODE

0 0 extended setting from microcontroller to SAA2003
1 0 allocation and scale factor information from SAA2013 to SAA2003
0 1 codec internal settings from microcontroller to SAA2003
1 1 codec status from SAA2003 to microcontroller and SAA2013 including peak

level data

Table 16 Register address settings.

A3 A2 A1 A0 REGISTER

0000codec external settings
0001codec interface mode control
0010serial audio interface mode control
0011fade counter rate control
0100fade counter control

(1)

Note

1. These registers are write only, accessed using the protocol shown in Fig.13.

ndbook, full pagewidth

L3MODE

L3CLK

L3DATA D0 D1 D2 D3 A0 A1 A2 A3

MBD626

Fig.13 Extended settings protocol.

Operation in LT mode

LT interface mode can be selected by writing an extended settings word to the interface mode control register as shown
in Table 17.

Table 17 Interface mode control register.

A3 A2 A1 A0 D3 D2 D1 D0 MODE

0 0 0 1 X X 1 X L3 mode (default)
0 0 0 1 X X 0 X LT mode

In LT mode the LTCNT0 and LTCNT1 pins are used, and the L3MODE pin becomes LTEN enable line. L3CLK becomes
LTCLK, and L3DATA becomes LTDATA.

May 1994 19

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

Table 18 Summary of address registers.

ADDRESS REGISTER

BIT DESCRIPTION

REGISTER EXPLANATION

0 external settings register 0 mute DAC

1 attenuate DAC
2 de-emphasis DAC
3 clock OK hold mode

1 codec extended settings 0 slave receive mode

1 L3/LT mode select
2 comparator delay bypass
3 WS/IEC 958 selection

2 serial audio mode control 0 18 bit operation

2

1I

S/EIAJ format
2 peak detector input select
3 transparent mode

3 fade processor fade rate 0 to 3 rate control, 0 to 15
4 fade processor control 0 to 3 fade command

5 to 15 not used −−

Codec internal settings and status

The settings register is write only, and the status register is read only. The interface protocols for accessing these
registers is shown in Figs 14 and 15.

handbook, full pagewidth

L3MODE

L3CLK

L3DATA 8 9 14 15 0 1 67

Fig.14 Codec internal settings write transfer.

May 1994 20

MBD627

May 1994 21

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

L3MODE

L3CLK

L3DATA 8150 716 3017 33 46 4731 32

MBD628

Fig.15 Codec status read transfer.

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

The codec internal settings register is shown in Table 19.

Table 19 Codec internal settings register formats.

BITS DESCRIPTION ENCODING/DECODING

15 to 12 bit rate index encoding only

11 and 10 sample frequency encoding only

9 decode mode encoding and decoding
8 external FS256 encoding and decoding
7 2 channel mono encoding only
6 mute sub-band filters encoding and decoding
5 external master I

4 select channel I/II decoding only
3 and 2 transparent bits encoding only
1 and 0 emphasis indication encoding only

2

S encoding and decoding

Table 20 Codec status register formats.

BITS DESCRIPTION ENCODING/DECODING

15 to 12 bit rate index encoding and decoding

11 and 10 sample frequency encoding and decoding

9 ready-to-receive encoding and decoding

8 not used −
7 and 6 sub-band mode encoding and decoding

5 synchronization decoding only

4 clock OK encoding and decoding
3 and 2 transparent bits encoding and decoding
1 and 0 emphasis indication encoding and decoding

16 first channel identification −

17 to 31 first channel peak level; LSB first −

32 second channel identification −

33 to 47 second channel peak level; LSB first −

May 1994 22

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

Average current consumption

The average current consumption is shown in Fig.16.

80

handbook, halfpage

I

DD

(mA)

60

40

20

0

2.5 3.5 4.5 5.5

Fig.16 Average current consumption.

Timing diagrams

MBD640

V (V)

DD

handbook, full pagewidth

FS256

SCK

t

cL

WS, SD1
and SD2

Fig.17 Serial audio interface timing in decode; master mode.

May 1994 23

T

FS

t

fH

t

d1

T

c

t

fL

t

d1

t

cH

t

h2

t

d2

MBD629

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

T

handbook, full pagewidth

FS256

FS

t

fH

t

fL

SCK

WS and SD2

SD1

handbook, full pagewidth

t

d1

t

cL

T

c

t

t

h1

su

t

cH

Fig.18 Serial audio interface timing in encode; master mode.

T

t

cL

c

t

cH

t

d1

t

h2

t

d2

MLB602

SCK

WS, SD1

SD1, SD2

T

FS

FS256

t

FH

t

FL

Fig.19 Serial audio interface timing; slave mode.

May 1994 24

t

t

h1

su

t

h2

t

d

MBD630

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

t

handbook, full pagewidth

SYNCDAI

WS, SCK
(slave to master)

WS, SCK
(slave to master)

SH

t

d1

t

d2

SD1

ndbook, full pagewidth

FS256

FDCL

t

d3

t

d4

MBD631

Fig.20 Serial audio master/slave timing.

T

FS

t

FH

t

d1

t

FL

t

d1

t

cL

t

h2

T

c

t

cH

FDWS, FDAO,
FSYNC

t

d2

FDAI

Fig.21 Filtered data interface timing.

May 1994 25

t

t

h1

su

MBD632

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

handbook, full pagewidth

k, full pagewidth

SCK

SBWS,
SBDA

SBWS

sub-band # 0 1 2 29 30 31 0 1 2 3

FDWS

FSYNC

Fig.22 FSYNC output timing.

T

c

t

d3

t

cH

t

d4

(encode)

(decode)

t

cL

t

t

d2

d1

MBD633

SBDA

SBEF

andbook, full pagewidth

SBWS

SBCL

SBDA

L3DATA

t

su2

t

h1

t

su1

0

Fig.23 Sub-band PASC interface timing.

t

h2

MBD634

912345678 101112

MBD635

May 1994 26

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

t

handbook, full pagewidth

L3MODE

ML

handbook, full pagewidth

L3CLK

L3DATA
(INPUT)

L3DATA
(OUTPUT)

L3MODE

t

d1

t

su

t

d2

t

cH

t

h1

t

cL

Fig.24 L3 bus timing; addressing mode.

t

h2

t

d3

MBD637

L3CLK

L3DATA
(INPUT)

L3DATA
(OUTPUT)

L3MODE

t

d1

t

su

t

d3

t

d2

t

cH

t

h1

t

d4

t

h2

Fig.25 L3 bus timing; data transfer mode.

May 1994 27

t

cL

t

ML

t

h3

t

d5

MBD636

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

handbook, full pagewidth

SYNCDAI

FS256
CLOCK
SOURCE

FS256
CLOCK
SOURCE

FDIR

internal

external

t

SH

t

d2

t

d1

t

d5

t

d4

t

d3

Fig.26 Internal/external clock source transition timing.

external

internal

MBD638

t

c24L

CLK24

t

f

t

c22L

CLK22

t

f

Fig.27 CLK22 and CLK24 timing.

May 1994 28

T

T

c24

c22

t

c24H

t

r

t

c22H

t

r

MBD639

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

V

I

I

I

V

O

I

O

I

DDQ

T

stg

T

amb

V

es1

V

es2

Notes

1. The input voltage (V

2. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.

3. Equivalent to discharging a 200 pF capacitor through a 2.5 µH inductor.

supply voltage −0.5 +6.5 V
input voltage note 1 −0.5 VDD + 0.5 V
input current − 20 mA
output voltage −0.5 +6.5 V
output current − 20 mA
quiescent supply current clocks stopped − 100 µA
storage temperature −65 +150 °C
operating ambient temperature −40 +85 °C
electrostatic handling note 2 −2000 +2000 V
electrostatic handling note 3 −200 +200 V

) may not exceed 6.5 V.

I

CHARACTERISTICS

= −40 to 85 °C; VDD = 2.7 to 5.5 V; unless otherwise specified.

T

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DD

I

DD

supply voltage 2.7 5.0 5.5 V
supply current VDD = 3.0 V − 32.5 35.0 mA

V

= 5.0 V − 68.8 75.0 mA

DD

sleep mode;
V

= 5.0 V

DD

−−400 µA

Inputs FDAI, L3CLK, URDA, SBDIR, SBEF, X256, SLEEP and L3MODE

V

IL

V

IH

I

LI

C

I

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V
input leakage current VI = 0 to V

DD

−10 − +10 µA

DD

− V

DD

DD

input capacitance −−10 pF

V
V

Inputs TEST0 and TEST1

V

IL

V

IH

R

I(pd)

C

I

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V
input pull-down resistance VI = V

DD

− 50 − kΩ

DD

− V

DD

DD

V
V

input capacitance −−10 pF

May 1994 29

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Inputs LTCNT0 and LTCNT1

V

IL

V

IH

R

I(pu)

C

I

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V

DD

− V
input pull-up resistance VI = 0 V − 50 − kΩ
input capacitance −−10 pF

Input RESET

V

tLH

threshold voltage

−−0.8V

LOW-to-HIGH

V

tHL

threshold voltage

0.2V

DD

−−V
HIGH-to-LOW

V

hys

C

I

hysteresis voltage − 0.33V
input capacitance −−10 pF

Outputs FDCL, FDWS, FDIR, FSYNC, FDAO, MUTEDAC, ATTDAC and DEEMDAC

V

OL

V

OH

C

L

t

r

LOW level output voltage IOL = 4 mA 0 − 0.4 V
HIGH level output voltage IOH = −4mA VDD− 0.4 − V
load capacitance −−30 pF
output rise time 0.4 V to VDD− 0.4 V;

−−20 ns

CL = 30 pF

t

f

output fall time VDD− 0.4 V to 0.4 V;

−−20 ns

CL = 30 pF

DD

DD

DD

DD

− V

DD

V
V

V

V

Output CLK22

V

OL

V

OH

C

L

t

r

t

f

LOW level output voltage IOL = 4 mA 0 − 0.4 V
HIGH level output voltage IOH = −4mA VDD− 0.4 − V
load capacitance −−30 pF
output rise time 0.4 V to VDD− 0.4 V;

output fall time VDD− 0.4 V to 0.4 V;

Output CLK24

V

OL

V

OH

C

L

t

r

t

f

LOW level output voltage IOL = 6 mA 0 − 0.4 V
HIGH level output voltage IOH = −6mA VDD− 0.4 − V
load capacitance −−50 pF
output rise time 0.4 V to VDD− 0.4 V;

output fall time VDD− 0.4 V to 0.4 V;

CL = 30 pF

CL = 30 pF

CL = 50 pF

CL = 50 pF

DD

V

−−7ns

−−7ns

DD

V

−−7ns

−−7ns

May 1994 30

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Output SYNCDAI

V

OL

V

OH

C

L

t

r

t

f

Output FS256

V

OL

V

OH

C

L

t

r

t

f

I

LI

Output SD2

V

OL

V

OH

C

L

t

r

t

f

I

LI

Output IECOP

V

OL

V

OH

C

L

t

r

t

f

I

LI

LOW level output voltage IOL = 4 mA 0 − 0.4 V
HIGH level output voltage IOH = −4mA VDD− 0.4 − V

DD

V
load capacitance −−40 pF
output rise time 0.4 V to VDD− 0.4 V;

−−20 ns

CL = 40 pF

output fall time VDD− 0.4 V to 0.4 V;

−−20 ns

CL = 40 pF

LOW level output voltage IOL = 6 mA 0 − 0.4 V
HIGH level output voltage IOH = −6mA VDD− 0.4 − V

DD

V
load capacitance −−60 pF
output rise time 0.4 V to VDD− 0.4 V;

−−7ns

CL = 60 pF

output fall time VDD− 0.4 V to 0.4 V

−−7ns

;

CL = 60 pF

3-state leakage current VI = 0 to V

DD

−10 − +10 µA

LOW level output voltage IOL = 4 mA 0 − 0.4 V
HIGH level output voltage IOH = −4mA VDD− 0.4 − V

DD

V
load capacitance −−30 pF
output rise time 0.4 V to VDD− 0.4 V;

−−20 ns

CL = 30 pF

output fall time VDD− 0.4 V to 0.4 V;

−−20 ns

CL = 30 pF

3-state leakage current VI = 0 to V

DD

−10 − +10 µA

LOW level output voltage IOL = 4 mA 0 − 0.4 V
HIGH level output voltage IOH = −4mA VDD− 0.4 − V

DD

V
load capacitance −−50 pF
output rise time 0.4 V to VDD− 0.4 V;

−−20 ns

CL = 50 pF

output fall time VDD− 0.4 V to 0.4 V;

−−20 ns

CL = 50 pF

3-state leakage current VI = 0 to V

DD

−10 − +10 µA

May 1994 31

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Inputs/outputs SBDA, SBCL and SBWS

V

IL

V

IH

R

I(pd)

C

I

V

OL

V

OH

C

L

t

r

t

f

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V
input pull-down resistance VI = V
input capacitance −−10 pF
LOW level output voltage IOL = 4 mA 0 − 0.4 V
HIGH level output voltage IOH = −4mA VDD− 0.4 − V
load capacitance −−30 pF
output rise time 0.4 V to VDD− 0.4 V;

output fall time VDD− 0.4 V to 0.4 V;

Inputs/outputs SD1, SCK and WS

V

IL

V

IH

R

I(pd)

C

I

V

OL

V

OH

C

L

t

r

t

f

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V
input pull-down resistance VI = V
input capacitance −−10 pF
LOW level output voltage IOL = 4 mA 0 − 0.4 V
HIGH level output voltage IOH = −4mA VDD− 0.4 − V
load capacitance −−50 pF
output rise time 0.4 V to VDD− 0.4 V;

output fall time VDD− 0.4 V to 0.4 V;

DD

CL = 30 pF

CL = 30 pF

DD

CL = 50 pF

CL = 50 pF

DD

DD

− V

DD

− 50 − kΩ

DD

−−20 ns

−−20 ns

DD

DD

− V

DD

− 50 − kΩ

DD

−−20 ns

−−20 ns

V

V

V

V

V

V

Input/output L3DATA

V

IL

V

IH

C

I

V

OL

V

OH

C

L

t

r

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V
input capacitance −−10 pF
LOW level output voltage IOL = 4 mA 0 − 0.4 V
HIGH level output voltage IOH = −4mA VDD− 0.4 − V
load capacitance −−60 pF
output rise time 0.4 V to VDD− 0.4 V;

CL = 60 pF

t

f

output fall time VDD− 0.4 V to 0.4 V;

CL = 60 pF

Input X22IN (external clock)

V

IL

V

IH

I

LI

C

I

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V
input leakage current −10 − +10 µA
input capacitance −−10 pF

May 1994 32

V

V

V

DD

− V

DD

DD

DD

−−20 ns

−−20 ns

V

V

DD

− V

DD

DD

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Output X22OUT

f

xtal

g

m

G

v

C

fb

C

O

Input X24IN (external clock)

V

IL

V

IH

I

LI

C

I

Output X24OUT

f

xtal

g

m

G

v

C

fb

C

O

Input X256

f

i

t

cH

t

cL

CLK22 and CLK24 timing; Fig.27

crystal frequency note 1 − 22.5792 − MHz
transconductance 1.5 −−mS
small signal voltage gain Gv = gm× R

O

3.5 −−
feedback capacitance −−5pF
output capacitance −−10 pF

LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V

DD

− V

DD

DD

V

V
input leakage current −10 − +10 µA
input capacitance −−10 pF

crystal frequency note 1 − 24.567 − MHz
transconductance 1.5 −−mS
small signal voltage gain Gv = gm× R

O

3.5 −−
feedback capacitance −−5pF
output capacitance −−10 pF

input frequency fs = 48 kHz − 12.288 − MHz

f

= 44.1 kHz − 11.2896 − MHz

s

f

= 32 kHz − 8.192 − MHz

s

HIGH time 35 −−ns
LOW time 35 −−ns

O

UTPUT CLK24

f

o

t

c24H

t

c24L

t

r

t

f

output frequency CL = 50 pF − 24.576 − MHz
HIGH time CL = 50 pF 12 −−ns
LOW time CL = 50 pF 12 −−ns
rise time CL = 50 pF −−7ns
fall time CL = 50 pF −−7ns

OUTPUT CLK22
f

o

t

c22H

t

c22L

t

r

t

f

output frequency CL = 30 pF − 22.5792 − MHz
HIGH time CL = 30 pF 11 −−ns
LOW time CL = 30 pF 11 −−ns
rise time CL = 30 pF −−7ns
fall time CL = 30 pF −−7ns

May 1994 33

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Drive processing interface timing; see Fig.23

t
t
t
t

t

t

t

t

t

cy
cH
cL
d1

d2

su1

h1

su2

h2

SCK cycle time − 1302 − ns
SCK HIGH time 460 651 − ns
SCK LOW time 460 651 − ns
SBWS and SBDA delay time

20 −−ns

until SCK LOW
SCK delay time until SBWS

−−20 ns
and SBDA valid

SBDA input set-up time before

235 −−ns

SCK HIGH
SBDA input hold time after

30 −−ns

SCK HIGH
set-up time from SCK HIGH

−−90 ns
until SBEF valid

SBEF input hold time after

380 −−ns

SCK HIGH

Filtered data interface timing; see Fig.21

FDCL, FDWS, FDAI
f

T
t

t

t

256

c

FH

FL

d1

FS256 frequency fs = 48 kHz − 12.288 − MHz

FDCL cycle time fs = 48 kHz − 325.6 − ns
FS256 HIGH time fs = 48 kHz; note 2 35 −−ns

FS256 LOW time fs = 48 kHz; note 2 35 −−ns

FS256 delay time until FDCL

AND FDAO

transition

t

cH

t

cL

t

h2

FDCL HIGH time fs = 48 kHz 143 −−ns
FDCL LOW time fs = 48 kHz 143 −−ns
FDWS, FDAO and FSYNC

hold time after FS256 HIGH

t

d2

FS256 HIGH delay time until
FDWS, FDAO and FSYNC
valid

t

su

FDAI input set-up time before
FS256 HIGH

t

h1

FDAI input hold time after
FS256 HIGH

f

= 44.1 kHz − 11.2896 − MHz

s

= 32 kHz − 8.192 − MHz

f

s

= 44.1 kHz; note 2 38 −−ns

f

s

f

= 32 kHz; note 2 75 −−ns

s

f

= 44.1 kHz; note 2 38 −−ns

s

f

= 32 kHz; note 2 35 −−ns

s

0 − 50 ns

0 −−ns

0 − 50 ns

20 −−ns

30 −−ns

May 1994 34

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing characteristics FDIR and SYNCDAI; see Fig.26

t

sH

t

d1

t

d2

t

d3

t

d4

t

d5

Baseband data interface timing characteristics

M

ASTER MODE; SEE FIGS 17 AND 18

T

c

t

cH

t

cL

t

d1

t

h2

t

d2

t

su

t

h1

SLAVE MODE; SEE FIG.19
T

c

t

cH

t

cL

t

su

t

h1

t

h2

t

d

SYNCDAI HIGH time 1280 −−ns
internal clock delay time after

0 −−ns

SYNCDAI LOW
external clock delay time after

−−320 ns
SYNCDAI LOW

FDIR delay time before

280 −−ns

SYNCDAI HIGH
external clock delay time

−−320 ns
before SYNCDAI HIGH

internal clock delay time

0 −−ns

before SYNCDAI HIGH

SCK cycle time fs = 48 kHz − 325.6 − ns
SCK HIGH time fs = 48 kHz 143 −−ns
SCK LOW time fs = 48 kHz 143 −−ns
FS256 HIGH delay time until

0 − 50 ns

SCK transition
WS, SD1 and SD2 hold time

0 −−ns

after FS256 HIGH
FS256 delay time until WS,

0 − 50 ns

SD1 and SD2 valid
SD1 input set-up time before

30 −−ns

SCK HIGH
SD1 input hold time after SCK

0 −−ns

HIGH

SCK cycle time fs = 48 kHz 325.6 − 651.2 ns
SCK HIGH time fs = 48 kHz 116 −−ns
SCK LOW time fs = 48 kHz 116 −−ns
WS and SD1 inputs set-up

30 −−ns

time before SCK HIGH
WS and SD1 inputs hold time

0 −−ns

after SCK HIGH
SD1 and SD2 outputs hold

66 −−ns

time after SCK HIGH
SCK delay time until SD1 and

−−223 ns
SD2 outputs valid

May 1994 35

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing characteristics master/slave mode transition; see Fig.20

t

sH

t

d1

t

d2

t

d3

t

d4

Timing L3 interface; see Fig.24

A

DDRESSING MODE

t

cH

t

cL

t

d1

t

su

t

h1

t

h2

t

d2

t

d3

SYNCDAI HIGH time 1280 −−ns
WS and SCK outputs enabled

140 −−ns

after SYNCDAI LOW
WS and SCK outputs disabled

140 −−ns

before SYNCDAI LOW
SD1 output disabled before

250 −−ns

SYNCDAI HIGH
SD1 output enabled after

790 −−ns

SYNCDAI LOW

L3CLK HIGH time 210 −−ns
L3CLK LOW time 210 −−ns
L3MODE LOW delay time until

190 −−ns

L3CLK HIGH
L3DATA input set-up time

190 −−ns

before L3CLK HIGH
L3DATA input hold time after

30 −−ns

L3CLK HIGH
L3CLK HIGH hold time before

190 −−ns

L3MODE HIGH
L3MODE LOW delay time until

0 − 50 ns

L3DATA disabled
L3MODE HIGH delay time

0 − 50 ns

until L3DATA enabled

May 1994 36

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

D

ATA MODE; SEE FIG.25

t

cH

t

cL

t

d1

t

d2

t

d3

t

su

t

h1

t

h2

t

d4

t

h3

t

d5

t

ML

Notes

1. The crystal frequencies 22.5792 MHz ±200 × 10−6MHz and 24.5760 MHz ±200 × 10−6MHz must track each other
in frequency with an accuracy of 200× 10−6MHz. For example if the 24.5760 MHz clock is 150× 10−6MHz fast, then
the range of the 22.5792 MHz clock becomes −50 × 10−6MHz and +350 × 10−6MHz

2. Timing values only valid for internally generated FS256.

L3CLK HIGH time 210 −−ns
L3CLK LOW time 210 −−ns
L3MODE delay time until

190 −−ns

L3CLK HIGH
L3MODE delay time until

0 − 50 ns

L3DATA enabled
L3MODE delay time until

−−380 ns

L3DATA valid
L3DATA set-up time before

190 −−ns

L3CLK HIGH
L3DATA input hold time after

30 −−ns

L3CLK HIGH
L3DATA output hold time after

120 −−ns

L3CLK HIGH
L3CLK delay time until

L3DATA output valid

not between data bits
7 and 8

between data bits 7

−−360 ns

−−530 ns

and 8

L3CLK HIGH hold time before

190 −−ns

L3MODE LOW
L3MODE LOW delay time until

0 − 50 ns

L3DATA output disabled
L3MODE LOW time between data words 190 −−ns

May 1994 37

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

PACKAGE OUTLINE

handbook, full pagewidth

seating

plane

0.1 S

12.9

12.3

44

1

pin 1 index

11

12

34

22

S

1.2
(4x)

0.8

33

0.8

0.40

23

0.20

B

10.1

9.9

12.9

12.3

B

0.15 M

Dimensions in mm.

0.8

0.40

0.20

0.15 M A

10.1

9.9

1.85

1.65

MBB944 - 2

Fig.28 Plastic quad flat-pack, 44-pin (short) (QFP44SL).

May 1994 38

0.25

0.05

1.2

0.8

(4x)

A

detail X

0.95

0.55

0.85

0.75

X

0.25

0.14

0 to 10

2.10

1.70

o

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

SOLDERING
Plastic quad flat-packs

YWAVE

B
During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

B

Y SOLDER PASTE REFLOW

Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be

applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

R

IRON OR PULSE

-HEATED SOLDER TOOL)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

May 1994 39

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.

May 1994 40

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

NOTES

May 1994 41

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

NOTES

May 1994 42

Philips Semiconductors Preliminary specification

Stereo filter and codec SAA2003

NOTES

May 1994 43

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

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Canada: INTEGRATED CIRCUITS:

Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 601 Milner Ave,
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Tel. [phone] 911, Fax. [phone]

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6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T.,
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Mexico: Philips Components, 5900 Gateway East, Suite 200,

EL PASO, TX 79905, Tel. [phone], Fax. [phone]

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

th

floor, Suite 51,

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: Philips Electrical Industries of Pakistan Ltd.,

Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. [phone],
Fax. [phone].

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106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

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Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. [phone], Fax. [phone].

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

South Africa: S.A. PHILIPS Pty Ltd., Components Division,

195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone].

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Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West

Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone].

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. [phone], Fax. [phone].

Turkey:Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Limited, P.O. Box 65,

Philips House, Torrington Place, LONDON, WC1E 7HD,
Tel. [phone], Fax. [phone]

United States:INTEGRATED CIRCUITS:

811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,

P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. [phone] and [phone], Fax. [phone]

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. [phone], Fax. [phone]

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD31 © Philips Electronics N.V. 1994

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

513061/1500/01/pp44 Date of release: May 1994
Document order number: 9397 731 40011

Philips Semiconductors