Datasheet SA1630BE Datasheet (Philips)

INTEGRATED CIRCUITS

SA1630

IF quadrature transceiver

Product specification 1998 Jul 21
IC17 Data Handbook

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

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

DESCRIPTION

The SA1630 is a 70–400 MHz I/Q transceiver for wireless LAN.
The Receive Path contains a digitally gain controlled linear IF
amplifier, a pair of quadrature down conversion mixers and a pair of
baseband amplifiers. The transmit path contains a pair of quadrature
up conversion mixers that transposes a quadrature baseband input
signal up to IF frequency. An external VCO signal is divided
internally and provides quadrature local oscillator signals for the
mixers. Another divider chain, reference divider and phase detector
are provided to avoid the need for an external synthesizer. To keep
power consumption to a minimum the transmit, receive and local
oscillator functions can be powered down under digital control.

FEA TURES

•Low supply voltage operation of 2.7V for main chip and 2.9V for

charge pump.

•Low current consumption: 33.5 mA in RX, 26.5 mA in TX, typical

at 3V .

•Flexible power up/down options.

•Optional 2.5V regulated reference voltage available during

transmit.

•Input IF frequency range of 70–400 MHz.

BE Package

IF IN

IF INX

V

CC

GNDRX

V

CC

PLL_ON

Rx_ON

GNDHDR

GC0
GC1
GC2
GC3
GC4
GC5

GNDRx

Rx

1
2
3

Rx

4
5
6
7
8

9
10
11
12

13 14 15 16 17 18 19

GNDRxRxRx

GNDRXTxTx

45464748

•Internal IF PLL for synthesizing the local IF oscillator signal.

•Bandwidth of baseband Tx inputs is 20 MHz and that of baseband

Rx outputs is 8.5MHz.

•Designed for IEEE 802.11 wireless LAN using Direct Sequence

Spread Spectrum modulation.

•Control registers power up in a default state.

•Only a standard reference input frequency required, choice of 8,

11, 22 or 44 MHz.

•Digital gain control of 70 dB in steps of 2 dB.

•Rx Baseband amplifiers are capable of driving 1k ||15pF

•Rx Baseband o/p’s clamp symmetrically , above 1Vp–p in order to

prevent dc bias shift under overdrive conditions.

•Package: LQFP–48, PCMCIA compatible

APPLICATIONS

•IF circuitry for IEEE 802.11 DSSS wireless LAN.

•Applications for high speed wireless data.

IFOUT

IFOUTX

424344

20 21 22 23 24

GNDTxRx

GNDTxRx

CC

V TxRx

394041 3738

REF

REF

V 2.5

I

36
35
34
33
32
31
30
29
28
27
26
25

GNDCP
CP
V CP

CC

DATA
CLOCK
STROBE
LOCK
LO_INX
LO_IN
GNDRx
CLK IN
CLK

INX

GND_BB

GND_BB

CC

V _BB

Q_RxOUT

I_Tx_IN

I_RXOUT

Q_Tx IN

I_Tx_INX

CC

Q_Tx INX

V _DIG

Tx_ON

GNDDIG

SR01549

Figure 1. Pin Configuration

ORDERING INFORMATION

DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #

48–Pin Plastic Low Profile Quad Flat package –40 to +85°C SA1630BE SOT313–2

1998 Jul 21 853–2049 19763

2

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

(46)

(45)

(10)
(11)
(12)

(4)

PLL–ON

R

Tx

Tx

IFOUT

Tx

IFOUTX

LO IN

LO INX

XON

MODE

ON

CONTROL

÷

2

(5)

(23)

(43)

(42)

(7)

GC0

(8)

GC1

(9)

GC2

Rx

IFIN

Rx

IFINX

GC3
GC4
GC5

(28)
(29)

(38)

2.5V REGULATOR

BUFFERS

V

2.5

REF

(1,3)

VCCR

(39)

VCCTXR

X

X

GND_BB

VCC_BB

I_Tx

IN

I_Tx

INX

Q_Tx

IN

Q_Tx

INX

I_Rx

Q_Rx

OUT

OUT

1

1

(13, 14)

(15)

(18)
(19)

(20)
(21)

(17)

(16)

(34)

(35)

(37)

(30)

(36)

V

CCCP

CP

I

REF

LOCK

GNDCP

CHARGE

8, 11, 22, 44

÷

CLK

IN

DAC

PUMP

N

÷

PHASE

DETECTOR

TEST REGISTER

INX

V

CCDIG

GND DIGCLK

Figure 2. Block Diagram

SYNTH

REGISTER

SERIAL

INPUT

DATA CLOCK STROBE

(2, 27, 44, 47, 48)(31)(32)(33)(24)(22)(25)(26)

GND RX

GND HDR

GNDTXR

(6)

X

(40, 41)

SR01551

1998 Jul 21

3

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

PIN DESCRIPTIONS

Pin No. Pin Name Description

1, 3 VCCRx Supply Pin for Rx section (IF circuits)

2, 27,

44,47,

13, 14 GND_BB Ground pin for Rx baseband circuits

40,41 GNDTxRx Ground pins used by Tx circuits

GNDRx Ground pins for Rx section (IF circuits)

48

4 PLL_ON One of the three digital CMOS logic control inputs to the mode control section
5 Rx_ON One of the three digital CMOS logic control inputs to the mode control section
6 GNDHDR Substrate ground
7 GCO Control bit 0 for IF VGA gain control, CMOS input
8 GC1 Control bit 1 for IF VGA gain control, CMOS input

9 GC2 Control bit 2 for IF VGA gain control, CMOS input
10 GC3 Control bit 3 for IF VGA gain control, CMOS input
11 GC4 Control bit 4 for IF VGA gain control, CMOS input
12 GC5 Control bit 5 for IF VGA gain control, CMOS input

15 VCC_BB Supply Pin for Rx Baseband circuits
16 Q_RXOUT Quadrature–phase Rx baseband output, single–ended
17 I_RxOUT In–phase Rx baseband output, single–ended
18 I_Tx IN In–phase differential Tx baseband input, positive
19 I_Tx INX In–phase dif ferential Tx baseband input, negative
20 Q_Tx IN Quadrature differential Tx baseband input, positive
21 Q_Tx INX Quadrature differential Tx baseband input, negative
22 VCC_DIG Supply for digital circuits
23 Tx_ON One of the Three digital CMOS logic control inputs to the mode control section
24 GNDDIG Digital ground
25 CLK INX Dif ferential reference input for synthesizer, negative
26 CLK IN Differential reference input for synthesizer, positive
28 LO_IN Differential LO input,positive
29 LO INX Differential LO input, negative
30 LOCK Test control output and synthesizer lock indicator
31 STROBE Serial bus strobe input
32 CLOCK Serial bus clock input
33 DATA Serial bus data input
34 VCCCP Supply for charge pump circuits
35 CP Charge pump output
36 GNDCP Ground for charge pump circuits
37 I

REF

38 V
39 VCCTxRx Supply pin used by Tx circuits

42 TxIFOUTX Differential transmitter IF output (open collector), positive
43 TxIFOUT Differential transmitter IF output (open collector), negative
45 RxIF INX Differential receiver IF input, negative
46 RxIF IN Differential receiver IF input, positive

2.5 Reference voltage of 2.5V available for external use

REF

Charge pump reference current

1998 Jul 21

4

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNITS

V

CCXX

V

IN

∆VG Any GND pin to any other GND pin 0 V

P

D

T

JMAX

P

MAX

T

STG

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER RATING UNITS

V

CCXXXX

VCCCP Charge pump supply voltage 2.7 to 3.6 V

T

A

NOTES:

1. There are no ESD protection diodes between pins 42, 43 and V
reduced. Proper ESD handling precautions should be followed.

MODE CONTROL

NO: PLL_ON RX_ON TX_ON STATE DESCRIPTION MODE 2.5V REF

1 0 X X SLEEP mode SLEEP Off
2 1 0 1 Synthesizer ON, Rx STDBY, Tx OFF WAIT Off
3 1 1 1 Synthesizer ON, Rx STDBY, Tx ON TRANSMIT On
4 1 1 0 Synthesizer ON, Rx ON, Tx OFF RECEIVE Off
5 1 0 0 Synthesizer ON, Rx OFF, Tx ON TRANSMIT Off

’0’ – LOGIC LOW
’1’ – LOGIC HIGH
’X’ – DON’T CARE

Supply voltages -0.3 to +6.0 V
Voltage applied to any other pin -0.3 to V

Power dissipation, TA = 25°C (still air) 300 mW
Maximum operating junction temperature 150 °C
Maximum power input/output +20 dBm
Storage temperature range –65 to +150 °C

Supply voltages: 2.7 to 3.6 V

Operating ambient temperature range -40 to +85 °C

to allow higher AC peak voltage. The ESD protection level has thus been

CC

+0.3 V

CCXX

1. Sleep mode (PLL OFF, Rx OFF, Tx OFF)

In this mode everything is switched off except the 3–wire digital bus.
As long as the digital supply is still on, the programmed values are
active and the 3–wire bus will continue to be programmable.

2. Wait Mode (Tx Off, Rx Standby)

PLL is on. Receiver is in the reduced current standby mode and the
transmitter is completely switched off. This mode maybe useful if the
PLL is to be kept on and is waiting for a quick turn–on to either
transmit or receive modes, especially when Rx outputs are AC
coupled.

3. Transmit mode (Rx standby)

The PLL and transmitter are on. The receive section is in a reduced
current mode wherein most of the Rx circuitry is powered down

except for the bias and baseband circuits needed to hold the
baseband output voltages in the active state. This mode is useful if
the Rx baseband outputs are AC coupled via a large capacitor and
the application demands quick turn–on for the Rx, from Tx.

4. Receive Mode (Tx Off)

The Transmitter is completely shut–off. The PLL and receiver
sections are operating.

5. Transmit Mode (Rx OFF)

PLL and Transmit sections are on. However, the Receiver is
completely shut–down. This mode is useful if the Rx baseband
outputs are DC coupled to the external world.

1998 Jul 21

5

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

RX VGA CONTROL TABLE

GC5 GC4 GC3 GC2 GC1 GC0 DECIMAL NUMBER

0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 –2
0 0 0 0 1 0 2 –4
0 0 0 0 1 1 3 –6
0 0 0 1 0 0 4 –8
0 0 0 1 0 1 5 –10
0 0 0 1 1 0 6 –12
0 0 0 1 1 1 7 –14
0 0 1 0 0 0 8 –16
0 0 1 0 0 1 9 –18
0 0 1 0 1 0 10 –20
0 0 1 0 1 1 11 –22
0 0 1 1 0 0 12 –24
0 0 1 1 0 1 13 –26
0 0 1 1 1 0 14 –28
0 0 1 1 1 1 15 –30
0 1 0 1 1 1 23 –32
0 1 1 0 0 0 24 –34
0 1 1 0 0 1 25 –36
0 1 1 0 1 0 26 –38
0 1 1 0 1 1 27 –40
0 1 1 1 0 0 28 –42
0 1 1 1 0 1 29 –44
0 1 1 1 1 0 30 –46
0 1 1 1 1 1 31 –48
1 1 0 1 0 0 52 –50
1 1 0 1 0 1 53 –52
1 1 0 1 1 0 54 –54
1 1 0 1 1 1 55 –56
1 1 1 0 0 0 56 –58
1 1 1 0 0 1 57 –60
1 1 1 0 1 0 58 –62
1 1 1 0 1 1 59 –64
1 1 1 1 0 0 60 –66
1 1 1 1 0 1 61 –68
1 1 1 1 1 0 62 –70

REDUCTION
FROM Gmax

1998 Jul 21

6

Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITION

UNITS

SA1630IF quadrature transceiver

DC ELECTRICAL CHARACTERISTICS

VCCXXX=+3V; VEEXXX = 0V; TA=25°C, unless otherwise stated.

LIMITS

MIN TYP MAX

I

CC–4

I

CC–2

I

CC–3

I

CC–1

I

CC–5

V

REF

Z

OUT_VREF

Supply Current, Receive (mode #4)

Supply Current, Wait (mode #2)

Supply Current, Transmit (mode #3)

Supply Current, Sleep mode (mode #1)

Supply current transmit (mode 5)

_2.5 Reference voltage (mode 3, enabled) Load = 1.5mA 2.5 V

Output impedance of reference voltage ∆I = 1.4 to 1.6mA 15

CMOS LOGIC INPUTS (DATA, CLOCK, STROBE)

V

IH

V

I

C

Input logic 1 level 2.0 V
Input logic 0 level 0 0.8 V

IL

Input logic current 1 µA

I

Input logic capacitance 4 pF

I

CMOS Logic output (LOCK)

V

OH

V

OL

Output logic 1 level IO = –2mA V
Output logic 0 level IO = 2mA 0.4 V

CMOS Logic Inputs (PLL_ON, RX_ON, TX_ON)

V

IH

V

I

Input logic 1 level
Input logic 0 level 0 0.8 V

IL

Input logic current 1 µA

I

PLL_ON=Rx_ON=Hi

Tx_ON = Low

Wait mode (2)

PLL_ON = Hi

Tx_ON = Hi

Rx_ON = Low

PLL_ON = TX_ON = Hi

RX_ON = Hi

PLL_ON = Low

RX_ON = DC
TX_ON = DC

PLL_ON = Hi

TX_ON = RX_ON = Low

33.5 41.5 mA

17 23 mA

26.5 34.5 mA

0.012 0.1 mA

22 28.5 mA

CCD

–0.4 V

CCD

2.0

V

CCTXRX



V

V

1998 Jul 21

7

Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITION

UNITS

SA1630IF quadrature transceiver

AC ELECTRICAL CHARACTERISTICS IF TRANSMIT MODULA TOR

(Mode #3, Tx ON Rx Standby) VCCXXX = +3V; GNDXXX = 0V; LO_in = 100 mV peak at 704 MHz, CLKin = 100mV peak at 22 MHz, T
25°C, unless otherwise stated.

LIMITS

MIN TYP MAX

4,5

BW

V

THD_3 Third harmonic distortion

R

INTx

C

INTx

IO DC Mean output DC current At TXIF

CS Carrier suppression

SBS SB Suppression

Input modulation bandwidth 500 ohms source impedance 22 MHz

1,2

1

Voltage common mode = 1 to 2V 1 Vpp

Input signal amplitude = 1 VPP,

8 MHz, VCM = 1.5

Between pins I_TXIN, I_TXINX

Q_TXIN, Q_TXINX

–55 –45 dBc

98 kΩ

Between pins I_TXIN, I_TXINX

Q_TXIN, Q_TXINX

VIN = IV

VCMI = VCMQ = VCC/2

OUT

Mismatch at TXIF

At TXIF

OUT

400 Ω tuned load

Differential output

f

= 352 MHz 35 47 dBc

OUT

PP

and TXIF

and TXIF

OUT

and TXIF

OUTX

OUTX

OUTX

2

30

VCC–0.3 V

2 2.75 mA

0.475 mA rms
190 mV rms

36 dBc

Input signal amplitude, Differential

IN

Input resistance

4

Input Capacitance

Minimum Tx output DC voltage

Output current DC offset
Output current available
Output differential voltage

5

4

2

1,3

1,3

2 pF

40 µA

Noise floor offset = 10 MHz 156 dBc/Hz

6

TX_ON, RX_ON transition

to transmit signal at 90% level

TX_ON, RX_ON transition to transmit

signal at 10% level

0.5 2.0 dB
4 µs

4 µs

T

G
t

ON

OFF

4

4

4

Gain stability
Turn–on time

Turn–off time

NOTES:

1. Tx inputs are differential sine wave, 0.5 V peak, with quadrature relationship between I and Q Tx input. The output spectrum will be SSB.
The tone is at a frequency of 1 MHz.

2. The output current in each arm is the same but 180 degrees out of phase with each other. Also the tuned load of 400 ohms differential, is
assumed. The power delivered to 400 ohms will be –10.4 dBm (typ.). The output current measurement is indirect based on output power
measurement according to P = 10 log I

2

rms (400)/IMV. See typical performance characteristic curve.

3. This is measured with respect to the SSB output.

4. Guaranteed by design and or characterization but not final tested.

5. The input bandwidth may be verified by measuring the output THD and signal level using a DSB spectrum where I = Q.

6. Measured over temperature and supply.

amb

=

1998 Jul 21

8

Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITION

UNITS

OVS

Output voltage swing

SA1630IF quadrature transceiver

AC ELECTRICAL CHARACTERISTICS IF RECEIVER DEMODULA T OR

(Mode #4, Rx_ON, Tx_OFF) VCCXXX = +3V = GNDXXX = 0V; LO IN = 100 mV
unless otherwise stated.

f

RInRx Differential input impedance

= 352 MHz

IN

VG Voltage gain AGC at maximum gain 81 88 dB
NF Input noise figure

1

VGA at maximum gain 7.5 dB
AGC range 67 70 dB
AGC step size 2 dB
AGC differential error 2 dB
AGC settling time any AGC step 200 nS
Channel matching

gain
phase

Output DC offset between IRx Out and
QRx Out

p

Maximum Gain, Output at 1 MHz 6 mV

AGC G

AGC Gain, except G
Output common mode voltage 1.9 V
Output impedance 7 Ω

3

THD

BW

t

ON

t

OFF

Total Harmonic Distortion Max. Gain, rated output at 1 MHz 3 %

5

Rx Bandwidth 7 8.5 10 MHz

4

4

Turn–on time

Turn–off time

RX_ON, TX_ON transition to

baseband signal out

RX_ON, TX_ON transition to no

baseband signal out

NOTES:

1. The Receive input is to be differential (using a balun or a differential source such as a differential SAW filter) and matched to external
generator’s impedance (ex: 50 ohms). The balun may or may not provide any impedance transformation depending on availability. An
external L–C matching circuit can provide the rest of the impedance transformation and absorb the input capacitance of the receiver input.
Such a differential input scheme is mandatory to avoid pickup, and keep the noise figure low. A shunt resistor across the input (value TBD)
will be used to set the input impedance as a compromise between the matching ease in production versus the noise figure of the receiver.
The system board layout has to keep the isolation between the receive inputs and the LO signal as high as possible. Otherwise the LO
leakage will overload the receiver.

2. The load is 1000 ohms in parallel with 15pF of capacitor.

3. THD is total harmonic distortion. We measure harmonics 2, 3, 4.

4. Guaranteed by design.

5. 3dB bandwidth relative to a passband measurement taken at 1MHz.

at 704 MHz, CLKIN = 100mV

peak

, into load

MIN

2

MIN

, at 22 MHz, Ta = 25°C,

peak

LIMITS

MIN TYP MAX

6.6K||0.7 kΩ||pF

0.1

0.25

dB

deg

0.9 1.15 Vp–p

1.0 1.4

2 µs

2 µs

1998 Jul 21

9

Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITION

UNITS

t

SA1630IF quadrature transceiver

AC ELECTRICAL CHARACTERISTICS IF SYNTHESIZER

VCCXXX = RX_ON = TX_ON = PLL_ON = +3V, VEEXXX = 0V; LO_IN = 100 mV
unless otherwise stated.

3

Single ended Referred to 50Ω 50 350 mVpk

Z

V

f

LO
LOIN
LOIN

Local oscillator input frequency range
Differential input impedance Between LO_IN and LO_INX 276||0.6 Ω||pF
LO input sensitivity

4

Programmable divider:

division range
step size

at 704 MHz, CLKIN = 100mV

peak

MIN TYP MAX.

140 800 MHz

64

peak

LIMITS

1

at 22 MHz, Ta = 25°C,

511

f

CLK

Z

CLKIN

f

CMIN

f

CMAX

I

REF

|ICP|

I

CP

I

CP

I

CP_M

Serial Interface

f

CLOCK

t

SU

t

H

W

Reference clock maximum frequency
Differential input impedance Between ClkIN and Clk
CLK input sensitivity

4

Phase detector minimum comparison
frequency

Phase detector maximum comparison
freq

Charge pump reference current R

3

INX

1 44 MHz

10||

1.0

kΩ
pF

Referred to 50Ω 50 200 400 mVpk

1 MHz

Ref Divider = 44 2.5 MHz

= 50KΩ 31.25 µA

EXT

Charge pump output current:
C0...C2 = 000
C0...C2 = 111
step size

Relative output current variation

Output current matching

1

2

Output leakage current 0.2

I

= 31.25 µA

REF

VCP = VCCCP/2

I

= 31.25 µA

REF

I

= 31.25 µA

REF

VCP = VCCCP/2

0.160

0.320

0.023

0.200

0.400

0.029

1.3

0.240

0.480

0.035

8

12
15

mA
mA
mA

%

%

nA

Output current tolerance
with temperature
with output voltage

3

1
5

%

Clock frequency 10 MHz
Set–up time; DATA to clock,

CLOCK to STROBE

30 ns

Hold time: CLOCK to DATA 30 ns
Pulse width: CLOCK 30 ns
Pulse width: STROBE 30 ns

NOTES:



1. The relative output current variation is defined thus:

I

I

OUT

OUT

 2

.

II2 1

I2–I



1

; WITH V1 0.7V, V2 VCCCP–0.8V(seeFigure3).



1

2. The output current matching is measured when both (positive current and negative current) sections of the output charge pumps are on

3. Guaranteed by design.

4. Maximum level guaranteed by design.

1998 Jul 21

10

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

CURRENT

I

2

I

1

VOLTAGE

V

1

I

2

I

1

V

2

SR00526

Figure 3. Relative Output Current Variation

APPLICATION DESCRIPTION
General

The 1630 performs the IF modulator and demodulator functionality
for high–speed wireless data transceivers. The design is optimized
for IEEE 802.11 wireless LAN using 11 chips/symbol Direct
Sequence Spread Spectrum.

Transmitter

The IF quadrature transmitter baseband modulator input is driven
differentially by the D/A converters in the DSP chip. The baseband
signals are DC coupled for fast turn–on and turn–off and for
constant carrier testing. The typical common–mode input voltage is
VCC/2.
The open collector outputs of the mixers are biased by two
inductors, which are part of an LC tank. The LC tank matches the
output impedance of the mixers to the input impedance of the
upconverter chip (or any filter in between) and suppresses IF
harmonics.

An optional 2.5V reference is available during mode (3) and (5), the
transmit mode with Rx in standby. This reference can be enabled or
disabled via the 3 wire bus (in this mode). This voltage is provided
for use by an external current DAC if needed.

Receiver

The receiver part of the SA1630 consists of an IF Variable gain
amplifier, a quadrature demodulator and a pair of baseband
amplifiers. The IF amplifier has its gain controlled by the DSP chip.
This ensures linear operation of the receiver chain over a wide
dynamic range of input signals. Linear operation is essential for
resolving echo’s due to multipath reception.

The digital controlled AGC is meant for fast level training for the
receiver.

The high gain receiver, which is distributed between the IF and
baseband part facilitates interfacing with the RF front–end chip,
which normally have moderate gains (up to 20 dB), and SAW IF
filters, which mostly have considerable loss (up to 8 dB) without
external amplifiers.

The baseband amplifiers have a high drive capability (1 Vpp into
1kΩ, 15 pF for VCC = 3V) that facilitates direct interfacing to the A/D
converter without active external elements.

The baseband amplifiers can interface directly to the Track/Hold
switch/capacitor combination with capacitance values up to 15 pF.
When sampled at 22MHz the output can settle to within 1/4 LSB
when swinging 1V p–p.

The chip has a unique mode in which the Rx is on standby while the
Tx is ON. In this mode the Rx Baseband circuits are idling at
reduced currents and all Rx I/O outputs retain their DC bias
unchanged from their values when the Rx was fully ON. This mode
is very essential if ac coupling through a large capacitor, such as,
10nF is used. From this mode the chip can quickly be switched to
the Rx ON mode (Tx OFF) without worrying about
charging/discharging the large AC coupling capacitor.

The VGA can be programmed in 2 ways: 1) Directly programming
external control pins. 2) programming over the serial 3–wire bus.
The former method can switch gain in less than 200 ns.

The Rx baseband section also incorporates simple low pass active
filters of the Sallen key type. The Rx bandwidth is mainly set by
these filters. The function of these filters is twofold: 1) attenuate high
frequency signals from the Rx mixers. 2) act as anti–aliasing filters
for any A to D converters following this chip.

IF synthesizer

The SA1630 has an integrated synthesizer that uses an external
VCO operating on twice the IF frequency. It is internally divided by 2
for obtaining quadrature signals. The divided VCO signal is not
externally available. This minimizes the LO feedthrough to the IF
input port and hence minimizes output dc glitches when the IF gain
is switched.

The PLL reference clock is derived from the 22 MHz DSP clock. The
available divider ratios facilitate both 1 and 2 MHz phase
comparison frequency from a 22 MHz and an optional 44 MHz clock
respectively. In essence the reference divider will have
programmable dividers ratios of 8, 11, 22 and 44.

The VCO shall be fed from a stabilized supply. Such a stabilized
supply is necessary in order to prevent oscillator jitters due to Rx/Tx
switching. The effect of oscillator jitters is further minimized when
using a high PLL loop bandwidth, which on its turn requires a high
phase comparison frequency (1 MHz, preferably 2 MHz).

If the IF Synthesizer is not used, the CLK

pins should be

IN

terminated to ac ground.

Serial Programming Input

The serial input is a 3–wire input (CLOCK, STROBE, DATA) to
program the counter ratios, charge pump current, status– and
DC–offset register , mode select and test register. The programming
data is structured into two 21–bit words; each word includes 4 chip
address bits and 1 subaddress bit. Figure 2 shows the timing
diagram of the serial input. When the STROBE = L, the clock driver
is enabled and on the positive edges of the CLOCK the signal on
DATA input is clocked into a shift register. When the STROBE = H,

the clock is disabled and the data in the shift register remains stable.

Depending on the value of the subaddress bit the data is latched
into different working registers. Table 3 shows the contents of each
word.

Default States

Upon power up (VCCDIG is applied) a reset signal is generated,
which sets all registers to a default state. The logic level at the

1998 Jul 21

11

Philips Semiconductors Product specification



x0

x1

yg

SA1630IF quadrature transceiver

STROBE pin should be low during power up to guarantee a proper
reset. These default states are shown in Table 2.

Reference Divider

The reference divider can be programmed to four different division
ratios (:8, :11, :22, :44), see registers r0, r1; default setting: divide by

22.

Main Divider

The external VCO signal, applied to the LOIN and LOINX inputs, is
divided by two and then fed to the main divider (:N). The main
divider is a programmable 9 bit divider, the minimum division ratio is
divide by 64. The division ratio is binary coded and set in the
registers n0 to n8. The default setting is a divide by 352.

At the completion of a main divider cycle, a main divider output is
generated which will drive the phase detector.

Phase Detector

The phase detector is a D-type flip-flop phase and frequency
detector shown in Figure 5. The flip-flops are set by the negative
edges of the output signals of the dividers. The rising edge of the
signal L will reset the flip-flops after both flip-flops have been set.
Around zero phase error this has the effect of delaying the reset for
1 reference input cycle. This avoids non-linearity or deadband
around zero phase error. The flip-flops drive on-chip charge pumps.
A source current from the charge pump acts to increase the VCO
frequency; a sink current acts to decrease the VCO frequency.

Current Setting

The charge pump current is defined by the current set between the
pin I

and VEECP. The current value to be set there is 31.2µA.

REF

This current can be set by an external resistor to be connected
between the pin I
setting resistor) can be calculated with the formula

R

and VEECP. The typical value R

REF

V

CP–1.6V

CC

EXT



31.2

(44.87K for 3V)

A

EXT

(current

The current can be set to zero by connecting the pin I

to VCCCP.

REF

Charge Pumps

The charge pumps at pin CP are driven by the phase detector and
the current value is determined by the binary value of the charge
pumps register CN = c2, c1, c0, default .4mA. The active charge
pump current is typically:

|  (c0  2c1  4c2)  29A  200A

|I

CP

Lock Detect

The output LOCK is H when the phase detector indicates a lock
condition. This condition is defined as a phase difference of less
than ±1 cycle on the reference input CLK

, CLKINX.

IN

Test Modes (Synthesizer, Transmit Mixer)

The LOCK output is selectable as a test output. Bits x0, x1 control
the selection, the default setting is normal lock output as described
in the Lock detect section. The selection of a Bit x0, x1 combination
has a twofold effect: First it routes a divider output signal to the
LOCK pin, second it disables mixer stages in the transmit path.

Setting x0,1 = 11 disables both transmit path mixers. This mode can

be used to prevent the transmitter from producing an IF output
signal even if the transmit part is powered on. This can be used to
simplify the control timing while commanding the transmit and
receive simultaneously without the transmit part causing
interference.

Table 1. Test Modes

Synthesizer Signal

at LOCK Pin

0 0 normal lock detect on on
1 0
0 1 LOIN ÷ 2 * (main divider ratio) on off
1 1

CLKIN divided by reference

divider ratio

main divider output, that goes to

the phase detector

Transmit Mixer

Q-mixer I-mixer

off on

off off

1998 Jul 21

12

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

Table 2. Definition of SA1630 Serial Registers

First data word: (shown with default values)

Address SA1630

MSB LSB

a0 a1 a2 a3 sa n0 n1 n2 n3 n4 n5 n6 n7 n8 r0 r1 c0 c1 c2 x0 x1

1 1 1 0 0 1 0 1 1 0 0 0 0 0 1 0 1 1 1 0 0

Sub:Address: 1 bit, sa, fixed to 0 for first data word

Reference Divider Register: 2 bits, r0...r1, 00 = /8, 01 = 11, 10 = /22, 11 = /44. Default: 10

Charge-Pump Register: 3 bits, c0...c2, Binary setting factor for charge pumps, values 000 = minimum current to 111 = maximum

Test Register: 2 bits, x0...x1, default 00, see functional description for details

Second data word: (shown with default values)

Address SA1630

MSB LSB

a0 a1 a2 a3 sa s0 s1 i0 i1 i2 q0 q1 q2 b0 b1 b2 b3 b4 b5 bc vc

1 1 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1

Sub:Address: 1 bit, sa, fixed to 1 for second data word

LLL Mode control: 2 bits, s0, s1 Not used, always set to 0, 0

I Offset Register: 3 bits, i0...i2 .10 Not used, always set to 0, 0, 0
Q Offset Register: 3 bits, q0...q2. q0. Currently not being used, always set to 0, 0, 0
VGA Gain Control 6 bits, b0...b5. 000 000 corresponds to maximum gain and 111 111 to minimum gain in 2 dB increments.

VGA Control Enable 1 bit, bc. When bc=0 the VGA is controlled by external pins. When bc=1 then bits b0...b5 control the VGA.

Regulator Disable 1 bit, Vc. When Vc=0 the 2.5V reference output is completely powered down. When Vc=1 the reference

Sub
Adr

Address: 4 bits, a0...a3, fixed to 1110

N-Divider:

Address: 4 bits, a0...a3, fixed to 1110

9 bits, n0...n8, values 64 (00100 0000) to 511 (11111 1111) allowed for IF choice, default 352 (assuming LO
input frequency is 704 MHz).

current, default is maximum charge pump current (111)

Sub

LLL Mode

Adr

Control

Check control table contained elsewhere in this document.

Default bc=0, control by external pins

voltage is enabled (provided Tx_ON=HIGH). Default: Vc = 1, enable the 2.5 reference.

I Offset Register

N-Divider

Q Offset
Register

Reference

Divider

VGA Gain Control

Charge-Pump Test

Misc

Control

bits

1998 Jul 21

13

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

LSB MSB

DATA

X1 or t

t

SU

5

X0 or t

4

t

H

a

1

a

0

t

SU

STROBE

CLOCK

STROBE

CLOCK

CLK

50%

FIRST CLOCKLAST CLOCKFIRST CLOCK

t

SU

50%

CLOCK ENABLED

SHIFT IN DATA

t

W

CLOCK

DISABLED

STORE DATA

SR00527

Figure 4. Serial Input Timing Sequence

L

“1”

D

Q

IN

REFERENCE

DIVIDER

C

R

R

VCCCP

P

P-TYPE

CHARGE PUMP

LO

C

“1”

IN

CLK

÷2

IN

L

R

X

P

N

I

CP

MAIN

DIVIDER

X

R

D
C

Q

N

V

SS

P

N-TYPE

CHARGE PUMP

SR00528

Figure 5. Phase Detector Structure with Timing

1998 Jul 21

14

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

3V
SUPPLY

10m

PLL_ON

Rx_ON

GC0

GC1

GC2

1

VCCRx

100n

100n

1n

1n

2

3

4

5

6

7

8

9

GNDRx

Rx

V

CC

PLL_ON

Rx_ON

GNDHDR

GC0

GC1

GC2

GNDRX

GNDRX

RxIF IN

RxIF INX

GNDRX

TxIFOUT

TxIFOUTX

GNDTxRx
GNDTxRx

48

47

1.8p

46

44nH

45

44

43

42

41
40

5K

1.8p

17.4

294

294

1n

RxIN

TxOUT

GC3

GC4

GC5

15P

15P

I/Q GEN

1MHZ

FOR SSB

TESTING

(8MHZ

FOR DSB

TEST-

ING)

1K

1K

100nF

100n

10

11

12

13

14

15

16

17

18

19

20

21

22

GC3

GC4

GC5

GND_BB

GND_BB

V

__BB

CC

Q_RXOUT

I_RxOUT

I_TX IN

I_Tx INX

Q_Tx IN

Q_Tx INX

V

CC DIG

TXRX

V

CC

V

REF

GNDCP

VCCCP

DATA

CLOCK

STROBE

LOCK

LO INX

LO_IN

GNDRx

CLK IN

CLK INX

GNDDIG

Tx_ON

39

I0n

50W

100n

TX_ON

V

REF

CP

W

LO IN

CLKIN

10n

10n

10n

1n

20Ω

10n

10n

3 WIRE
SERIAL BUS

LOCK

38

2.5

37

I

REF

36

35

CP

34

33
32
31

30

29

28

27

26

25

24

23

1998 Jul 21

SR01550

Figure 6. Typical SA1630 Test Circuit

15

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

Supply Current Sleep Mode 1

22

20

18

16

14

Supply Current uA

12

10

–50 0 50 100

30
29

28

27
26

25

24

Supply Current mA

23
22

–50 0 50 100

Vs. Temperature and Supply

Temperature °C

Supply Current Transmit Mode 3

Vs. Temperature and Supply

Temperature °C

3.6 V

3 V

2.7 V

3.6 V
3 V

2.7 V

Supply Current Wait Mode 2
Vs. Temperature and Supply

20

19

18

17

16

Supply Current mA

15

14

–50 0 50 100

40

38

36
34

32

30

Supply Current mA

28

26

–50 0 50 100

Temperature °C

Supply Current Receive Mode 4

Vs. Temperature and Supply

Temperature °C

3.6 V

3 V

2.7 V

3.6 V

2.7 V

26

24

22

20

Supply Current mA

18

16

1998 Jul 21

Supply Current Transmit Mode 5

Vs. Temperature and Supply

3.6 V
3 V

2.7 V

–50 0 50 100

Temperature °C

Figure 7.

16

Receiver Third Harmonic Distortion

Vs. Temperature and Supply

40

dB below signal with Rx input
IVPP at maximum gain

38

2.7 V

36

3 V

34

3.6 V

32

Third Harmonic dB

30

28

–50 0 50 100

Temperature °C

SR01601

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

Receiver Maximum Gain

100

95

90

Gain dB

85

80

–50 0 50 100

–30
–32
–34

Carrier Suppression

–36
–38
–40
–42

Suppression dB

–44

3.6

–46

3

2.7 V

–48
–50

–50 0 50 100

Vs. Temperature and Supply

Temperature °C

Transmitter Carrier and

Sideband Suppression

Vs. Temperature and Supply

Sideband

Suppression

Temperature °C

3.6 V
3 V

2.7 V

2.7 V

3.6

Receiver AGC Gain Range

75

70

Gain Range dB

65

–50 0 50 100

–50

–55

3

–60

Distortion dBc

–65

–70

–50 0 50 100

Vs. Temperature and Supply

Temperature °C

Transmitter Third Harmonic Distortion

Vs. Temperature and Supply

Temperature °C

2.7 V
3 V

3.6 V

2.7 V
3

3.6

Current mA

1998 Jul 21

Transmitter AC Output Current

0.5
Average output at 353MHz
Input 1V

0.4

2.7V to 3,6 V

0.3

0.2

–50 0 50

Vs. Temperature and Supply

PP

Temperature °C

100

Figure 8.

17

P Charge Pump Current 000

–190

–195

–200

Current uA

–205

–210

–50 0 50

Vs. Temperature and Supply

Temperature °C

3.6

3

2.7 V

100

SR01600

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

P Charge Pump Current 111

Vs. Temperature and Supply

–390

–395

–400

–405

Current uA

–410

–415

–420

–50 0 50 100

Temperature °C

N Charge Pump Current 111

Vs. Temperature and Supply

410

405

400

Current uA

395

3.6

3

2.7 V

3.6
V

2.7 V

N Charge Pump Current 000
Vs. Temperature and Supply

205

200

3.6

Current uA

195

190

–50 0 50

5

0

3
V

–5

Current uA

–10

Temperature °C

Charge Pump Match 111

Vs. Temperature and Supply

3

2.7 V

100

2.7 V
3 V

3.6 V

390

–25

–27

–29

–31

Current uA

–33

–35

1998 Jul 21

–50 0 50 100

P Charge Pump Step Size

Vs. Temperature and Supply

2.7 V

3 V

3.6 V

–50 0 50 100

Temperature °C

Temperature C

Figure 9.

18

–15

–50 0 50 100

35

33

31

3.6 V

29

Current uA

3 V

2.7 V

27

25

–50 0 50 100

Temperature °C

N Charge Pump Step Size

Vs. Temperature and Supply

Temperature °C

SR01599

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

2.5 Reference Voltage Vs. Load

3.0

2.8

2.6

Reference Voltage V

2.4
–2.0 –1.2 –0.4 0.4 1.2 2.0

Vcc= 3V

–14
–16
–18
–20
–22
–24
–26

Output Level dBm

0 3 6 9 12 15

Vcc= 3V Gain= –70

3

Vcm – 0.7V to VCC–0.8V

and Temperature

Load Current mA

Receiver Filter Bandwidth Vs.
Frequency and Temperature

Output Frequency MHz

Charge Pump Relative Variation

Vs. Temperature and Supply

85°C
25°C

–40°C

25°C

–40°C

85°C

Transmitter Input Modulation

Bandwidth Vs. Frequency

–21
–22
–23
–24
–25

Output Level dBm

–26

0 4 8 12162024283236

Vcc = 3V

0.6

0.5

0.4

0.3

RMS Output mA rms

0.2

0.50 0.70 0.90 1.10 1.30 1.50

Vcc= 3V

Frequency MHz

Transmitter RMS Output Current

Vs. Input Voltage

Single Ended Input Vpp V

2

2.7 V

P Pump

Variation %

3 V

1

3.6 V

0

–50 0 50

N Pump 2.7V to 3.6V

Temperature °C

100

SR01602

Figure 10.

1998 Jul 21

19

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

1998 Jul 21

20

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

NOTES

1998 Jul 21

21

Philips Semiconductors Product specification

SA1630IF quadrature transceiver

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 07-98
Document order number: 9397 750 04166




1998 Jul 21

22