Datasheet S3C9614, S3P9614 Datasheet (Samsung)

S3C9614/P9614 PRODUCT OVERVIEW

1PRODUCT OVERVIEW

SAM87RI PRODUCT FAMILY

Samsung's SAM87RI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide range
of integrated peripherals, and supports OTP device.

A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.

S3C9614/P9614 MICROCONTROLLER

The S3C9614/P9614 microcontroller with USB function can be used in a wide range of general purpose
applications. It is especially suitable for mouse or joystick controller and is available in 20-pin DIP and 24-pin
SOP package.

The S3C9614/P9614 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built
around the powerful SAM87RI CPU core.

Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9614/P9614 has 4K-bytes of program
memory on-chip and 208 bytes of RAM including 16 bytes of working register.

Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core:
— Two configurable I/O ports (11 pins)

— 7 bit-programmable pins for external interrupts
— 8-bit timer/counter with two operating modes

OTP

The S3C9614 microcontroller is also available in OTP (One Time Programmable) version, S3P9614. S3P9614
microcontroller has an on-chip 4K-byte one-time-programmable EPROM instead of masked ROM. The S3P9614
is comparable to S3C9614, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW S3C9614/P9614

FEATURES

1-2

S3C9614/P9614 PRODUCT OVERVIEW

CPU

• SAM87RI CPU core

Memory

• 4K-byte internal program memory (ROM)

• 208-byte RAM

• 16 bytes of working register

Instruction Set

• 41 instructions

• IDLE and STOP instructions added for power­down modes

Instruction Execution Time

• 1.0 µs at 6 MHz f

OSC

Interrupts

• 12 interrupt sources with one vector

• One level, one vector interrupt structure

Oscillation Circuit Options

• 6 MHz crystal/ceramic oscillator

• External clock source

General I/O

• 11 bit-programmable I/O pins

Timer/Counter

• One 8-bit basic timer for watchdog function and
programmable oscillation stabilization interval
generation function

• One 8-bit timer/counter with Compare/Overflow
counter

USB Serial Bus

• Compatible to USB low speed (1.5 Mbps) device

1.0 specification.

• Serial bus interface engine (SIE)
— Packet decoding/generation
— CRC generation and checking
— NRZI encoding/decoding and bit-stuffing

• Two 8-byte receive/transmit USB buffer

Operating Temperature Range

• – 40°C to + 85°C

Operating Voltage Range

• 4.0 V to 5.25 V

Package Types

• 20-pin DIP

• 24-pin SOP

Comparator

• 4-channel mode, 4-bit resolution

• 3-channel mode, external reference
low EMI design

1-3

S3C9614/P9614 PRODUCT OVERVIEW

BLOCK DIAGRAM

X

X

IN

OUT

RESET

TEST

OSC

BASIC
TIMER

TIMER 0

I/O PORT AND

INTERRUPT CONTROL

SAM87RI

CPU

4-KB ROM

208-BYTE

REGISTER

Figure 1-1. Block Diagram

PORT 1/
COMPA­RATOR

PORT 0

USB

SIE

P1.0/CIN0/SCLK
P1.1/CIN1/SDAT
P1.2/CIN2
P1.3/CIN3
P1.4/INT1
P1.5/INT1
P1.6/INT1
P1.7/INT1

P0.0/INT0
P0.1/INT0
P0.2/INT0

D+
D-

3.3Vout

1-5

PRODUCT OVERVIEW S3C9614/P9614

PIN ASSIGNMENTS

VSS

XOUT

XIN

TEST
P0.0/INT0
P0.1/INT0

RESET

P0.2/INT0
P1.7/INT1
P1.6/INT1

1
2
3
4
5
6
7
8
9
10

S3C9614

20-DIP

(Top View)

20
19
18
17
16
15
14
13
12
11

VDD
P1.0/CIN0
P1.1/CIN1
P1.2/CIN2
P1.3/CIN3
P1.4/INT1
P1.5/INT1

3.3 VOUT
D+
D-

Figure 1-2. Pin Assignment Diagram (20-Pin DIP Package)

1-6

S3C9614/P9614 PRODUCT OVERVIEW

VSS

XOUT

XIN
NC

TEST
P0.0/INT0
P0.1/INT0

RESET

NC
P0.2/INT0
P1.7/INT1
P1.6/INT1

1
2
3
4
5
6
7
8
9
10
11
12

S3C9614

24-SOP

(Top View)

24
23
22
21
20
19
18
17
16
15
14
13

VDD
P1.0/CIN0
P1.1/CIN1
NC
P1.2/CIN2
P1.3/CIN3
P1.4/INT1
P1.5/INT1
NC

3.3 VOUT
D+
D-

Figure 1-3. Pin Assignment Diagram (24-Pin SOP Package)

1-7

PRODUCT OVERVIEW S3C9614/P9614

PIN DESCRIPTIONS

Table 1-1. S3C9614/P9614 Pin Descriptions

Pin

Names

P0.0–P0.2 I/O Bit-programmable I/O port for Schmitt trigger

Pin

Type

Pin

Description

Circuit

Number

Pin

Numbers

D 5, 6, 8 INT0
input or push-pull output. Pull-up resistors are
individually assignable to input pins by software
and are automatically disable for output pins.
Port0 can be individually configured as external
interrupt inputs.

P1.0–P1.3 I/O Bit-programmable I/O port for Schmitt trigger

F-8 19–16 CIN0–
input or push-pull output. Pull-up resistors are
individually assignable to input pins by software.
Port1.0–1.3 can be configured as comparator
input

P1.4-P1.7 I/O Bit-programmable I/O port for Schmitt trigger

D 15, 14, 10, 9 INT1
input or push-pull output. Pull-up resistors are
individually assignable to input pins by software
and are automatically disabled for output pins.
Port1.4–1.7 can be individually configured as
external interrupt inputs.

D+/D- I/O Only used as USB tranceive/receive port. – 12–11 –

3.3VOUT O Internal regulator 3.3 V output pin for referencing

– 13 –

the voltage

XIN, X

OUT

– System clock input and output pin

– 3–2 –
(crystal/ceramic oscillator, or external clock
source)

INT0 I External interrupt for bit-programmable port0. D 5, 6, 8 Port0
INT1 I External interrupt for bit-programmable port1 D 9, 10, 14, 15 Port1

RESET

I

RESET signal input pin.

TEST I Test signal input pin (for factory use only; must

– 7 –

– 4 –
be connected to VSS)

Share

Pins

CIN3

1-8

V

DD

V

SS

– Power input pin – 20 –
– VSS is a ground power for CPU core. – 1 –

S3C9614/P9614 PRODUCT OVERVIEW

Pin Circuits

Table 1-2. Pin Circuit Assignments for the S3C9614/P9614

Circuit Number Circuit Type S3C9614/P9614 Assignments

C O
D I/O Port0, Port1.4–1.7, INT0, INT1

F-8 I/O Port1.0–1.3

NOTE: Diagrams of circuit types C–D, and F-8 are presented below.

DATA

OUTPUT
DISABLE

V

DD

Figure 1-4. Pin Circuit Type C

OUT

V

PULL-UP

ENABLE

DATA

OUTPUT

DISABLE

CIRCUIT

TYPE C

Figure 1-5. Pin Circuit Type D

DD

IN/OUT

1-9

PRODUCT OVERVIEW S3C9614/P9614

V

DD

PULL-UP

ENABLE

V

DD

DATA

OUTPUT

CIRCUIT

TYPE C

IN/OUT

DISABLE

ANALOG/

EXTERNAL

VREF INPUT

Figure 1-6. Pin Circuit Type F-8

1-10

S3C9614/P9614 PRODUCT OVERVIEW

Right Button

KS86P6104

CON_B

C3

X

X

V

V

IN

OUT

DD

SS

S3C9614

P0.0/INT0

P0.1/INT0

Button

1 2 3

Left Button

Button

1 2 3

USB Cable

5
4
3
2
1

C4

R1

R2

C1 R3

C2

V3.3

D-

D+

RESET

P0.2/INT0

P1.7/INT1

P1.3/CIN3

P1.2/CIN2

P1.1/CIN1

P1.0/CIN0

5
4
3

Array 4

2
1

2

1
2
3

1
2
3

+

1
2

+

1

Figure 1-7. USB Mouse Circuit Diagram

1-11

S3C9614/P9614 ELECTRICAL DATA

13 ELECTRICAL DATA

OVERVIEW

In this section, the following S3C9614/P9614 electrical characteristics are presented in tables and graphs:
— Absolute maximum ratings

— D.C. electrical characteristics
— I/O capacitance
— A.C. electrical characteristics

— Input timing for RESET
— Oscillator characteristics
— Operating voltage range
— Oscillation stabilization time
— Clock timing measurement points at X

— Data retention supply voltage in Stop mode

IN

— Stop mode release timing when initiated by a RESET
— Stop mode release timing when initiated by an external interrupt
— Characteristic curves
— Comparator Electrical Characteristics

13-1

ELECTRICAL DATA S3C9614/P9614

Table 13-1. Absolute Maximum Ratings

(TA = 25°C)

Parameter Symbol Conditions Rating Unit

Supply voltage V
Input voltage V
Output voltage V
Output current high I

DD

IN
O

OH

All in ports – 0.3 to V
All output ports – 0.3 to VDD + 0.3 V
One I/O pin active – 18 mA

– – 0.3 to + 6.5 V

+ 0.3 V

DD

All I/O pins active – 60

Output current low I

OL

One I/O pin active + 30 mA
Total pin current for ports 0, 1 + 100

Operating

T

A

– – 40 to +85 °

C

temperature
Storage

T

STG

– – 65 to + 150 °

C

temperature

13-2

S3C9614/P9614 ELECTRICAL DATA

Table 13-2. D.C. Electrical Characteristics

(T

= – 40°C to + 85°C, VDD = 4.0 V to 5.25 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Input highvoltage V

Input low voltage V

Output high voltage V

IH1

V

IH2

V

OH

IL1
IL2

All input pins except V
X

IN

All input pins except V
X

IN

VDD = 4.5 V – 5.5 V

D+, D– 0.8 V

IH2,

D+, D– – – 0.2 V

IL2,

DD

V

– 0.5 V

DD

– V

– – 0.4

V

– 1.0 – – V

DD

DD
DD

DD

V

V

IOH = – 200 µA
All output ports except D+, D–

Output low voltage V

OL

V

= 4.5 V – 5.5 V

DD

– – 0.4 V

IOL = 2 mA
All output ports except D+, D–

Input high leakage
current

I

LIH1

VIN = V

DD

All inputs except I

– – 3 µA

LIH2

except D+, D–

Input low leakage
current

I

LIH2

I

LIL1

VIN = V
X

V

, X

IN

= 0 V

IN

DD

OUT

All inputs except I

– – 20

– – – 3 µA

LIL2

except D+, D–

I

Output high leakage

I

current
Output low leakage

I

current
Pull-up resistors R

LIL2

LOH

LOL

R

V

= 0 V

IN

X

OUT, XIN

V

= V

OUT

DD

All output pins except D+, D–
V

= 0 V

OUT

All output pins except D+, D–
V

L1
L2

IN

V

IN

= 0 V; V
= 0 V; V

DD
DD

– – – 20

– – 3 µA

– – – 3 µA

= 5.0 V, 25 50 100
= 5.0 V,

100 220 400

KΩ

RESET only

Supply current

(note)

I

DD1

Normal operation mode

–

6.5 15 mA

6-MHz CPU clock

I

DD2

Idle mode;

– 4 8 mA

6-MHz CPU clock

I

DD3

Stop mode;

– 150 300 µA

oscillator stop

NOTES:

1. Supply current does not include current drawn through internal pull-up resistors or external output current load.

2. This parameter is guaranteed, but not tested (include D+, D–).

3. Only in 4.2 V to 5.25 V, D+ and D– satisfy the USB spec 1.0.

13-3

ELECTRICAL DATA S3C9614/P9614

Table 13-3. Input/Output Capacitance

(TA = – 40°C to + 85°C, V

DD

= 0 V)

Parameter Symbol Conditions Min Typ Max Unit

Input
capacitance

Output

C

C

OUT

IN

f = 1 MHz; unmeasured pins

are connected to V

SS

– – 10 pF

capacitance
I/o capacitance C

IO

Table 13-4. A.C. Electrical Characteristics

(T

= – 40°C to + 85°C, V

A

= 4.0 V to 5.25 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Noise filter t

RESET input

NF1H

t

NF2

t

RSL

, t

P1 (RC delay) 100 – 200 ns

NF1L

RESET only (RC delay)

– 800 –

Input 10 – –

low width

t

NF1L

t

NF1H

t

NF2

µs

RESET

0.8 V

DD

0.2 V

DD

t

RSL

Figure 13-1. Input Timing for RESETRESET

0.5V

DD

0.5 V

DD

13-4

S3C9614/P9614 ELECTRICAL DATA

Table 13-5. Oscillator Characteristics

(TA = – 40°C + 85°C)

Oscillator Clock Circuit Test Condition Min Typ Max Unit

Main crystal Main
ceramic
(f

)

OSC

C1

C2

X

X

IN

OUT

Oscillation frequency
VDD = 4.0 V – 5.25 V

– 6.0 – MHz

External clock

X

X

IN

OUT

Oscillation frequency
VDD = 4.0 V – 5.25 V

– 6.0 –

Table 13-6. Oscillation Stabilization Time

(TA = – 40°C + 85°C, VDD = 4.0 V to 5.25 V)

Oscillator Test Condition Min Typ Max Unit

Main crystal VDD = 4.5 V to 5.5 V, f
Main ceramic

(Oscillation stabilization occurs when VDD is equal to

> 6.0 MHz – – 10 ms

OSC

the minimum oscillator voltage range.)

Oscillator
stabilization wait

t

stop mode release time by a reset –

WAIT

216/f

OSC

time

t

stop mode release time by an interrupt – – –

WAIT

NOTE: The oscillator stabilization wait time, t

basic timer control register, BTCON.

, when it is released by an interrupt, is determined by the setting in the

WAIT

–

13-5

ELECTRICAL DATA S3C9614/P9614

1 / f

OSC

t

XL

X

IN

Figure 13-2. Clock Timing Measurement Points at X

t

XH

V

– 0.5 V

DD

0.4 V

IN

Table 13-7. Data Retention Supply Voltage in Stop Mode

(TA = 0°C to + 70°C)

Parameter Symbol Conditions Min Typ Max Unit

Data retention

V

DDDR

Stop mode 2.0 – 6 V

supply voltage
Data retention

I

DDDR

Stop mode; V

= 2.0 V – – 5 µA

DDDR

supply current

13-6

S3C9614/P9614 ELECTRICAL DATA

INTERNAL

IDLE MODE
(BASIC TIMER
ACTIVE)

NORMAL
OPERATING
MODE

V

DD

RESET

EXECUTION OF

STOP

∼∼∼

∼∼∼

RESET

∼

STOP MODE

DATA RETENTION MODE

∼

V

DDDR

0.5 V

DD

t

WAIT

V

DD

EXTERNAL
INTERRUPT

Figure 13-4. Stop Mode Release Timing When Initiated by an External Interrupt

Figure 13-3. Stop Mode Release Timing When Initiated by a RESETRESET

∼∼∼

∼

∼∼∼

∼

EXECUTION OF

STOP INSTRUCTION

STOP MODE

DATA RETENTION MODE

V

DDDR

0.2 V

DD

t

WAIT

0.8 V

IDLE MODE
(BASIC TIMER
ACTIVE)

NORMAL
OPERATING
MODE

DD

13-7

ELECTRICAL DATA S3C9614/P9614

Table 13-8. Comparator Electrical Characteristics

(T

= – 40°C to + 85°C, V

A

= 4.0 V to 5.25 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Conversion time

(1)

tCON – –

4 × 2

4

– F

CPU

or

7

4 × 2

Comparator input

V

ICN

– V

SS

– V

DD

V

voltage
Comparator input

R

CN

– 2 1000 –

MΩ

impedance
Comparator

V

REF

– 1.8 – V

DD

V

reference voltage
Comparator input

I

CIN

VDD = 5 V – 3 – 3

µA

current
Reference input

I

REF

VDD = 5 V – 3 – 3

µA

current
Comparator block I
current

(2)

COM

VDD = 5.5 V – 1 2 mA
VDD = 4.5 V 0.5 1 mA
VDD = 5 V

100 500 nA

(when power down mode)

NOTES:

1. Conversion time is the time required from the moment a conversion operation starts until it ends.

2. I

is an operating current during conversion.

COM

13-8

S3C9614/P9614 ELECTRICAL DATA

Table 13-9. Low Speed Source Electrical Characteristics (USB)

(TA = – 40°C to + 85°C, Voltage Regulator Output V

= 2.8 V to 3.5 V, typ 3,3 V)

33out

Parameter Symbol Conditions Min Max Unit

Transition Time:
Rise Time Tr CL = 50 pF 75 – ns

CL = 350 pF – 300

Fall Time Tf CL = 50 pF 75 –

CL = 350 pF – 300
Rise/Fall Time Matching Trfm (Tr/Tf) CL = 50 pF 70 130 %
Output Signal Crossover Voltage Vcrs CL = 50 pF 1.3 2.0 V
Voltage Regulator Output Voltage V33OUT

with V33OUT to GND 0.1 µF

2.8 3.5 V

capacitor

D.U.T

R1

Point

S/W

CL

2.8VTest

R2

10%

90% 90%

MEASUREMENT

POINTS

Tr Tf

10%

R1 = 15 K
R2 = 1.5 K
CL = 50pF-350pF

Ω

Ω

DM: S/W ON
DP: S/W OFF

Figure 13-5. USB Data Signal Rise and Fall Time

DP

Vcrs

DM

3.3 V

MAX: 2.0 V
MIN: 1.3 V

0 V

Figure 13-6. USB Output Signal Crossover Point Voltage

13-9

S3C9614/P9614 MECHANICAL DATA

14 MECHANICAL DATA

OVERVIEW

This section contains the following information about the device package:
— Package dimensions in millimeters

— Pad diagram

#20 #11

20-DIP-300A

6.40 ± 0.2

(1.77) 1.52 ± 0.1

NOTE: Dimensions are in millimeters.

#1 #10

26.80 MAX

26.40 ± 0.2

0.46 ± 0.1

2.54

7.62

3.25 ± 0.2

0.51MIN

5.08MAX

3.30 ± 0.3

+0.1

0.25

0-15

– 0.05

°

Figure 14-1. 20-DIP0300A Package Dimensions

14-1

MECHANICAL DATA S3C9614/P9614

#24 #13

24-SOP-375

10.30 ± 0.3

#1 #12

15.74 MAX

15.34

(0.69) 0.38 ± 0.1

± 0.2

1.27

0.15

2.30 ± 0.2

0.05MIN

7.50 ± 0.2

+0.10

- 0.05

2.70MAX

0.10 MAX

0-8°

9.53

0.85±0.20

NOTE: Dimensions are in millimeters.

Figure 14-2. 24-SOP-375 Package Dimensions

14-2

S3C9614/P9614 S3P9614 OTP

15 S3P9614 OTP

OVERVIEW

The S3P9614 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9614

microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.

The S3P9614 is fully compatible with the S3C9614, both in function and in pin configuration. Because of its
simple programming requirements, the S3P9614 is ideal for use as an evaluation chip for the S3C9614.

VSS/VSS

XOUT

XIN

TEST/TEST

P0.0/INT0
P0.1/INT0

RESETRESET/RESET

P0.2/INT0
P1.7/INT1
P1.6/INT1

Figure 15-1. S3P9614 Pin Assignments (20-DIP Package)

1
2
3
4
5
6
7
8
9
10

S3P9614

20-DIP

(Top View)

20
19
18
17
16
15
14
13
12
11

VDD/VDD
P1.0/CIN0/SCLK
P1.1/CIN1/SDAT
P1.2/CIN2
P1.3/CIN3
P1.4/INT1
P1.5/INT1

3.3 VOUT
D+
D-

15-1

S3P9614 OTP S3C9614/P9614

VSS/VSS

XOUT

XIN

NC

TEST/TEST

P0.0/INT0
P0.1/INT0

RESET/RESET

NC
P0.2/INT0
P1.7/INT1
P1.6/INT1

1
2
3
4
5
6
7
8
9
10
11
12

S3P9614

24-SOP

(Top View)

24
23
22
21
20
19
18
17
16
15
14
13

VDD/VDD
P1.0/CIN0/SCLK
P1.1/CIN1/SDAT
NC
P1.2/CIN2
P1.3/CIN3
P1.4/INT1
P1.5/INT1
NC

3.3 VOUT
D+
D-

Figure 15-2. S3P9614 Pin Assignments (24-SOP Package)

15-2

S3C9614/P9614 S3P9614 OTP

Table 15-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No.

I/O Function

(20 DIP)

P1.0 (Pin 18) SDAT 18 I/O Serial Data Pin (Output when reading, Input

when writing) Input and Push-pull Output Port
can be assigned

P1.1 (Pin 19) SCLK 19 I/O Serial Clock Pin (Input Only Pin)

V

TEST

PP

(TEST)

4 I 0V : OTP write and test mode

5V : Operating mode

RESET RESET

7 I Chip Initialization and EPROM Cell Writing

Power Supply Pin (Indicates OTP Mode
Entering) When writing 12.5V is applied and
when reading.

VDD/V

SS

VDD/V

SS

20/1 I Logic Power Supply Pin.

Table 15-2. Comparison of S3P9614 and S3C9614 Features

Characteristic S3P9614 S3C9614

Program Memory 4 K byte EPROM 4 K byte mask ROM
Operating Voltage (VDD)

OTP Programming Mode

4.0 V to 5.25 V 4.0 V to 5.25 V
VDD = 5 V, V

(RESET)=12.5V

PP

Pin Configuration 20 DIP/24 SOP 20 DIP/24 SOP
EPROM Programmability User Program 1 time Programmed at the factory

15-3

S3P9614 OTP S3C9614/P9614

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the V

(RESET) pin of the S3P9614, the EPROM programming mode is entered.

PP
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 14-3 below.

Table 15-3. Operating Mode Selection Criteria

V

DD

V

PP

(RESETRESET)

REG/

MEMMEM

Address
(A15-A0)

R/W Mode

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

Table 15-4. D.C. Electrical Characteristics

(T

= – 40°C to + 85°C, VDD = 4.0 V to 5.25 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Supply Current

(note)

I

DD1

Normal mode;

– 6.5 15 mA

6 MHz CPU clock

I

DD2

Idle mode;

4 8

6 MHz CPU clock

I

DD3

Stop mode;

150 300

µA

oscillator stop

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

15-4

S3C9614/P9614 S3P9614 OTP

START

Address= First Location

VDD=5V, VPP=12.5V

x = 0

Program One 1ms Pulse

Increment X

FAIL

Device Failed

Verify Byte

YES

x = 10

NO

FAIL

NO

FAIL

Verify 1 Byte

Last Address

V

= VPP= 5 V

DD

Compare All Byte

PASS

Device Passed

Figure 15-3. OTP Programming Algorithm

Increment Address

15-5