Datasheet S3C7044, S3C7048, S3P7048 Datasheet (Samsung)

S3C7044/C7048/P7048 PRODUCT OVERVIEW

1PRODUCT OVERVIEW

The S3C7044/C7048 single-chip CMOS microcontroller has been designed for very high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

The S3P7048 is the microcontroller which has 8K-bytes one-time-programmable ROM and the functions are
same to S3C7044/C7048.

With two 8-bit timer/counters, an 8-bit serial I/O interface, and eight software n-channel open-drain I/O pins, the
S3C7044/C7048 offers an excellent design solution for a wide variety of general-purpose applications.

Up to 36 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts
provide fast response to internal and external events.

In addition, the S3C7044/C7048's advanced CMOS technology provides for low power consumption and a wide
operating voltage range.

1-1

PRODUCT OVERVIEW S3C7044/C7048/P7048

FEATURES SUMMARY

Memory

• 512 × 4-bit RAM

• 4096 × 8-bit ROM: S3C7044

• 8192 × 8-bit ROM: S3C7048

36 I/O Pins

• Input only: 4 pins

• I/O: 24 pins

• N-channel open-drain I/O: 8 pins

Memory-Mapped I/O Structure

• Data memory bank 15

8-Bit Basic Timer

• 4 interval timer functions

Two 8-Bit Timer/Counters

• Programmable interval timer

• External event counter function

• Timer/counters clock outputs to TCLO0 and

TCLO1 pins

Bit Sequential Carrier

• Supports 16-bit serial data transfer in arbitrary
format

Interrupts

• 3 external interrupt vectors

• 4 internal interrupt vectors

• 2 quasi-interrupts

Power-Down Modes

• Idle: Only CPU clock stops

• Stop: System clock stops

Oscillation Sources

• Crystal or Ceramic for system clock

• Oscillation frequency : 0.4 – 6.0MHz

• CPU clock divider circuit (by 4. 8, or 64)

Instruction Execution Times

• 0.95, 1.91, 15.3 µs at 4.19 MHz

• 0.67, 1.33, 10.7 µs at 6.0 MHz

Watch Timer

• Time interval generation: 0.5 s, 3.9 ms at

4.19 MHz

• 4 frequency outputs to the BUZ pin

8-Bit Serial I/O Interface

• 8-bit transmit/receive mode

• 8-bit receive mode

• LSB-first or MSB-first transmission selectable

1-2

Operating Temperature

• - 40 °C to 85 °C

Operating Voltage Range

• 1.8 V to 5.5 V (Main)

• 2.0 V to 5.5 V (OTP)

Package Types

• 42-pin SDIP, 44-pin QFP

S3C7044/C7048/P7048 PRODUCT OVERVIEW

FUNCTION OVERVIEW

SAM47 CPU

All S3C7-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up
to 32K-byte of program memory. The arithmetic logic unit(ALU) performs 4-bit addition, subtraction, logical, and
shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operation in two cycles.

CPU REGISTERS
program counter

A 12-bit program counter (PC) stores addresses for instruction fetches during program execution. Usually, the PC
is incremented by the number of bytes of the fetched instruction. The one instruction fetch that does not
increment the PC is the 1-byte REF instruction which references instruction stored in a look-up table in the ROM.
Whenever a reset operation or an interrupt occurs, bits PC12 though PC0 are set to the vector address.

Stack pointer

An 8-bit stack pointer (SP) stores addresses for stack operation. The stack area is located in general-purpose
data memory bank 0. The SP is 8-bit read/writeable and SP bit 0 must always be logic zero.

During an interrupt or a subroutine call, the PC value and the PSW are written to the stack area. When the
service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruction
is executed.

The stack pointer can access the stack despite data memory access enable flag status. Since the reset value of
the stack pointer is not defined in firmware, you use program code to initialize the stack pointer to 00H. This sets
the first register of the stack area to data memory location 0FFH.

PROGRAM MEMORY

In its standard configuration, the 4096 x 8-bit (S3C7404), 8192 x 8-bit (S3C7408) ROM is divided into four areas:

 16-byte area for vector addresses
 96-byte instruction reference area
 16-byte general-purpose area (0010 – 001FH)
 3968-byte area for general-purpose program memory (S3C7404)
 8064-byte area for general-purpose program memory (S3C7408)

The vector address area is used mostly during reset operation and interrupts. These 16 bytes can alternately be
used as general-purpose ROM.

The REF instruction references 2x1-byte or 2-byte instruction stored in reference area location 0020H – 007FH.
REF can also reference three-byte instruction such as JP or CALL. So that a REF instruction can reference these
instruction, however, the JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is written to
the reference area with the format TJP or TCALL instead of the normal instruction name. Unused location in the
REF instruction look-up area can be allocated to general-purpose use.

1-3

PRODUCT OVERVIEW S3C7044/C7048/P7048

DATA MEMORY
Overview

The 512 x 4bit data memory has five areas:

 32 x 4-bit working register area
 224 x 4-bit general-purpose area in bank 0 which is also used as the stack area
 256 x 4-bit general-purpose area in bank 1
 128 x 4-bit area in bank 15 for memory-mapped I/O addresses

The data memory area is also organized as three memory banks  bank0, bank1, and bank15. You use the
select memory bank instruction (SMB) to select one of the banks as working data memory.

Data stored in RAM location are 1-, 4-, and 8-bit addressable. After a hardware reset, data memory initialization
values must be defined by program code.

Data Memory addressing modes

The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, or 15. When the
EMB flag is logic zero, only location 00H–7FH of bank 0 and bank 15 can be accessed. When the EMB flag is
set to logic one, all three data memory banks can be accessed based on the current SMB value.

Working registers

The RAM's working register area in data memory bank 0 is also divided into four register banks. Each register
bank has eight 4-bit registers. Paired 4-bit registers are 8-bit addressable.

Register A can be used as a 4-bit accumulator and double register EA as an 8-bit extended accumulator; double
registers WX, WL, and HL are used as address pointers for indirect addressing.

To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use bank 0 for
main programs and banks 1, 2, and 3 for interrupt service routines.

Bit sequential carrier

The bit sequential carrier (BSC) mapped in data memory bank 15 is a 16-bit general register that you can
manipulate using 1-, 4-, and 8-bit RAM control instructions.

Using the BSC register, addresses and bit location can be specified sequentially using 1-bit indirect addressing
instructions. In this way, a program can generate 16-bit data output by moving the bit location sequentially,
incrementing or decrementing the value of the L register. You can also use direct addressing to manipulate data
in the BSC.

1-4

S3C7044/C7048/P7048 PRODUCT OVERVIEW

CONTROL REGISTERS
Program Status Word

The 8-bit program status word (PSW) controls ALU operation and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory access enable flags.

Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine is
completed, PSW values are restored.

IS1 IS0 EMB ERB

C SC2 SC1 SC0

Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag ( C ) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0–SC2) can be
addressed using 8-bit read instructions only.

Select Bank (SB) Register

Two 4-bit location called the SB register store address values used to access specific memory and register
banks: the select memory bank register, SMB, and the select register bank register, SRB.

'SMB n' instructions select a data memory bank (0, 1, or 15) and store the upper four bits of the 12-bit data
memory address in the SMB register. The 'SMB n' instruction is used to select register bank 0, 1, 2, or 3, and to
store the address data in the SRB.

The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and
subroutines.

CLOCK CIRCUITS

System oscillation circuit generates the internal clock signals for the CPU and peripheral hardwares. The system
clock can use a crystal, ceramic, or RC oscillation source, or an externally-generated clock signal. To drive
S3C7044/C7048 using an external clock source, the external clock signal should be input to Xin, and its inverted

signal to X

out

.

A 4-bit power control register is used to enable or disable oscillation, and to select the CPU clock. The internal
system clock signal (fx) can be divided internally to produce three CPU clock frequencies  fx/4, fx/8, or fx/64.

INTERRUPTS

Interrupt requests can be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or
externally by peripheral devices (INT0, INT1, and INT4). There are two quasi-interrupts: INT2 and INTW.

INT2/KS0–KS7 detects rising/falling edges of incoming signals and INTW detects time intervals of 0.5 seconds
of 3.91 milliseconds at 4.19MHz. The following components support interrupt processing:

 Interrupt enable flags
 Interrupt request flags
 Interrupt priority registers
 Power-down termination circuit

1-5

PRODUCT OVERVIEW S3C7044/C7048/P7048

POWER-DOWN

To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle
mode and the STOP instruction initiates stop mode.

In idle mode, only the CPU clock stops while peripherals and the oscillation source continue to operate normally.
Stop mode effects only the system clock. In stop mode system clock oscillation stops completely, halting all

operations except for a few basic peripheral functions. RESET or an interrupt (with the exception of INT0) can be
used to terminate either idle or stop mode.

RESETRESET

When a RESET signal occurs during normal operation or during power-down mode, the CPU enters idle mode
when the reset operation is initiated. When the standard oscillation stabilization interval (31.3 ms at 4.19 MHz)
has elapsed, normal CPU operation resumes.

I/O PORTS

The S3C7044/C7048 has 9 I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H–FFCH in
bank 15 of the RAM.

There are 4 input pins, 24 configurable I/O pins, and 8 software n-channel open-drain I/O pins, for a total of 36
I/O pins. The contents of I/O port pin latches can be read, written, or tested at the corresponding address using
bit manipulation instructions.

TIMERS AND TIMER/COUNTERS

The timer function has four main components: an 8-bit basic interval timer, two 8-bit timer/counters, and a watch
timer. The 8-bit basic timer generates interrupt requests at precise intervals, based on the selected CPU clock
frequency.

The programmable 8-bit timer/counters are used for external event counting, generation of arbitrary clock
frequencies for output, and dividing external clock signals. The 8-bit timer/counter 0 generates a clock signal

(SCK) for the serial I/O interface.
The watch timer has an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. Its

functions include real-time and watch-time measurement, and frequency outputs for buzzer sound.

SERIAL I/O INTERFACE

The serial I/O interface supports the transmission or reception of 8-bit serial data with an external device. The
serial interface has the following functional components:

 8-bit mode register
 Clock selector circuit
 8-bit buffer register
 3-bit serial clock counter

The serial I/O circuit can be set either to transmit-and-receive or to receive-only mode. MSB-first or LSB-first
transmission is also selectable. The serial interface operates with an internal or an external clock source, or using
the clock signal generated by the 8-bit timer/counter 0. To modify transmission frequency, the appropriate bits in
the serial I/O mode register (SMOD) must be manipulated.

1-6

S3C7044/C7048/P7048 PRODUCT OVERVIEW

BLOCK DIAGRAM

P4.0–P4.3

P5.0–P5.3

P6.0–P6.3 /

KS0–KS3

P7.0–P7.3 /

KS4–KS7

P8.0–P8.3

INT0, INT1,

INT2,INT4

8-BIT

TIMER/

COUNTER 0

8-BIT

TIMER/

COUNTER 1

I/O PORT 4

I/O PORT 5

I/O PORT 6

I/O PORT 7

I/O PORT 8

RESET

INTERRUPT

CONTROL

BLOCK

INTERNAL

INTERRUPTS

INSTRUCTION DECODER

ARITHMETIC

LOGIC UNIT

512 x 4-BIT

DATA

MEMORY

Xin Xout

AND

CLOCK

BASIC

TIMER

INSTRUCTION

REGISTER

PROGRAM
COUNTER

PROGRAM

STATUS WORD

STACK

POINTER

PROGRAM MEMORY

4 KBYTE: S3C7404
8 KBYTE: S3C7408

WATCH

TIMER

I/O PORT 0

SERIAL

I/O

INPUT

PORT 1

I/O PORT 2

I/O PORT 3

P0.0 /

SCK

P0.1 / SO
P0.2 / SI
P0.3 / BTCO

P1.0 / INT0
P1.1 / INT1
P1.2 / INT2
P1.3 / INT4

P2.0 / TCLO0
P2.1 / TCLO1
P2.2 / CLO
P2.3 / BUZ

P3.0 / TCL0
P3.1 / TCL1
P3.2
P3.3

Figure 1-1. S3C7044/C7048/P0408 Block Diagram

1-7

PRODUCT OVERVIEW S3C7044/C7048/P7048

PIN ASSIGNMENTS

P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0

P2.3/BUZ

P2.2/CLO
P2.1/TCLO1
P2.0/TCLO0

P0.3/BTCO

P0.2/SI

P0.1/SO

P0.0/SCK

P8.3
P8.2
P8.1
P8.0
P3.3

P3.2
P3.1/TCL1
P3.0/TCL0

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

42
41
40
39
38

S3C7044/C7048

(42-SDIP-600)

37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

VSS
P7.0/KS4
P7.1/KS5
P7.2/KS6
P7.3/KS7
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
XIN
XOUT

RESET

P5.0
P5.1
P5.2
P5.3
P4.0
P4.1
P4.2
P4.3
TEST

Figure 1-2. S3C7044/C7048 Pin Assignment Diagrams (42-SDIP Pakage)

1-8

S3C7044/C7048/P7048 PRODUCT OVERVIEW

P3.1/TCL1

P3.0/TCL0

P5.3
P5.2
P5.1
P5.0

RESET

XOUT

XIN
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0

P4.0

4443424140393837363534

1
2
3
4
5

S3C7044/C7048

6

(44-QFP-1010B)

7
8
9
10
11

1213141516171819202122

P7.3/KS7

P7.2/KS6

VDD

VSS

P7.1/KS5

P7.0/KS4

P1.3/INT4

P1.2/INT2

TEST

P4.3

P4.2

P4.1

P3.3

P3.2

NC

P2.3/BUZ

P1.1/INT1

P2.2/CLO

P1.0/INT0

33
32
31
30
29
28
27
26
25
24
23

NC
P8.0
P8.1
P8.2
P8.3
P0.0/SCK
P0.1/SO
P0.2/SI
P0.3/BTCO
P2.0/TCLO0
P2.1/TCLO1

Figure 1-3. S3C7044/C7048 Pin Assignment Diagrams (44-QFP Pakage)

1-9

PRODUCT OVERVIEW S3C7044/C7048/P7048

PIN DESCRIPTIONS

Table 1-1. S3C7044/C7048/P0408 Pin Description

Pin Name Pin Type Description Number Share Pin

P0.0
P0.1
P0.2
P0.3

P1.0
P1.1
P1.2
P1.3

P2.0
P2.1
P2.2
P2.3

P3.0
P3.1
P3.2
P3.3

P4.0–P4.3
P5.0–P5.3

P6.0–P6.3
P7.0–P7.3

P8.0–P8.3 I/O 4-bit I/O ports.

I/O 4-bit I/O port.

1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.

12 (28)
11 (27)
10 (26)

9 (25)
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.

I 4-bit input port.

1-bit and 4-bit read and test is possible.
3-bit pull-up resistors are assignable by software to
pins P1.0, P1.1, and P1.2.

4 (20)

3 (19)

2 (18)

1 (17)

I/O Same as port 0. 8 (24)

7 (23)

6 (22)

5 (21)

I/O Same as port 0. 20 (38)

19 (37)
18 (36)
17 (35)

I/O 4-bit I/O ports.

N-channel open-drain output up to 9 volts.
1-bit and 4-bit read/write and test is possible.
Ports 4 and 5 can be paired to support 8-bit data

26–23

(44–41)

30–27

(4–1)
transfer.
8-bit unit pull-up resistors are assignable by mask
option.

I/O 4-bit I/O ports.

1-bit or 4-bit read/write and test is possible.
Port 6 pins are individually software configurable as
input or output.

37–34

(11–8)

41–38

(15–12)
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins
(port 6 only).
Ports 6 and 7 can be paired to enable 8-bit data
transfer.

16–13

1-bit and 4-bit read/write and test is possible.

(32–29)
Pins are individually software configurable as input or
output.
4-bit pull-down resistors are software assignable;
pull-down resistors are automatically disabled for
output pins.

SCK

SO

SI

BTCO

INT0
INT1
INT2
INT4

TCLO0
TCLO1

CLO
BUZ

TCL0
TCL1

–

KS0–KS3
KS4–KS7

–

NOTE: Parentheses indicate pin number for 44 QFP package.

1-10

S3C7044/C7048/P7048 PRODUCT OVERVIEW

Table 1-1. S3C7044/C7048 Pin Descriptions (Continued)

Pin Name Pin Type Description Number Share

Pin

SCK

I/O Serial I/O interface clock signal 12 (28) P0.0

SO I/O Serial data output 11 (27) P0.1
SI I/O Serial data input 10 (26) P0.2
BTCO I/O Basic timer clock output (2 Hz, 16 Hz, 64 Hz, or 256

9 (25) P0.3

Hz at 4.19 MHz)

INT0, INT1 I External interrupts. The triggering edge for INT0 and

INT1 is selectable. INT0 is synchronized to system

4, 3

(20, 19)

P1.0, P1.1

clock.
INT2 I Quasi-interrupt with detection of rising edges 2 (18) P1.2
INT4 I External interrupt with detection of rising and falling

1 (17) P1.3

edges.
TCLO0 I/O Timer/counter 0 clock output 8 (24) P2.0
TCLO1 I/O Timer/counter 1 clock output 7 (23) P2.1
CLO I/O Clock output 6 (22) P2.2
BUZ I/O 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at

5 (21) P2.3

4.19 MHz for buzzer sound
TCL0 I/O External clock input for timer/counter 0 20 (38) P3.0
TCL1 I/O External clock input for timer/counter 1 19 (37) P3.1
KS0–KS3

I/O Quasi-interrupt inputs with falling edge detection 37–34

P6.0–P6.3

(11–8)

KS4–KS7

41–38

P7.0–P7.3

(15–12)

V

DD

– Power supply 21 (39)

–

V

SS

RESET

Xin, X

out

– Ground 42 (16)

I Reset signal 31 (5)

– Crystal, ceramic, or RC oscillator signal for system

clock (For external clock input, use Xin and input
Xin's reverse phase to X

out

)

33, 32

(7, 6)

TEST – Test signal input (must be connected to VSS) 22 (40)
NC – No connection (must be connected to VSS) (33, 34) –

NOTE: Parentheses indicate pin number for 44 QFP package.

–
–
–

–

1-11

PRODUCT OVERVIEW S3C7044/C7048/P7048

Table 1-2. Overview of S3C7044/C7048 Pin Data

Pin Names Share Pins I/O Type Reset Value Circuit Type

P0.0–P0.3

SCK, SO, SI, BTCO

I/O Input D-1

P1.0–P1.2 INT0, INT1, INT2 I Input A-3
P1.3 INT4 I Input B-4
P2.0–P2.3 TCLO0, TCLO1, CLO,

I/O Input D

BUZ
P3.0–P3.1 TCL0, TCL1 I/O Input D-1
P3.2–P3.3 – I/O Input D
P4.0–P4.3

– I/O

(NOTE)

E-2

P5.0–P5.3
P6.0–P6.3

P7.0–P7.3

KS0–KS3

KS4–KS7

I/O Input D-1

P8.0–P8.3 – I/O Input D-2
Xin, X

RESET

out

– – – –
– I – B

TEST – I – –
NC – – – –
VDD, V

SS

– – – –

NOTE: When pull-up resistors are provided, port 4 and port 5 pins are reset to high level; with no pull-ups, they are reset to

high impedance.

1-12

S3C7044/C7048/P7048 PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

V

DD

V

DD

IN

Figure 1-4. Pin Circuit Type A

P-CHANNEL

V

DD

PULL-UP
RESISTOR

P-CHANNEL

N-CHANNEL

PULL-UP RESISTOR
ENABLE

PULL-UP
RESISTOR

IN

SCHMITT TRIGGER

Figure 1-6. Pin Circuit Type B

IN

IN

SCHMITT TRIGGER

Figure 1-5. Pin Circuit Type A-3

SCHMITT TRIGGER

Figure 1-7. Pin Circuit Type B-4

1-13

PRODUCT OVERVIEW S3C7044/C7048/P7048

V

DD

DATA

OUTPUT
DISABLE

Figure 1-8. Pin Circuit Type C

V

DD

V

DD

P-CHANNEL

N-CHANNEL

PULL-UP
RESISTOR

OUT

PULL-UP
RESISTOR

RESISTOR

ENABLE

DATA

OUTPUT

DISABLE

CIRCUIT

TYPE C

SCHMITT TRIGGER

P-CHANNEL

Figure 1-10. Pin Circuit Type D-1

DATA

OUTPUT

DISABLE

CIRCUIT

TYPE C

I/O

I/O

RESISTOR

ENABLE

DATA

OUTPUT

DISABLE

CIRCUIT

TYPE C

CIRCUIT TYPE A

Figure 1-9. Pin Circuit Type D

P-CHANNEL

I/O

CIRCUIT TYPE A

RESISTOR

ENABLE

N-CHANNEL

PULL-DOWN
RESISTOR

Figure 1-11. Pin Circuit Type D-2

1-14

S3C7044/C7048/P7048 PRODUCT OVERVIEW

VDD

I/O

DATA

OUTPUT

DISABLE

N-CHANNEL

Figure 1-12. Pin Circuit Type E-2

1-15

S3C7044/C7048/P7048 ELECTRICAL DATA

13 ELECTRICAL DATA

In this section, information on S3C7044/C7048 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:

Standard Electrical Characteristics

— Absolute maximum ratings
— D.C. electrical characteristics
— System clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range

Miscellaneous Timing Waveforms

— A.C timing measurement point
— Clock timing measurement at X

— TCL timing
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing

Stop Mode Characteristics and Timing Waveforms

— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request

IN

and X

OUT

13-1

ELECTRICAL DATA S3C7044/C7048/P7048

Table 13-1. Absolute Maximum Ratings

(T

= 25 °C)

A

Parameter Symbol Conditions Rating Units

Supply Voltage V
Input Voltage V
Output Voltage V
Output Current High I

DD

I1

OH

All I/O ports except 4 and 5 – 0.3 to V

O

One I/O port active – 15 mA

– – 0.3 to + 6.5 V

+ 0.3 V

DD

– – 0.3 to VDD + 0.3 V

All I/O ports active – 30

Output Current Low I

OL

One I/O port active + 30 (Peak value) mA

(note)

+ 15

All I/O ports, total + 100 (Peak value)

(note)

+ 60

Operating Temperature T
Storage Temperature T

stg

A

– – 40 to + 85
– – 65 to + 150

°

C

°

C

NOTE: The values for output current low ( IOL ) are calculated as peak value × Duty .

13-2

S3C7044/C7048/P7048 ELECTRICAL DATA

Table 13-2. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Input High
Voltage

V

IH1

V

IH2

V

IH3

All input pins except those
specified below for V

IH2

– V

IH4

Ports 0, 1, 3, 6, 7, and RESET
Ports 4 and 5 with pull-up

0.7 V

0.8 V

0.7 V

DD

DD
DD

– V

DD

V

resistors assigned
Ports 4 and 5 are open-drain

Input Low
Voltage

Output High
Voltage

Output Low
Voltage

V

V

V

V

V
V

IH4

IL1

IL2
IL3

OH

OL1

XIN and X

OUT

All input pins except those
specified below for V

IL2–VIL3

Ports 0, 1, 3, 6, 7, and RESET
Xin and X

out

IOH = – 1 mA
Ports except 1, 4, and 5

V

= 4.5 V to 5.5 V

DD

IOL = 15 mA, Ports 4, 5 only

V

– 0.1

DD

– – 0.3 V

0.2 V

DD

DD

0.1

V

– 1.0 – – V

DD

– – 2 V

V

Input High
Leakage
Current

Input Low
Leakage
Current

V

I

LIH1

I

LIH2

I

LIL1

I

LIL2

OL2

VDD = 1.8 to 5.5 V
IOL = 1.6mA

VDD = 4.5 V to 5.5 V
IOL= 4 mA
All output ports except ports 4,5

VDD = 1.8 to 5.5 V
IOL = 1.6mA

VI = V

DD

All input pins except those
specified below for I

VI = V

DD

XIN and X
V

= 0

I

OUT

V

LIH2

All input pins except below and

RESET

V

= 0 V

I

XIN and X

OUT

only

0.4

2

0.4

– – 3 µA

20

– – – 3 µA

– 20

13-3

ELECTRICAL DATA S3C7044/C7048/P7048

Table 13-2. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Output High

I

LOH

V

= V

O

All output pins – – 3 µA

DD,

Leakage Current
Output Low

I

LOL

V

= 0 V, All output pins – – – 3 µA

O

Leakage Current
Pull-Up

Resistor

R

L1

VI = 0 V; V

DD

= 5 V

25 47 100

kΩ

Ports 0, 1 (not P1.3), 2, 3, 6, 7
V

= 3 V 50 95 200

DD

R

L2

V

= V

O

– 2V; V

DD

DD

= 5V

15 47 70

Ports 4 and 5 only
V

= 3 V 10 45 60

DD

Pull-Down
Resistor

Supply
Current

(1)

R

R

I

DD1

V

L3

L4

= 5 V; VI = 0V; RESET

DD

V

= 3 V 200 450 800

DD

V

= 5 V; VI = VDD; Port 8 25 47 100

DD

V

= 3 V 50 95 200

DD

Run mode; V

= 5 V ± 10% 6.0 MHz – 3.9 8.0 mA

DD

Crystal oscillator; C1 = C2 = 22 pF 4.19 MHz 2.9 5.5

100 220 400

kΩ

V

= 3 V ± 10% 6.0 MHz 1.8 4.0

DD

I

DD2

Run mode; V

DD

crystal oscillator, C1 = C2 = 22 pF 4.19 MHz 1.2 1.8
V

= 3 V ± 10% 6.0 MHz 0.5 1.5

DD

I

DD3

Stop mode; VDD = 5 V ± 10%
Stop mode; VDD = 3 V ± 10%

NOTES

1. D.C. electrical values for Supply Current (I

2. The supply current assumes a CPU clock of fx/4.

DD1

to I

4.19 MHz 1.3 3.0

= 5 V ± 10%

6.0 MHz – 1.3 2.5 mA

4.19 MHz 0.44 1.0
– 0.2 3 µA

0.1 2

) do not include current drawn through internal pull-up resistors.

DD3

13-4

S3C7044/C7048/P7048 ELECTRICAL DATA

Table 13-3. Main System Clock Oscillator Characteristics

(T

= – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)

A

Oscillator Clock

Configuration

Ceramic

Xin Xout

Oscillator

C1 C2

Crystal

Xin Xout

Oscillator

C1 C2

External

Xin Xout

Clock

Parameter Test Condition Min Typ Max Units

Oscillation frequency

Stabilization time

(2)

Oscillation frequency

Stabilization time

(2)

XIN input frequency

(1)

VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz

VDD = 1.8 V to 5.5 V 0.4 – 4.2
VDD = 3 V – – 4 ms

(1)

VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz

VDD = 1.8 V to 5.5 V 0.4 – 4.2
VDD = 3 V – – 10 ms

(1)

VDD = 2.7 V to 5.5 V 0.4 – 6.0 MHz

VDD = 1.8 V to 5.5 V 0.4 – 4.2

XIN input high and low

– 83.3 – 1250 ns

level width (tXH, tXL)

NOTES

1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.

13-5

ELECTRICAL DATA S3C7044/C7048/P7048

SS

Table 13-4. Input/Output Capacitance

(TA = 25 °C, V

= 0 V )

DD

Parameter Symbol Condition Min Typ Max Units

Input Capacitance C

IN

f = 1 MHz; Unmeasured

– – 15 pF

pins are returned to V

Output Capacitance C
I/O Capacitance C

OUT

IO

Table 13-5. A.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, V

A

= 1.8 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Units

Instruction Cycle

t

CY

V

= 2.7 V to 5.5 V 0.67 – 64 µs

DD

Time

VDD = 1.8 V to 5.5 V 0.95

TCL0, TCL1 Input

f

TI0

f

,

VDD = 2.7 V to 5.5 V 0 – 1.5 MHz

TI1

Frequency

VDD = 1.8 V to 5.5V 1

TCL0, TCL1 Input
High, Low Width

t

TIH0

t

TIH1

, t
, t

VDD = 2.7 V to 5.5 V 0.48 – – µs

TIL0
TIL1

VDD = 1.8 V to 5.5 V 1.8

SCK Cycle Time

SCK High, Low

Width

t

KCY

t

KH, tKL

V

= 2.7 V to 5.5 V

DD

External SCK source
Internal SCK source

V

= 1.8 V to 5.5 V

DD

External SCK source
Internal SCK source

V

= 2.7 V to 5.5 V

DD

External SCK source
Internal SCK source

V

= 1.8 V to 5.5 V

DD

External SCK source
Internal SCK source

800 – – µs

670

3200

3800

335 – – µs

t

/

KCY

2 – 50

1600

t

/

KCY

2 – 150

13-6

S3C7044/C7048/P7048 ELECTRICAL DATA

Table 13-5. A.C. Electrical Characteristics (Continued)

(TA = – 40 °C to + 85 °C, V

= 1.8 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Units

SI Setup Time to
SCK High

t

SIK

VDD = 2.7 V to 5.5 V
External SCK source

Internal SCK source
VDD = 1.8 V to 5.5 V

100 – – ns

150
150

External SCK source

500
400 – – ns

400
600

SI Hold Time to
SCK High

t

KSI

Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source

Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source

500

– – 300 ns

250

1000

Output Delay for
SCK to SO

t

KSO

Internal SCK source

(1)

VDD = 2.7 V to 5.5 V
External SCK source

Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source

1000

Interrupt Input

t

INTH

, t

Internal SCK source
INT0

INTL

(2)

– –

High, Low Width

INT1, INT2, INT4, KS0 - KS7 10

RESET Input Low

t

RSL

Input 10 – –

Width

µs

µs

NOTES

1. R(1Kohm) and C(100pF) are the load resistance and load capacitance of the SO output line.

2. Minimum value for INT0 is based on a clock of 2t

or 128/fx as assigned by the IMOD0 register setting.

CY

13-7

ELECTRICAL DATA S3C7044/C7048/P7048

CPU CLOCK

1.5 MHz

1.05 kHz

15.625 kHz

Table 13-6. RAM Data Retention Supply Voltage in Stop Mode

Main Osc. Freq. ( Divided by 4 )

6 MHz

4.2 MHz

400 kHz

1 2 3 4 5 6 7

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)

Figure 13-1. Standard Operating Voltage Range

(TA = – 40 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Data retention supply voltage V
Data retention supply current I

Release signal set time t
Oscillator stabilization wait t

(1)

time

NOTES

1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.

2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.

DDDR

DDDR

SREL
WAIT

V

DDDR

Released by RESET
Released by interrupt –

– 1.5 – 5.5 V

= 1.5 V – 0.1 10

– 0 – –

–

217/fx

(2)

– ms
– ms

µA

µs

13-8

S3C7044/C7048/P7048 ELECTRICAL DATA

TIMING WAVEFORMS

INTERNAL RESET

OPERATION

V

DD

RESET

V

DD

STOP MODE

DATA RETENTION MODE

V

EXECUTION OF

STOP INSTRUCTION

DDDR

t

SREL

Figure 13-2. Stop Mode Release Timing When Initiated By RESETRESET

IDLE MODE

STOP MODE

DATA RETENTION MODE

IDLE MODE

t

WAIT

NORMAL
OPERATING
MODE

OPERATING
MODE

V

EXECUTION OF

DDDR

STOP INSTRUCTION

POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)

t

SREL

t

WAIT

Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request

13-9

ELECTRICAL DATA S3C7044/C7048/P7048

Timing Waveforms (continued)

Xin

0.8 V

0.2 V

DD

DD

MEASUREMENT

POINTS

0.8 V

0.2 V

DD

DD

Figure 13-4. A.C. Timing Measurement Points (Except for XIN)

1 / fx

t

XL

t

XH

V

DD

0.1 V

– 0.1 V

TCL

Figure 13-5. Clock Timing Measurement at X

1 / f

TI

t

TIL

t

TIH

Figure 13-6. TCL Timing

IN

V

0.8

DD

0.2 V

DD

13-10

S3C7044/C7048/P7048 ELECTRICAL DATA

t

RSL

RESET

0.2 V

DD

Figure 13-7. Input Timing for RESETRESET Signal

INT0, 1, 2, 4
KS0 to KS7

Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts

t

INTL

0.8 V

0.2 V

DD
DD

t

INTH

13-11

ELECTRICAL DATA S3C7044/C7048/P7048

tKCY

tKL tKH

SCK

0.8 VDD

0.2 VDD

tSIK tKSI

SO

SI

INPUT DATA

0.8 VDD

0.2 VDD

tKSO

OUTPUT DATA

Figure 13-9. Serial Data Transfer Timing

13-12

S3C7044/C7048/P7048 ECHANICAL DATA

14 MECHANICAL DATA

This section contains the following information about the device package:
— 42-SDIP-600 package dimensions in millimeters

— 44-QFP-1010B package dimensions in millimeters

00 ± 0.2

14.

(1.77)

0.50 ± 0.1

NOTE

#42 #22

42-SDIP-600

#1 #21

39.10 ± 0.2

1.00 ± 0.1

: Dimensions are in millimeters.

1.778

0 ~ 15 °

15.24

5

1

0

.

.

0

0

+

–

5

2

.

0

0.51 MIN 3.50 ± 0.2

3.30 ± 0.3 5.08 MAX

Figure 14-1. 42-SDIP-600 Package Dimensions

14-1

MECHANICAL DATA S3C7044/C7048/P7048

0

.

0~8°

1

5

+

0

.1

–

0.

0

5

0.1 MAX

13.20 ± 0.30

10.00 ± 0.2

± 0.30

44-QFP-1010B

10.00 ± 0.2

13.20

#44

0.80 ± 0.20

#1

1.00

0.35

+ 0.10

- 0.05

0.80

0.0 MIN

2.05 ± 0.1

14-2

NOTE

: Dimensions are in millimeters.

Figure 14-2. 44-QFP-1010B Package Dimensions

2.30 MAX

S3C7044/C7048/P7048 S3P7048 OTP

15 S3P7048 OTP

OVERVIEW

The S3P7048 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the

S3C7044/C7048 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.

The S3P7048 is fully compatible with the S3C7044/C7048, both in function and in pin configuration. Because of
its simple programming requirements, the S3P7048 is ideal for use as an evaluation chip for the
S3C7044/C7048.

P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0

P2.3/BUZ

P2.2/CLO
P2.1/TCLO1
P2.0/TCLO0

P0.3/BTCO

P0.2/SI

P0.1/SO

P0.0/SCK

P8.3
P8.2
P8.1
P8.0
P3.3
P3.2

SDAT/P3.1/TCL1
SCLK/P3.0/TCL0

VDD/VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

NOTE: The bolds indicate an OTP pin name.

(42-SDIP-600)

S3P7048

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

Figure 15-1. S3P7048 Pin Assignments (42-SDIP Package)

VSS/VSS
P7.0/KS4
P7.1/KS5
P7.2/KS6
P7.3/KS7
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
XIN
XOUT

RESET/RESETRESET

P5.0
P5.1
P5.2
P5.3
P4.0
P4.1
P4.2
P4.3
TEST/TEST

15-1

S3P7048 OTP S3C7044/C7048/P7048

SDAT/P3.1/TCL1

SCLK/P3.0/TCL0

TEST/TEST

VDD/VDD

P3.3

P3.2

NC

33
32
31
30
29
28
27
26
25
24
23

NC
P8.0
P8.1
P8.2
P8.3
P0.0/SCK
P0.1/SO
P0.2/SI
P0.3/BTCO
P2.0/TCLO0
P2.1/TCLO1

P5.3
P5.2
P5.1
P5.0

RESETRESET/RESET

XOUT

XIN
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0

P4.3

P4.2

P4.1

P4.0

4443424140393837363534

1
2
3
4
5
6
7
8
9
10
11

S3P7048

(44-QFP-1010B)

1213141516171819202122

P7.3/KS7

P7.2/KS6

NOTE: The bolds indicate an OTP pin name.

VSS/VSS

P7.1/KS5

P7.0/KS4

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

P2.3/BUZ

P2.2/CLO

Figure 15-2. S3P7048 Pin Assignments (44-QFP Package)

15-2

S3C7044/C7048/P7048 S3P7048 OTP

Table 15-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P3.1 SDAT 19 (37) I/O Serial data pin. Output port when reading and

input port when writing. Can be assigned as a
Input/push-pull output port.

P3.0 SCLK 20 (38) I/O Serial clock pin. Input only pin.

TEST

VPP(TEST)

22 (40) I Power supply pin for EPROM cell writing

(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in writing
mode and when 5 V is applied, OTP is in reading
mode. (Option)

RESET RESET

VDD/V

SS

VDD/V

SS

31 (5) I Chip initialization

21/42(39/16) I

Logic power supply pin. VDD should be tied to
+5 V during programming.

NOTE: ( ) means the 44-QFP OTP pin number.

Table 15-2. Comparison of S3P7048 and S3C7044/C7048 Features

Characteristic S3P7048 S3C7044/C7048

Program Memory 8 K-byte EPROM 4 K-byte mask ROM: S3C7044

8 K-byte mask ROM: S3C7048

Operating Voltage (VDD)
OTP Programming Mode

2.0 V to 5.5 V 1.8 V to 5.5V
VDD = 5 V, VPP(TEST)=12.5V

Pin Configuration 42SDIP, 44QFP 42SDIP, 44QFP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP(TEST) pin of the S3P7048, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 15-3 below.

Table 15-3. Operating Mode Selection Criteria

V

DD

Vpp

(TEST)

REG/

MEM

Address
(A15-A0)

R/W Mode

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

15-3

S3P7048 OTP S3C7044/C7048/P7048

Table 15-4. D.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Input High
Voltage

V

IH1

V

IH2

V

IH3

All input pins except those
specified below for V

IH2

– V

IH4

Ports 0, 1, 3, 6, 7, and RESET
Ports 4 and 5 with pull-up

0.7 V

0.8 V

0.7 V

DD

DD
DD

–

V

DD

V

resistors assigned
Ports 4 and 5 are open-drain

Input Low
Voltage

Output High
Voltage

Output Low
Voltage

V

IH4

V

IL1

V

IL2

V

IL3

V

OH

V

OL1

XIN and X

OUT

All input pins except those
specified below for V

IL2–VIL3

Ports 0, 1, 3, 6, 7, and RESET
XIN and X

OUT

IOH = – 1 mA
Ports except 1, 4, and 5

V

= 4.5 V to 5.5 V

DD

IOL = 15 mA, Ports 4, 5 only

V

– 0.1

DD

– –

0.3 V

0.2 V

DD

DD

0.1

V

DD

– 1.0

– – V

– – 2 V

V

Input High
Leakage
Current

Input Low
Leakage
Current

V

I

I

I

I

OL2

LIH1

LIH2

LIL1

LIL2

VDD = 2.0 to 5.5 V
IOL = 1.6mA

VDD = 4.5 V to 5.5 V
IOL= 4 mA
All output ports except ports 4,5

VDD = 2.0 to 5.5 V
IOL = 1.6mA

VI = V

DD

All input pins except those
specified below for I

VI = V

DD

XIN and X
V

= 0

I

OUT

V

LIH2

All input pins except below and

RESET

V

= 0 V

I

XIN and X

OUT

only

0.4

2

0.4

– – 3 µA

20

– – – 3 µA

– 20

15-4

S3C7044/C7048/P7048 S3P7048 OTP

Table 15-4. D.C. Electrical Characteristics (Continued)

(T

= – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Units

Output High

I

LOH

V

= V

O

All output pins

DD,

– – 3 µA

Leakage Current
Output Low

I

LOL

V

= 0 V, All output pins

O

– – – 3 µA

Leakage Current
Pull-Up

Resistor

R

R

L1

VI = 0 V; V

DD

= 5 V

Ports 0, 1 (not P1.3), 2, 3, 6, 7

V

= 3 V

DD

V

= V

L2

O

– 2V; V

DD

DD

= 5V

25 47 100

50 95 200
15 47 70

kΩ

Ports 4 and 5 only

V

Pull-Down
Resistor

Supply
Current

(1)

R

R

I

DD1

= 3 V

DD

V

L3

L4

= 5 V; VI = 0V; RESET

DD

V

= 3 V

DD

V

= 5 V; VI = VDD; Port 8

DD

V

= 3 V

DD

Run mode; V

= 5 V ± 10%

DD

6.0 MHz – 3.9 8.0 mA

Crystal oscillator; C1 = C2 = 22 pF 4.19 MHz 2.9 5.5

10 45 60

100 220 400
200 450 800

25 47 100
50 95 200

kΩ

V

= 3 V ± 10%

DD

I

DD2

Run mode; V

DD

crystal oscillator, C1 = C2 = 22 pF 4.19 MHz 1.2 1.8

V

= 3 V ± 10%

DD

I

DD3

Stop mode; VDD = 5 V ± 10%

Stop mode; VDD = 3 V ± 10%

NOTES

1. D.C. electrical values for Supply Current (I

2. The supply current assumes a CPU clock of fx/4.

DD1

to I

6.0 MHz 1.8 4.0

4.19 MHz 1.3 3.0

= 5 V ± 10%

6.0 MHz – 1.3 2.5 mA

6.0 MHz 0.5 1.5

4.19 MHz 0.44 1.0
– 0.2 3 µA

0.1 2

) do not include current drawn through internal pull-up resistors.

DD3

15-5

S3P7048 OTP S3C7044/C7048/P7048

Table 15-5. A.C. Electrical Characteristics

(T

= – 40 °C to + 85 °C, V

A

= 2.0 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Units

Instruction Cycle

t

CY

V

= 2.7 V to 5.5 V

DD

0.67 – 64 µs

Time

TCL0, TCL1 Input

f

TI0

VDD = 2.0 V to 5.5 V

f

,

VDD = 2.7 V to 5.5 V

TI1

0.95
0 – 1.5 MHz

Frequency

TCL0, TCL1 Input
High, Low Width

t

TIH0

t

TIH1

, t
, t

VDD = 2.0 V to 5.5V
VDD = 2.7 V to 5.5 V

TIL0
TIL1

VDD = 2.0 V to 5.5 V

0.48 – – µs

1.8

1

SCK Cycle Time

SCK High, Low

Width

t

KCY

t

KH, tKL

V

= 2.7 V to 5.5 V

DD

External SCK source
Internal SCK source

V

= 2.0 V to 5.5 V

DD

External SCK source
Internal SCK source

V

= 2.7 V to 5.5 V

DD

External SCK source
Internal SCK source

V

= 2.0 V to 5.5 V

DD

External SCK source
Internal SCK source

800 – – µs

670

3200

3800

335 – – µs

t

/

KCY

2 – 50

1600

t

/

KCY

2 – 150

15-6

S3C7044/C7048/P7048 S3P7048 OTP

Table 15-5. A.C. Electrical Characteristics (Continued)

(TA = – 40 °C to + 85 °C, V

= 2.0 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Units

SI Setup Time to
SCK High

t

SIK

VDD = 2.7 V to 5.5 V
External SCK source

Internal SCK source
VDD = 2.0 V to 5.5 V

100 – – ns

150
150

External SCK source

500
400 – – ns

400
600

SI Hold Time to
SCK High

t

KSI

Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source

Internal SCK source
VDD = 2.0 V to 5.5 V
External SCK source

500

– – 300 ns

250

1000

Output Delay for
SCK to SO

t

KSO

Internal SCK source

(1)

VDD = 2.7 V to 5.5 V
External SCK source

Internal SCK source
VDD = 2.0 V to 5.5 V
External SCK source

1000

Interrupt Input

t

INTH

, t

Internal SCK source
INT0

INTL

(2)

– –

High, Low Width

INT1, INT2, INT4, KS0 - KS7 10

RESET Input Low

t

RSL

Input 10 – –

Width

µs

µs

NOTES

1. R (1KΩ) and C (100pF) are the load resistance and load capacitance of the SO output line.

2. Minimum value for INT0 is based on a clock of 2t

or 128/fx as assigned by the IMOD0 register setting.

CY

15-7

S3P7048 OTP S3C7044/C7048/P7048

CPU CLOCK

1.5 MHz

1.05 kHz

15.625 kHz

Main Osc. Freq. ( Divided by 4 )

6 MHz

4.2 MHz

400 kHz

1 2 3 4 5 6 7

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)

Figure 15-3. Standard Operating Voltage Range

15-8

S3C7044/C7048/P7048 S3P7048 OTP

START

Address= First Location

VDD=5V, VPP=12.5V

x = 0

Program One 1ms Pulse

Increment X

FAIL

Device Failed

Verify Byte

YES

x = 10

NO

FAIL

NO

FAIL

Verify 1 Byte

Last Address

V

= VPP= 5 V

DD

Compare All Byte

PASS

Device Passed

Figure 15-4. OTP Programming Algorithm

Increment Address

15-9