Page 1
S3C7031/7032 PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
OVERVIEW
The S3C7031/7032 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core.
With comparator inputs, high-current LED direct-drive pins, serial I/O interface, and a versatile 8-bit
timer/counter, the S3C7031/7032 offers an excellent design solution for a wide range of applications such as
mouse controllers, subsystem controllers, and toys.
Up to 15 pins of the 20-pin DIP or 20-pin SOP package can be dedicated to I/O. Pull-up resistors are assignable
to all of the pins by software. Four vectored interrupts provide fast response to internal and external events.
In addition, the S3C7031/7032's advanced CMOS technology provides for very low power consumption and a
wide operating voltage range.
DEVELOPMENT SUPPORT
The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based
development environment for KS57-series microcontrollers that is powerful, reliable, and portable. In addition to
its easy to use window-oriented program development structure, the SMDS toolset includes versatile debugging,
trace, instruction timing, and performance measurement applications.
The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and
accepts assembly language sources in a variety of microprocessor formats.
SAMA generates industry-standard object files that also contain program control data for SMDS compatibility.
1-1
Page 2
PRODUCT OVERVIEW S3C7031/7032
FEATURES
Memory
— 1024 × 8-bit program memory (S3C7031)
(ROM)
— 2048 × 8-bit program memory (S3C7032)
(ROM)
— 128 × 4-bit data memory (S3C7031) (RAM)
— 256 × 4-bit data memory (S3C7032) (RAM)
I/O Pins
— Up to 15 pins for 20-DIP and 20-SOP package
Comparator Inputs
— 4-channel mode
Internal reference: 4-bit resolution
— 3-channel mode
External reference
8-Bit Basic Timer
— Programmable interval timer
8-Bit Serial I/O Interface
— 8-bit transmit/receive mode
— 8-bit receive-only mode
— LSB-first or MSB-first transmission selectable
— Internal or external clock source
Interrupts
— One external interrupt vector
— Three internal interrupt vectors
— Two quasi-interrupts
Memory-Mapped I/O Structure
Two Power-Down Modes
— Idle mode: Only the CPU clock stops
— Stop mode: Main system clock stops
On-Chip Crystal, Ceramic, Or RC Oscillator
— Crystal/ceramic: 4.19 MHz (typical)
— RC: 1 MHz (typical)
— CPU clock divider circuit (by 4, 8, or 64)
8-Bit Timer/Counter
— Programmable interval timer
— External event counter function
— Timer clock output to TIO pin
Watch Timer
— Time interval generation: 0.5 s, 3.9 ms at
4.19 MHz
— Four frequency outputs to BUZ pin
Bit Sequential Carrier
— 16-bit serial data transfer in arbitrary format
Frequency Outputs
— Eight frequency outputs to the CLO pin
Instruction Execution Times
— 0.95, 1.91, 15.3 µs at 4.19 MHz (5 V),
4 µs at 1 MHz (2.7 V)
Operating Temperature:
— – 40°C to 85°C
Operating Voltage Range:
— 2.7 V to 6.0 V
Package Type:
— 20-DIP, 20-SOP
1-2
Page 3
S3C7031/7032 PRODUCT OVERVIEW
BLOCK DIAGRAM
X
RESET
X
OUT
IN
P2.0 - P2.3
P3.0/SCK
P3.1/SO
P3.2/SI
P3.3/BUZ
Basic
Timer
Watch
Timer
I/O Port 2
I/O Port 3
Serial I/O Port
Interrupt
Control
Block
Internal
Interrupts
Instruction Decoder
Arithmetic
Logic Unit
Data
Memory
NOTES:
1. Program Memory is 1-KByte (S3C7031) and 2-KByte (S3C7032).
2. Data Memory is 128 x 4bit (S3C7031) and 256 x 4bit (S3C7032).
(2)
Clock
and
Stack
Pointer
Program
Counter
Program
Status Word
Flags
Program
Memory
(1)
I/O Port 0
8-Bit
Timer/
Counter
Comparator
I/O Port 1
P0.0/CLO
P0.1/TIO
P0.2/INT1
P0.0/KS0/CIN0
P0.1/KS1/CIN1
P0.2/KS2/CIN2
P0.3/KS3/CIN3
Figure 1-1. S3C7031/7032 Block Diagram
1-3
Page 4
PRODUCT OVERVIEW S3C7031/7032
PIN ASSIGNMENTS
P0.0/CLO
P0.1/TIO
P0.2/INT1
P0.0/KS0/CIN0
P0.1/KS1/CIN1
P0.2/KS2/CIN2
P0.3/KS3/CIN3
XOUT
XIN
VSS
NOTE: Pin assignments are identical for the 20-pin DIP and SOP package.
1
2
3
4
5
6
7
8
9
10
KS57C7031/
KS57C7032
(Top view)
20
19
18
17
16
15
14
13
12
11
VDD
P3.3/BUZ
P3.2/SI
P3.1/SO
P3.0/SCK
P2.3
P2.2
P2.1
P2.0
RESET
Figure 1-2. S3C7031/7032 Pin Assignment Diagram (20-pin DIP/SOP Package)
PIN DESCRIPTIONS
Table 1-1. S3C7031/7032 Pin Descriptions
Pin Name Pin Type Description Number Share Pin
P0.0
P0.1
P0.2
P1.0
P1.1
P1.2
P1.3
1-4
I/O 3-bit I/O port.
1-bit or 3-bit read/write and test is possible.
Pull-up resistors are individually assignable to input
pins by software and are automatically disabled for
output pins.
Pins are individually configurable as input or output.
I/O Same as port 0 except that port 1 is a 4-bit I/O port. 4
1
2
3
KS0/CIN0
5
6
7
KS1/CIN1
KS2/CIN2
KS3/CIN3
CLO
TIO
INT1
Page 5
S3C7031/7032 PRODUCT OVERVIEW
Table 1-1. S3C7031/7032 Pin Descriptions (Continued)
Pin Name Pin Type Description Number Share Pin
P2.0-P2.3
P3.0
P3.1
P3.2
P3.3
I/O 4-bit I/O port. 1-bit, 4-bit or 8-bit read/write and test is
possible. Pins are individually configurable as input
or output.
Pull-up resistors are individually assignable to input
pins by software and are automatically disabled for
12-15
16
17
18
19
–-
SCK
SO
SI
BUZ
output pins. Ports are software configurable as
n-channel open-drain outputs or push-pull output by
software.
Ports 2 and 3 can be paired to enable 8-bit data
transfer.
CLO I/O Eight frequency outputs 1 P0.0
TIO I/O External clock input or timer clock output 2 P0.1
INT1 I/O External interrupts with rising or falling edge
3 P0.2
detection
KS0-KS3 I/O Quasi-interrupts with falling edge detection 4-7 P1.0-P1.3
CIN0-CIN3 I/O 4-channel comparator input.
4-7 P1.0-P1.3
CIN0-CIN2: comparator input only.
CIN3: comparator input or external reference input
SCK
I/O Serial interface clock signal 16 P3.0
SO I/O Serial data output 17 P3.1
SI I/O Serial data input 18 P3.2
BUZ I/O 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at
19 P3.3
4.19 MHz for buzzer sound
XIN, X
RESET
V
DD
V
SS
OUT
–- Crystal, ceramic, or RC signal for system clock 9, 8 –-
I Reset signal 11 ––- Power supply 20 ––- Ground 10 –-
Table 1-2. Overview of S3C7031/7032 Pin Data
Pin Numbers Pin Names Share Pins I/O Type Reset Value Circuit Type
1-3 P0.0-P0.2 CLO, TIO, INT1 I/O Input 2
4-7 P1.0-P1.3 KS0/CIN0-KS3/CIN3 I/O Input 4
12-5 P2.0-P2.3 – I/O Input 3
16-19 P3.0-P3.3
11
20, 10
9, 8
RESET
VDD, V
XIN, X
SS
OUT
SCK, SO, SI, BUZ
–- I –- 1
–- –- –- ––- –- –- –-
I/O Input 3
1-5
Page 6
PRODUCT OVERVIEW S3C7031/7032
PIN CIRCUIT DIAGRAMS
In
Schmitt Trigger
Figure 1-3. Pin Circuit Type 1
VDD
Data
Output DIsable
Pull-up
Registor
Pull-up Enable
VDD
VSS
Schmit Trigger
Figure 1-4. Pin Circuit Type 2
Typical 50 KΩ
(VDD = 5V)
I/O
1-6
Page 7
S3C7031/7032 PRODUCT OVERVIEW
VDD
Data
Open-drain
Output Disable
Pull-up
Registor
Pull-up Enable
VDD
Schmit Trigger
Figure 1-5. Pin Circuit Type 3
Typical 50 KΩ
(VDD =5V)
I/O
VSS
1-7
Page 8
PRODUCT OVERVIEW S3C7031/7032
VDD
Output Disable
(Digital)
Data
Open-drain
In
Intk
(Quasi)
In
Pull-up Enable
Schmit Trigger
REF
(P1.3 Only)
+
Pull-up
Registor
VDD
VSS
Typical 50 KΩ
(VDD =5V)
P-CH
I/O
(Analog) Comparator
Digital or Analog
Selectable by Software
Figure 1-6. Pin Circuit Type 4
REF
1-8
Page 9
S3C7031/7032 ELECTRICAL DATA
14 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7031/7032 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Oscillators characteristics
— I/O capacitance
— Comparator electrical characteristics
— A.C. electrical characteristics
— Operating voltage range
Oscillation Characteristics
— System clock oscillator frequencies and stabilization time
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
14-1
Page 10
ELECTRICAL DATA S3C7031/7032
Miscellaneous Timing Waveforms
— Clock timing measurement at X
IN
— TIO timing
— Input timing for RESET
— Input timing for external interrupts and quasi-interrupts
— Serial data transfer timing
Characteristic Curves
— IDD vs Frequency
— IDD vs V
DD
— IOL vs VOL (P0.0)
— IOL vs VOL (P1.1)
— IOL vs VOL (P2.0)
— IOH vs VOH (P0.0)
— IOH vs VOH (P1.1)
14-2
Page 11
S3C7031/7032 ELECTRICAL DATA
Table 14-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter Symbol Conditions Rating Units
Supply Voltage
Input Voltage
Output Voltage
Output Current High
V
DD
V
I
V
O
I
OH
All I/O ports
One I/O port active - 5 mA
– - 0.3 to + 7.0 V
- 0.3 to V
–
- 0.3 to VDD + 0.3
DD
+ 0.3
V
V
All I/O ports active - 15
Output Current Low
I
OL
One I/O port active 25 mA
All I/O port, total 100
Operating Temperature
Storage Temperature
T
A
T
stg
– - 40 to + 85
– - 65 to + 150
°
C
°
C
Table 14-2. D.C. Electrical Characteristics
(T
= - 40 °C to + 85 °C, VDD = 2.7 V to 6.0 V)
A
Parameter Symbol Conditions Min Typ Max Units
Input High
VIH1
Ports 0, 1, 2, 3, RESET
0.7 V
DD
–
V
DD
Voltage
Input Low
VIH2 XIN, X
VIL1
Ports 0, 1, 2, 3, RESET
OUT
V
0.5
-
DD
– –
–
V
0.3 V
DD
DD
Voltage
Output High
Voltage
VIL2 XIN, X
OUT
VOH1 VDD = 4.5 V to 6.0 V
IOH = - 3 mA
V
DD
1.0 V
-
DD
-
0.4
0.4
– V
Ports 0, 1, 2, 3 except P0.0
VDD = 4.5 V to 6.0 V
V
DD
2.0 V
-
DD
- 0.9
–
IOH = - 6 mA
Ports 0, 1, 2, 3 except P0.0
VOH2 VDD = 4.5 V to 6.0 V
V
DD
-
2.0
– –
IOH = - 10 mA
P0.0
Output Low
Voltage
VOL1 V
= 4.5 V to 6.0 V
DD
IOL = 25 mA
– 1.4 2.0 V
Ports 0, 1, 2, 3 except P0.0
VOL2 V
= 4.5 V to 6.0 V
DD
– 1.6 2.0 V
IOL = 50 mA
P0.0
V
V
14-3
Page 12
ELECTRICAL DATA S3C7031/7032
Table 14-2. D.C. Electrical Characteristics (Continued)
(T
= - 40 °C to + 85 °C, VDD = 2.7 V to 6.0 V)
A
Parameter Symbol Conditions Min Typ Max Units
I
Input High
Leakage
Current
Input Low
Leakage
Current
Output High
Leakage
1 VIN = V
LIH
I
2 VIN = V
LIH
I
1 V
LIL
I
2 V
LIL
I
LOH
DD
All input pins except I
DD
XIN, X
OUT
= 0 V
IN
All input pins except I
= 0 V
IN
XIN, X
OUT
V
= V
O
DD
All output pins
LIH
LIL
– – 3
µA
2
15 20
– – - 3
µA
2
-15 - 20
– – 3
µA
Current
Output Low
Leakage
I
LOL
V
= 0 V
O
All output pins
– – - 3
µA
Current
Pull- Up
Resistor
R
V
L
Ports 0, 1, 2, 3
V
= 0 V; V
IN
= 0 V; V
IN
= 5 V - 10 %
DD
= 3 V - 10 %
DD
15 50 80
30 100 200
KΩ
Ports 0, 1, 2, 3
Supply
Current
(2)
IDD1
V
= 5 V ± 10 %
DD
4.19 MHz crystal oscillator
(2)
– 1.7 8.0 mA
C1 = C2 = 22 pF
V
= 3 V ± 10 %
DD
(3)
0.6 1.2
4.19 MHz crystal oscillator
C1 = C2 = 22 pF
IDD2 Idle mode; VDD = 5 V ± 10 %
– 0.5 1.8 mA
4.19 MHz crystal oscillator
C1 = C2 = 22 pF
Idle mode; VDD = 3 V ± 10 %
0.2 1.0
4.19 MHz crystal oscillator
C1 = C2 = 22 pF
IDD3
Stop mode
0.2 5
µA
VDD = 5 V - 10 %
Stop mode
0.1 3
VDD = 3 V - 10 %
NOTES:
1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up resistors.
2. For high-speed controller operation, set the PCON register to 0011B.
3. For low-speed controller operation, set the PCON register to 0000B.
14-4
Page 13
S3C7031/7032 ELECTRICAL DATA
Table 14-3. Oscillators Characteristics
(T
= - 40 °C to + 85 °C, VDD = 5 V)
A
Oscillator Clock
Configuration
Ceramic
Oscillator
XIN XOUT
C1
Crystal
Oscillator
XIN XOUT
C1
External
Clock
XIN XOUT
Oscillation frequency
C2
Stabilization time
Oscillation frequency
C2
Stabilization time
X
input frequency
IN
Parameter Test Condition Min Typ Max Units
(2)
(1)
After VDD reaches
– 0.4 – 4.5 MHz
– – 4 ms
the minimum level
of its variable range
(2)
(1)
VDD = 2.7 V to 4.5 V
VDD = 4.5 V to 6.0 V
(1)
– 0.4 4.19 4.5 MHz
– – 30 ms
– – 10
– 0.4 – 4.5 MHz
XIN input high and low
– 111 – 1250 ns
level width (tXH, tXL)
RC
Oscillator
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
XIN XOUT
R
Frequency
VDD = 5 V
VDD = 3 V
0.6 1 2.3 MHz
0.4 0.8 1.5
14-5
Page 14
ELECTRICAL DATA S3C7031/7032
Table 14-4. Input/Output Capacitance
(TA = 25 °C, V
DD
= 0 V )
Parameter Symbol Condition Min Typ Max Units
C
C
OUT
IN
f = 1 MHz; Unmeasured pins
are returned to V
SS
– – 15 pF
– – 15 pF
Input
Capacitance
Output
Capacitance
I/O Capacitance
C
IO
– – 15 pF
Table 14-5. Comparator Electrical Characteristics
(T
= - 40 °C to + 85 °C, VDD = 4.0 V to 6.0 V)
A
Parameter Symbol Condition Min Typ Max Units
Input Voltage Range – – 0 –
Reference Voltage
V
REF
– 0 –
V
DD
V
DD
Range
V
Input
Voltage
Internal
Reference
CIN
1
– – – - 150 mV
Accuracy
V
External
CIN
2
– – – - 50
Reference
I
Input Leakage Current
CIN
I
,
REF
– - 3 – 3
V
V
µA
14-6
Page 15
S3C7031/7032 ELECTRICAL DATA
Table 14-6. A.C. Electrical Characteristics
(T
= - 40 °C to + 85 °C, V
A
= 2.7 V to 6.0 V)
DD
Parameter Symbol Conditions Min Typ Max Units
Instruction Cycle Time
t
CY
V
= 4.5 V to 6.0 V
DD
VDD = 2.7 V to 4.5 V
0.95 – 64 µs
3.8
TIO Input Frequency
TIO Input High, Low
Width
SCK Cycle Time
SCK High, Low Width
SI Setup Time to
SCK High
SI Hold Time to SCK
High
Output Delay for SCK
to SO
f
t
TIH
t
KCY
tKH, t
t
SIK
t
KSI
t
KSO
TI
, t
VDD = 4.5 V to 6.0 V
0 – 1 MHz
VDD = 2.7 V to 4.5 V
VDD = 4.5 V to 6.0 V
TIL
VDD = 2.7 V to 4.5 V
VDD = 4.5 V to 6.0 V; Input
VDD = 4.5 V to 6.0 V; Output
VDD = 2.7 V to 4.5 V; Input
VDD = 2.7 V to 4.5 V; Output
VDD = 4.5 V to 6.0 V; Input
KL
VDD = 4.5 V to 6.0 V; Output t
VDD = 2.7 V to 4.5 V; Input
VDD = 2.7 V to 4.5 V; Output
0.48 – – µs
1.8
800 – – ns
950
3200
3800
400 – – ns
/2-50
KCY
1600
t
/2-50
KCY
Input 100 – – ns
Output 150
Input 400 – – ns
Output 400
VDD = 4.5 V to 6.0 V; Input
– – 300 ns
VDD = 4.5 V to 6.0 V; Output
275 kHz
250
Interrupt Input
High, Low Width
RESET Input Low
Width
t
INTH
t
RSL
, t
V
= 2.7 V to 4.5 V; Input
DD
V
= 2.7 V to 4.5 V; Output
DD
INT1, KS0-KS3 10 – – µs
INTL
1000
1000
Input 10 – – µs
14-7
Page 16
ELECTRICAL DATA S3C7031/7032
CPU Clock
1.0475MHz
1.00MHz
750kHz
500kHz
250kHz
15.6kHz
1 2 3 4 5 6 7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n =4, 8 or 64)
Figure 14-1. Standard Operating Voltage Range
Table 14-7. RAM Data Retention Supply Voltage in Stop Mode
(TA = - 40 °C to + 85 °C)
Parameter Symbol Condition Min Typ Max Units
Data Retention Supply voltage
Data Retention Supply Current
Release Signal Set Time
Oscillation Stabilization Wait
(1)
Time
V
DDDR
I
DDDR
t
SREL
t
WAIT
– 2.0 — 6.0 V
V
DDDR
= 2.0 V
– 0 — – µs
Released by RESET
– 0.1 10 µA
–
217 / fx
– ms
Released by interrupt – (2) –
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14-8
Page 17
S3C7031/7032 ELECTRICAL DATA
TIMING WAVEFORMS
Internal RESET
Operation
~
~
Stop Mode
Idle Mode
VDD
RESET
VDD
Data Retention Mode
VDDDR
tSREL
tWAIT
Execution Of
Stop Instrction
~
~
Figure 14-2.Stop Mode Release Timing When Initiated By RESETRESET
Idle Mode
~
Execution Of
Stop Instrction
~
~
~
Stop Mode
Data Retention Mode
VDDDR
Normal Mode
tSREL
Operating
Mode
Power - Down Mode Terminating Signal
(Interrupt Request)
tWAIT
Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request
14-9
Page 18
ELECTRICAL DATA S3C7031/7032
0.7 VDD 0.7 VDD
Measurement
Points
0.3 VDD
0.3 VDD
Figure 14-4. A.C. Timing Measure Points (Except for XIN)
1/fx
tXL tXH
XIN
TIO
Figure 14-5. Clock Timing Measurement at X
1/fTCL
tTIL tTIH
Figure 14-6. TIO Timing
VDD - 0.5V
0.4 V
IN
0.7 VDD
0.3 VDD
14-10
Page 19
S3C7031/7032 ELECTRICAL DATA
tRSL
RESET
0.3 VDD
Figure 14-7. Input Timing for RESETRESET Signal
t
t
INTL
INTH
INT1
KS0 to KS3
0.7 V
DD
0.3 V
DD
Figure 14-8. Input Timing for External Interrupts
14-11
Page 20
ELECTRICAL DATA S3C7031/7032
tKCY
tKL tKH
SCK
SI
SO
tKSO tKIS
0.7 VDD
Input Data
0.3 VDD
tKSO
Output Data
0.7 VDD
0.3 VDD
Figure 14-9. Serial Data Transfer Timing
14-12
Page 21
S3C7031/7032 ELECTRICAL DATA
CHARACTERISTIC CURVES
NOTE
The characteristic values shown in the following graphs are based on actual test measurements. They do not,
however, represent guaranteed operating values.
70
63
54
49
42
35
IOL (mA)
28
21
14
7
0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0
VOL (V)
VDD = 4.5V
VDD = 6.0V
Figure 14-10. IOL vs. VOL (Port 0,1,2,3)
14-13
Page 22
ELECTRICAL DATA S3C7031/7032
100
90
80
70
60
50
IOL (mA)
40
30
20
10
0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0
VOL (V)
VDD = 4.5V
VDD = 6.0V
Figure 14-11. IOL vs. VOL (Port 0.0)
-30.0
-27.0
-24.0
-21.0
-18.0
-15.0
IOL (mA)
-12.0
-9.0
-6.0
-3.0
0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0
VDD = 4.5V
VOL (V)
VDD = 6.0V
14-14
Figure 14-12. IOH vs. VOH (Port 0,1,2,3except P0.0)
Page 23
S3C7031/7032 ELECTRICAL DATA
3.0
2.5
2.5
1.5
2
1.5
IDD (mA)
1
0.5
~
0
~
0
3.0
Figure 14-13. IDD vs. V
2
VDD = 5.5V(/4)
IDD1 (/4)
IDD2
4.0 5.0 6.0
VDD (V)
DD
IDD1(mA)
0.5
1
0
0
2.0
fx (MHz)
3.0
4.0 5.01.0
Figure 14-14. IDD vs. Frequency
14-15
Page 24
S3C7031/7032 MECHANICAL DATA
15 MECHANICAL DATA
This section contains the following information about the device package:
— A 20-pin DIP package is available for S3C7031/7032.
— A 20-pin SOP package is available for S3C7031/7032.
#20
±
6.40 0.20
(1.77)
0.46 0.10± 1.52 0.10±
NOTE: Dimensions are in millimeters
20-DIP-300A
26.40 0.20±
#11
#10#1
2.54
3.52 0.20±0.51 MIN
5.08 MAX
3.30 0.30±
7.62
0-15
0.25
+ 0.10
-
0.05
Figure 15-1. 20-pin DIP-300A Package Dimensions
15-1
Page 25
MECHANICAL DATA S3C7031/7032
#11#20
±
7.50 0.20
±
20-SOP-375
10.30 0.30
#1 #10
±
12.74 0.20
(0.66)
+ 0.10
0.40
-
0.05
NOTE: Dimensions are in millimeters
Figure 15-2. 20-pin SOP-375 Package Dimensions
1.27
0.203
2.30 0.10±
0.05 MIN
+ 0.10
-
0.05
0.85 0.20±
2.50 MAX
9.53
0-8
15-2
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