Datasheet RFD14N06L, RFD14N06LSM, RFP14N06L Datasheet (Intersil)

RFD14N06L, RFD14N06LSM, RFP14N06L

Data Sheet July 1999

14A, 60V, 0.100 Ohm, Logic Level,
N-Channel Power MOSFETs

These are N-Channel power MOSFETs manufacturedusing
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relaydrivers. This performance is accomplished
through a special gateoxide design which providesfullrated
conductance at gate bias in the 3V - 5V range, thereby
facilitating true on-off power control directly from logic level
(5V) integrated circuits.

Formerly developmental type TA09870.

Ordering Information

PART NUMBER PACKAGE BRAND

RFD14N06L TO-251AA 14N06L
RFD14N06LSM TO-252AA 14N06L
RFP14N06L TO-220AB FP14N06L

NOTE: When ordering, use the entire part number. Addthe suffix 9A, to
obtain the TO-252AA variant in tape and reel, i.e. RFD14N06LSM9A.

File Number

4088.3

Features

• 14A, 60V

DS(ON)

= 0.100Ω

®

Model

•r

• Temperature Compensating PSPICE

• Can be Driven Directly from CMOS, NMOS, and TTL
Circuits

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

D

G

S

Packaging

DRAIN (FLANGE)

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

GATE

DRAIN (FLANGE)

JEDEC TO-220AB

SOURCE

DRAIN

GATE

GATE

SOURCE

DRAIN (FLANGE)

6-1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFD14N06L, RFD14N06LSM, RFP14N06LS

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFD14N06L, RFD14N06LSM,

RFP14N06LS UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DSS

DGR

GS

DM

AS

D

Refer to Peak Current Curve

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

60 V
60 V

±10 V

14

Refer to UIS Curve

48

0.32

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
On Resistance r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)

Gate Charge at 5V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction-to-Case R
Thermal Resistance Junction-to-Ambient R

DSS

DSS

GSS

ON

r

f

OFF

g(5)

g(TH)

ISS
OSS
RSS

θJC

θJA

ID = 250µA, VGS = 0V, Figure 13 60 - - V
VGS = VDS, ID = 250µA, Figure 12 1 - 2 V
VDS = 48V,

VGS = 0V

TC = 25oC--1µA
TC = 150oC--50µA

VGS = ±10V - - 100 nA

= 14A, VGS = 5V - - 0.100 Ω

VDD = 30V, ID = 7A,
RL = 4.28Ω, VGS = 5V,
RGS = 0.6Ω
Figures 10, 18, 19

- - 60 ns

-13- ns

-24- ns

-42- ns

-16- ns

- - 100 ns
VGS = 0V to 10V VDD = 48V,
VGS = 0V to 5V - - 25 nC
VGS = 0V to 1V - - 1.5 nC

ID = 14A,
RL = 3.43Ω
Figures 20, 21

VDS = 25V, VGS = 0V,
f = 1MHz
Figure 14

- - 40 nC

- 670 - pF

- 185 - pF

-50- pF

- - 3.125
TO-251 and TO-252 - - 100
TO-220 - - 80

o
o
o

C/W
C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t

6-2

SD

rr

ISD = 14A - - 1.5 V
ISD = 14A, dISD/dt = 100A/µs - - 125 ns

RFD14N06L, RFD14N06LSM, RFP14N06L

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

25 50 75 100

0

0

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

125

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

1

150

175

16

12

8

, DRAIN CURRENT (A)

4

D

I

0

25 50 75 100

TC, CASE TEMPERATURE (oC)

125

150

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

175

0.5

0.2

0.1

0.1

NORMALIZED

JC,

θ

Z

100

10

, DRAIN CURRENT (A)

D

I

1

1

0.05

0.02

THERMAL IMPEDANCE

0.01

0.01

-5

10

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

VDS, DRAIN TO SOURCE VOLTAGE (V)

SINGLE PULSE

DS(ON)

10

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

-1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

TC = 25oC

= MAX RATED

T

J

100µs

1ms

10ms
100ms

DC

100

200

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

100

DM

10

-5

10

VGS = 10V

, PEAK CURRENT CAPABILITY (A)
I

VGS = 5V

-4

10

-3

10

t, PULSE WIDTH (s)

P

DM

t

1

t

2

1/t2

JA

θ

0

10

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

-2

10

o

C DERATE PEAK



=

II



25



-1

10

+ T

A

175 T

–

---------------------

150

TC = 25oC

0

10

1

10

C

1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

6-3

RFD14N06L, RFD14N06LSM, RFP14N06L

Typical Performance Curves

50

10

STARTING TJ = +150oC

If R = 0

, AVALANCHE CURRENT (A)

tAV = (L)(IAS)/(1.3*RATED BV

AS

I

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

1

0.01

0.1 1 10

tAV, TIME IN AVALANCHE (ms)

DSS

- VDD)

Unless Otherwise Specified (Continued)

STARTING TJ = 25oC

) +1]

DSS-VDD

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

35

VDD= 15V
PULSE DURATION = 80µs

30

DUTY CYCLE = 0.5% MAX

25

20

-55oC

25oC

175

35

= 10V

V

GS

30

25

20

15

10

, DRAIN CURRENT (A)

D

I

5

0

0

1.5
VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 5V
VGS = 4.5V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.

= 25oC

T

C

3.0 4.5 7.5

V

GS

VGS = 3V

VGS = 2.5V

6.0

= 4V

FIGURE 7. SATURATION CHARACTERISTICS

250

o

C

200

150

ID = 7A ID = 14A

ID = 28A

15

10

, DRAIN TO SOURCE CURRENT (A)

5

DS(ON)

I

0

0 3.0 4.5 6.0 7.51.5

VGS, GATE TO SOURCE VOLTAGE (V)

, DRAIN TO SOURCE

DS(ON)

r

ID = 3.5A

100

ON RESISTANCE (mΩ)

50

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

0

2.5 3.0 3.5 4.0 4.5
VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCEvs GATE

VOLTAGE AND DRAIN CURRENT

160

VDD = 25V, ID = 14A, RL = 1.78Ω

140

120

100

80

60

40

SWITCHING TIME (ns)

20

0

010203040

RGS, GATE TO SOURCE RESISTANCE (Ω)

t

d(OFF)

t

r

t

f

t

d(ON)

50

2.5

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

= 5V, ID = 14A

V

GS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

5.0

200

FIGURE 10. SWITCHING TIME vs GATE TO SOURCE

RESISTANCE

6-4

FIGURE 11. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

RFD14N06L, RFD14N06LSM, RFP14N06L

Typical Performance Curves

2.0
VGS = VDS, ID = 250µA

1.5

1.0

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

Unless Otherwise Specified (Continued)

FIGURE 12. NORMALIZED GATETHRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

800

C

ISS

600

VGS = 0V, f = 1MHz

= CGS + C

C

ISS

C

= C

400

C, CAPACITANCE (pF)

200

0

0 5 10 15 20 25

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

RSS
OSS

≈ CDS + C

GD

GD

GD

C

OSS

C

RSS

FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

200

2.0
ID = 250µA

1.5

1.0

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
T

, JUNCTION TEMPERATURE (oC)

J

FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

60

45

30

15

, DRAIN-SOURCE VOLTAGE (V)

DS

V

0

V

DD

= BV

I

--------------------- -

20

I

DSS

0.75 BV

0.50 BV

0.25 BV

RL = 3.57Ω
I

G(REF)

VGS = 5V

G REF()

GACT()

DSS
DSS
DSS

= 0.4mA

t, TIME (ms)

VDD = BV

I

G REF()

--------------------- -

80

I

GACT()

DSS

10

7.5

5.0

2.5

0

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

200

, GATE-SOURCE VOLTAGE (V)

GS

V

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

t

0V

P

AS

R

G

DUT

I

AS

0.01Ω

+

V

DD

-

0

FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

6-5

t

P

I

AS

t

AV

V

DS

V

DD

RFD14N06L, RFD14N06LSM, RFP14N06L

Test Circuits and Waveforms

R

G

V

GS

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

CURRENT

REGULATOR

12V

BATTERY

0

0.2µF

50kΩ

I

G(REF)

0.3µF

G

IG CURRENT

SAMPLING

RESISTOR RESISTOR

(Continued)

R

L

DUT

D

S

I
SAMPLING

V

DS

(ISOLATED
SUPPLY)

SAME TYPE
AS DUT

DUT

CURRENT

D

t

ON

t

d(ON)

t

V

DS

+

V

DD

-

V

DS

0

V

0

V

DD

VGS= 1V

0

I

G(REF)

0

GS

10%

V

GS

90%

50%

Q

10%

g(TH)

r

PULSE WIDTH

V

DS

Q

g(5)

Q

g(TOT)

VGS= 5V

t

d(OFF)

90%

t

OFF

50%

t

f

10%

VGS= 10V

90%

FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS

6-6

RFD14N06L, RFD14N06LSM, RFP14N06L

PSPICE Electrical Model

.SUBCKT RFP14N06L 2 1 3 ; rev 9/15/94
CA 12 8 1.464e-9
CB 15 14 1.64e-9
CIN 6 8 6.17e-10

DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 65.35
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1

IT 8 17 1

LDRAIN 2 5 1e-9
LGATE 1 9 5.68e-9
LSOURCE 3 7 5.35e-9

MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 33.1e-3
RGATE 9 20 5.85
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 14.3e-3
RVTO 18 19 RVTOMOD 1

GATE

1

LGATE

9

RGATE

10

ESG

EVTO

20

+

18

8

S1A

12

13814

S1B

CA

EGS

DPLCAP

RSCL2

6
8

+

RIN

+

VTO

6

S2A

15

13

S2B

13

6
8

EDS

CIN

CB

5

LDRAIN

RSCL1

ESCL

8

DBREAK

EBREAK

MOS2

RSOURCE

11

17

+

17
18

7

RBREAK

IT

DBODY

LSOURCE

51

+

5

51

50
RDRAIN

16

+

21

MOS1

14

+

5
8

18

RVTO

19

VBAT

+

DRAIN
2

3
SOURCE

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1
VTO 21 6 0.485

ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/46,7))}

.MODEL DBDMOD D (IS = 2.23e-13 RS = 1.15e-2 TRS1 = 1.64e-3 TRS2 = 7.89e-6 CJO = 6.83e-10 TT = 3.68e-8)
.MODEL DBKMOD D (RS = 3.8e-1 TRS1 = 1.89e-3 TRS2 = 1.13e-5)
.MODEL DPLCAPMOD D (CJO = 25.7e-11 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 1.935 KP = 18.89 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 7.18e-4 TC2 = 1.53e-6)
.MODEL RDSMOD RES (TC1 = 4.45e-3 TC2 = 2.9e-5)
.MODEL RSCLMOD RES (TC1 = 2.8e-3 TC2 = 6.0e-6)
.MODEL RVTOMOD RES (TC1 = -1.7e-3 TC2 = -2.0e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.55 VOFF= -1.55)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.55 VOFF= -3.55)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.55 VOFF= 2.45)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.45 VOFF= -2.55)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature
Options; authored by William J. Hepp and C. Frank Wheatley.

6-7

RFD14N06L, RFD14N06LSM, RFP14N06L

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However ,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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6-8

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