Datasheet RF1S70N06SM Datasheet (Intersil)

RFG70N06, RFP70N06, RF1S70N06SM

Data Sheet July 1999 File Number

70A, 60V, 0.014 Ohm, N-Channel Power
MOSFETs

These are N-Channel power MOSFETs manufacturedusing
the MegaFET process. This process, which uses feature
sizes approaching those of LSI circuits, gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switchingregulators,switchingconverters, motor drivers and
relaydrivers. These transistors can be operated directly from
integrated circuits.

Formerly developmental type TA49007.

Ordering Information

PART NUMBER PACKAGE BRAND

RFG70N06 TO-247 RFG70N06
RFP70N06 TO-220AB RFP70N06
RF1S70N06SM TO-263AB F1S70N06

NOTE: When ordering use the entire part number. Add the suffix 9A to
obtain the TO-263AB variant in tape and reel, e.g. RF1S70N06SM9A.

Features

• 70A, 60V

DS(on)

= 0.014Ω

®

Model

•r

• Temperature Compensated PSPICE

• Peak Current vs Pulse Width Curve

• UIS Rating Curve (Single Pulse)

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

3206.5

Packaging

DRAIN

(BOTTOM

SIDE METAL)

JEDEC STYLE TO-247 JEDEC TO-220AB

SOURCE

DRAIN

GATE

DRAIN

(FLANGE)

JEDEC TO-263AB

DRAIN

GATE

SOURCE

(FLANGE)

SOURCE

DRAIN

GATE

4-474

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFG70N06, RFP70N06, RF1S70N06SM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFG70N06, RFP70N06

RF1S70N06SM UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . .V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DSS

DGR

DM

GS

AS

D

Refer to Peak Current Curve

D

Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

60 V
60 V
70

±20 V

Refer to UIS Curve A

150

1.0

W/oC

-55 to 175

300
260

A

W

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

(OFF)
g(TOT)

Gate Charge at 10V Q
Threshold Gate Charge Q

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance, Junction to Case R
Thermal Resistance, Junction to Ambient R

DSS

DSS

GSS

(ON)

r

f

g(10)

g(TH)

ISS

OSS

RSS

θJC
θJA

ID = 250µA, VGS = 0V (Figure 11) 60 - - V
VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V
VDS = 60V, VGS = 0V - - 1 µA
VDS = 0.8 x Rated BV

, TC = 150oC--25µA

DSS

VGS = ±20V - - ±100 nA
ID = 70A, VGS = 10V (Figure 9) - - 0.014 Ω
VDD = 30V, I

VGS = 10V, RGS = 2.5Ω
(Figure 13)

≈ 70A, R

D

= 0.43Ω,

L

- - 125 ns

-12- ns

-50- ns

-40- ns

-15- ns

- - 125 ns
VGS = 0V to 20V VDD = 48V, ID = 70A,
VGS = 0V to 10V - 100 115 nC
VGS = 0V to 2V - 5.5 6.5 nC

RL = 0.68Ω
I

= 2.2mA

g(REF)

(Figure 13)

VDS = 25V, VGS = 0V, f = 1MHz
(Figure 12)

- 185 215 nC

- 3000 - pF

- 900 - pF

- 300 - pF

- - 1.0oC/W
TO-220 and TO-263 - - 62
TO-247 - - 30

o
o

C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t

SD

rr

NOTES:

2. Pulse test: pulse width ≤ 300ms, duty cycle ≤ 2%.

3. Repetitive rating:pulse width is limited bymaximum junction temperature. SeeTransient Thermal Impedance curve (Figure3) and Peak Current
Capability Curve (Figure 5).

4-475

ISD = 70A - 1.5 V
ISD = 70A, dISD/dt = 100A/µs - 125 ns

RFG70N06, RFP70N06, RF1S70N06SM

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

125

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

1

0.5

150

80

70

60

50

40

30

, DRAIN CURRENT (A)

20

D

I

10

0

25 50 75 100

TC, CASE TEMPERATURE (oC)

125

150

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

175

0.2

0.1

0.1

, NORMALIZED

JC

θ

Z

500

100

10

, DRAIN CURRENT (A)

D

I

1

1

0.05

0.02

THERMAL IMPEDANCE

0.01

0.01

-5

10

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

TC = 25oC

= MAX RATED

T

J

SINGLE PULSE

VDS, DRAIN TO SOURCE VOLTAGE (V)

SINGLE PULSE

DS(ON)

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

-1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

1000

100µs

1ms

10ms

100ms

DC

10

100

, PEAK CURRENT (A)

DM

100

I

50

10

VGS = 10V

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-5

-4

10

10

t, PULSE WIDTH (s)

-3

P

DM

t

1

t

2

1/t2

x R

JC

θ

0

10

TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:

=

II

-2

10

+ T

JC

C

θ

–

175 T




25



10

----------------------­150

-1

C

0

10

1

10

1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

4-476

RFG70N06, RFP70N06, RF1S70N06SM

Typical Performance Curves

300

100

, AVALANCHE CURRENT (A)

STARTING TJ = 150oC

AS

I

10

0.01

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R) ln [(IAS*R)/(1.3*RATED BV

AV

STARTING TJ = 25oC

0.1

tAV, TIME IN AVALANCHE (ms)

Unless Otherwise Specified (Continued)

- VDD)

DSS

) +1]

DSS-VDD

1

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

200

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD= 15V

160

-55oC

25oC

175oC

200

160

120

80

, DRAIN CURRENT (A)

D

I

40

0

10

0123 5

= 20V

V

GS

VDS, DRAIN TO SOURCE VOLTAGE (V)

= 10V

V

GS

VGS = 8V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T

= 25oC

C

VGS = 7V

VGS = 6V

= 5V

V

GS

= 4.5V

V

GS

4

FIGURE 7. SATURATION CHARACTERISTICS

2.5

PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 70A

2

120

80

40

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

I

0

0

VGS, GATE TO SOURCE VOLTAGE (V)

468102

1.5

1

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

2.0
VGS = VDS, ID = 250µA

1.5

1.0

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

200

2.0
ID = 250µA

1.5

1.0

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
, JUNCTION TEMPERATURE (oC)

T

J

200

200

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

4-477

FIGURE 11. NORMALIZED DRAIN TOSOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

RFG70N06, RFP70N06, RF1S70N06SM

Typical Performance Curves

Unless Otherwise Specified (Continued)

5000

VGS = 0V, f = 1MHz

4000

ISS

C

= C

RSS

C

≈ C

C

ISS

OSS

GD

DS

GD

+ C

= CGS + C

C

3000

2000

C

C, CAPACITANCE (pF)

1000

0

0 5 10 15 20

OSS

C

RSS

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

Test Circuits and Waveforms

V

DS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

DUT

+

-

GS

V

DD

60

VDD = BV

45

DSS

VDD = BV

DSS

10

7.5

RL = 0.86Ω

I

= 2.2mA

30

15

G(REF)

VGS = 10V

0.75 BV

0.50 BV

0.25 BV

DSS
DSS
DSS

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

25

0

20

I

G(REF)

I

G(ACT)

t, TIME (µs)

80

I

G(REF)

I

G(ACT)

5

2.5

0

, GATE TO SOURCE VOLTAGE (V)

GS

V

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

BV

DSS

t

P

I

AS

V

DS

V

DD

0V

P

I

AS

0.01Ω

0

t

AV

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

10%

d(ON)

90%

50%

t

10%

r

PULSE WIDTH

V

DS

V

DS

R

DUT

L

+

V

DD

-

0

V

GS

0

V

GS

R

GS

V

GS

t

d(OFF)

90%

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. SWITCHING WAVEFORMS

t

OFF

50%

t

f

90%

10%

4-478

RFG70N06, RFP70N06, RF1S70N06SM

Test Circuits and Waveforms

V

DS

V

GS

I

g(REF)

FIGURE 18. GATE CHARGE TEST CIRCUIT

(Continued)

R

L

DUT

V

DD

+

V

DD

-

VGS= 2V

0

I

g(REF)

0

V

GS

Q

g(TH)

Q

V

DS

g(10)

Q

g(TOT)

VGS= 20V

VGS = 10V

FIGURE 19. GATE CHARGE WAVEFORM

4-479

RFG70N06, RFP70N06, RF1S70N06SM

PSPICE Electrical Model

.SUBCKT RFG70N06 2 1 3 ; rev 3/20/92

CA 12 8 5.56e-9
CB 15 14 5.30e-9
CIN 6 8 2.63e-9

DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 65.18
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1

IT 8 17 1

LDRAIN 2 5 1e-9
LGATE 1 9 3.10e-9
LSOURCE 3 7 1.82e-9

MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 4.66e-3
RLDRAIN 2 5 10
RGATE 9 20 1.21
RLGATE 1 9 31
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 3.92e-3
RLSOURCE 3 7 18.2
RVTO 18 19 RVTOMOD 1

RLGATE

GATE

1

LGATE

9

RGATE

10

-

6

ESG

8

+

EVTO

20

+

18

8

S1A

12

S1B

CA CB

6

-

RIN

13814

13

13

+

6

EGS

8

--

DPLCAP

VTO

-

S2A

15

S2B

CIN

EDS

RLDRAIN

5

LDRAIN

RSCL1RSCL2

+

51

5

ESCL

51

50

RDRAIN

16

+

21

MOS1

14

+

5
8

8

DBREAK

EBREAK

MOS2

RSOURCE

11

17

+

17

18

-

RBREAK

IT

DBODY

RLSOURCE

7

LSOURCE

2

DRAIN

3

SOURCE

18

RVTO

19

VBAT

+

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1
VTO 21 6 0.605

.MODEL DBDMOD D (IS = 7.91e-12 RS = 3.87e-3 TRS1 = 2.71e-3 TRS2 = 2.50e-7 CJO = 4.84e-9 TT = 4.51e-8)
.MODEL DBKMOD D (RS = 3.9e-2 TRS1 =1.05e-4 TRS2 = 3.11e-5)
.MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 3.46 KP = 47 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 8.46e-4 TC2 = -8.48e-7)
.MODEL RDSMOD RES (TC1 = 2.23e-3 TC2 = 6.56e-6)
.MODEL RVTOMOD RES (TC1 = -3.29e-3 TC2 = 3.49e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8.35 VOFF= -6.35)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.35 VOFF= -8.35)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 3.0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.0 VOFF= -2.0)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.

4-480

RFG70N06, RFP70N06, RF1S70N06SM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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