Datasheet RF1K49154 Datasheet (Intersil)

RF1K49154

Data Sheet October 1999

2A, 60V, 0.130 Ohm, Dual N-Channel,
LittleFET™ Power MOSFET

This Dual N-Channel powerMOSFETismanufacturedusing
the latest manufacturing process technology. This process,
which uses feature sizes approaching those of LSI
integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. It is designed for use
in applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low voltage bus
switches. These devices can be operated directly from
integrated circuits.

Formerly developmental type TA49154.

Ordering Information

PART NUMBER PACKAGE BRAND

RF1K49154 MS-012AA RF1K49154

NOTE: When ordering, use the entire part number. For ordering in
tape andreel, add thesuffix96 to thepart number, i.e., RF1K4915496.

File Number 4143.3

Features

• 2A, 60V

•r

DS(ON)

• Temperature Compensating PSPICE

= 0.130Ω

®

Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D1(8)
D1(7)

S1(1)

G1(2)

Packaging

JEDEC MS-012AA

BRANDING DASH

1

2

D2(6)
D2(5)

S2(3)

G2(4)

5

3

4

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

LittleFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.

1-888-INTERSIL or 407-727-9207

| Copyright © Intersil Corporation 1999.

RF1K49154

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

A

RF1K49154 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS= 20kΩ, Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain Current Continuous (Pulse width = 5s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

DSS

DGR

GS

DM

AS

D

Refer to Peak Current Curve

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

60 V
60 V

±20 V

2

Refer to UIS Curve

2

0.016

-55 to 150

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ = 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V
Zero Gate Voltage Drain Current I

DSSID

GS(TH)VGS

DSS

= 250µA, VGS = 0V, (Figure 12) 60 - - V

= VDS, ID = 250µA, (Figure 11) 2 - 4 V
VDS = 55V, VGS = 0V - - 1 µA
VDS = 50V, VGS = 0V, TC = 150oC - - 250 µA

Gate to Source Leakage Current I
Drain to Source On Resistance r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)VGS

Gate Charge at 10V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Ambient R

GSS

ON

OFF

g(10)

g(TH)

ISS

OSS

RSS

θJA

VGS = ±20V - - ±10 µA

= 2A, VGS = 10V, (Figures 9, 10) - - 0.130 Ω

VDD = 30V, ID≈ 2A,
RL = 15Ω, VGS = 10V,
RGS = 25Ω
(Figure 14)

r

- - 50 ns

-10-ns

-25-ns

-70-ns

f

-35-ns

- - 155 ns

= 0V to 20V VDD = 48V,
VGS = 0V to 10V - 14 17 nC
VGS = 0V to 2V - 0.8 1.0 nC

ID = 2A,
RL = 24Ω
(Figure 14)

VDS = 25V, VGS = 0V,
f = 1MHz (Figure 13)

-2632nC

- 340 - pF

- 140 - pF

-40-pF

Pulse Width = 1s

- - 62.5

o

C/W

Device Mounted on FR-4 Material

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t

2

SD

rr

ISD = 2A - - 1.5 V
ISD = 2A, dISD/dt = 100A/µs--62ns

RF1K49154

Typical Performance Curves T

= 25oC, Unless Otherwise Specified

A

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

125

TA, AMBIENT TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWERDISSIPATIONvs AMBIENT

TEMPERATURE

5

1

0.1

, NORMALIZED

θJA

Z

0.01

THERMAL IMPEDANCE

0.001

-5

10

DUTY CYCLE

DESCENDING ORDER

0.5

0.2

0.1

0.05

0.02

0.01

SINGLE PULSE

-4

10

-3

10

2.5

2

1.5

1

, DRAIN CURRENT (A)

D

I

0.5

0

25 50 75 100 125 150

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

AMBIENT TEMPERATURE

-2

10

t, RECTANGULAR PULSE DURATION (s)

-1

10

0

10

TA, AMBIENT TEMPERATURE (oC)

P

DM

t

1

t

2

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

1

10

θJA

10

1/t2

2

x R

θJA

+ T

A

3

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

100

THERMAL IMPEDANCE

10

MAY LIMIT CURRENT
IN THIS REGION

, PEAK CURRENT CAPABILITY (A)

DM

I

1

-5

10

-4

10

V

= 20V

GS

VGS = 10V

-3

10

t, PULSE WIDTH (s)

FOR TEMPERATURES
ABOVE 25

o

CURRENT AS FOLLOWS:

I = I

25

-2

10

10

20

10

1

, DRAIN CURRENT (A)

D

OPERATION IN THIS

I

AREA MAY BE
LIMITED BY r

0.1

0.1
V

DS

TJ = MAX RATED
T

= 25oC

A

5ms
10ms

DS(ON)

V

DSS (MAX)

1 10 200

= 60V

100

, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

3

TA = 25oC

C DERATE PEAK

150 - T

A

125

-1

0

10

1

10

RF1K49154

Typical Performance Curves T

10

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

5

, AVALANCHE CURRENT (A)

AS

I

STARTING TJ = 150oC

1

0.1
tAV, TIME IN AVALANCHE (ms)

STARTING TJ = 25oC

1 10 100

DSS

- VDD)

= 25oC, Unless Otherwise Specified (Continued)

A

- VDD) +1]

DSS

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

20

VDD= 15V
PULSE DURATION = 80µs

16

DUTY CYCLE = 0.5% MAX

12

-55oC

25oC

150oC

20

V

= 20V

GS

VGS = 10V

15

10

, DRAIN CURRENT (A)

5

D

I

0

0 1.5 3.0 4.5 6.0 7.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

V

GS

VGS = 8V

= 9V

VGS = 7V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC

= 6V

V

GS

V

= 5V

GS

FIGURE 7. SATURATION CHARACTERISTICS

500

400

300

ID = 0.5A

= 1A

I

D

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD= 15V

ID = 4A

ID = 2A

8

4

, ON-STATE DRAIN CURRENT (A)

D(ON)

I

0

0468102

VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE

2

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V

= 10V, ID = 2A

GS

1.5

1

0.5

NORMALIZED ON RESISTANCE

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

200

, ON-STATE RESISTANCE (mΩ)

100

DS(ON)

r

0

26810

4

, GATE TO SOURCE VOLTAGE (V)

V

GS

VOLTAGE AND DRAIN CURRENT

1.5
VGS = VDS,

1.25

1

NORMALIZED GATE

0.75

THRESHOLD VOLTAGE

0.5

-80 -40 0 40 80 120 160

I

= 250µA

D

TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

4

FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

RF1K49154

Typical Performance Curves T

1.5
ID = 250µA

1.25

1

0.75

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.5

-80

-40 0 40 80 120
T

, JUNCTION TEMPERATURE (oC)

J

= 25oC, Unless Otherwise Specified (Continued)

A

FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

60

45

30

PLATEAU VOLTAGES IN

15

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

DESCENDING ORDER:

I

GREF()

--------------------- -

20

I

G ACT()

160

VDD = BV

RL = 30Ω

= 0.26mA

I

G(REF)

= 10V

V

GS

VDD = BV
VDD = 0.75 BV
VDD = 0.50 BV
VDD = 0.25 BV

DSS

t, TIME (µs)

500

400

300

200

C, CAPACITANCE (pF)

100

0

0 5 10 15 20 25

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

C

C

ISS

OSS

RSS

VGS = 0V, f = 1MHz

= CGS + C

C

ISS

C

= C

RSS

C

= CDS + C

OSS

FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

10

7.5

DSS

5

DSS
DSS
DSS

I

GREF()

--------------------- -

80

I

G ACT()

2.5

0

, GATE TO SOURCE VOLTAGE (V)

GS

V

GD

GD

GD

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

t

0V

P

AS

R

G

DUT

I

AS

0.01Ω

+

V

DD

-

0

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

5

t

P

I

AS

t

AV

V

DS

V

DD

Test Circuits and Waveforms (Continued)

RF1K49154

t

ON

t

10%

d(ON)

90%

50%

t

10%

r

PULSE WIDTH

V

DS

V

DS

R

DUT

L

+

V

DD

-

0

V

GS

0

V

GS

R

GS

V

GS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

V

I

g(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

VGS= 2V

0

Q

g(TOT)

V

DS

Q

OR Q

g(10)

V

GS

VGS= 1V FOR

g(5)

V

GS

VGS= 5V FOR

2

L

DEVICES

L2 DEVICES

Q

g(TH)

t

d(OFF)

90%

= 10V

t

OFF

t

f

10%

50%

VGS= 20V

V

= 10V FOR

GS

L2 DEVICES

90%

I

g(REF)

0

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

6

RF1K49154

PSPICE Electrical Model

SUBCKT RF1K49154 2 1 3 ; rev 2/2/96

CA 12 8 3.5e-10
CB 15 14 3.7e-10
CIN 6 8 2.26e-10

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 63
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

GATE

IT 8 17 1
LDRAIN 2 5 1e-9

LGATE 1 9 1.4e-9
LSOURCE 3 7 3.1e-10
K1 LGATE LSOURCE 0.131

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7.0e-3
RGATE 9 20 1.9
RLDRAIN 2 5 10
RLGATE 1 9 14
RLSOURCE 3 7 3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 5.6e-2

ESG

LGATE

1

RLGATE

9

RGATE

CA

EVTEMP
+

18
22

20

S1A

12

13

8

S1B

EGS EDS

-

+

-

13

10

6
8

+

+

RSLC2

6

S2A

14
13

S2B

6
8

-

-

DPLCAP

EVTHRES

+

19

8

CIN

15

CB

-

+

-

5

RSLC1

51

5

51

50
RDRAIN

21

MSTRO

14

5
8

+

-

ESLC

16

8

MMED

DBREAK

11

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

17
18

-

RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),3))}
.MODEL DBODYMOD D (IS = 2.6e-13 RS = 2.34e-2 IKF = 5.5 N = 0.995 TRS1 = 2.8e-3 TRS2 = 1.1e-5 CJO = 3.7e-10 TT = 3.5e-8 M = 0.46

+ XTI = 5.5)
.MODEL DBREAKMOD D (RS = 0.5 IKF = 0.1 N = 1 TRS1 = 3e-3 TRS2 = -5e-5)
.MODEL DPLCAPMOD D (CJO = 5.6e-10 IS = 1e-30 N = 10 M = 0.92)
.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 1.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.9)
.MODEL MSTROMOD NMOS (VTO = 3.68 KP = 13.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.83 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 19 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.08e-3 TC2 = 5e-7)
.MODEL RDRAINMOD RES (TC1 = 1.7e-2 TC2 = 1e-4)
.MODEL RSLCMOD RES (TC1 = 1e-9 TC2 = 1e-4)
.MODEL RSOURCEMOD RES (TC1 = 3.3e-3 TC2 = 1e-9)
.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -4e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.9e-3 TC2 = 2.2e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.1 VOFF= -4)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4 VOFF= -7.1)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.01 VOFF= 1.9)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.9 VOFF= 0.01)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.

LDRAIN

RLDRAIN

DBODY

LSOURCE

7

RLSOURCE

RVTEMP
19

-

VBAT

+

22

DRAIN

2

SOURCE

3

7

RF1K49154

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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