Datasheet RF1K49224 Datasheet (Intersil)

RF1K49224

Data Sheet August 1999 File Number

3.5A/2.5A, 30V, 0.060/0.150 Ohms, Complementary LittleFET™ Power MOSFET

The RF1K49224 complementary power MOSFET is manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It is designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and low voltage bus switches. This device can be operated directly from intergrated circuits.

Formerly developmental type TA49224.

Ordering Information

PART NUMBER PACKAGE BRAND

RF1K49224 MS-012AA RF1K49224

NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e.RF1K4922496.

Features

• 3.5A, 30V (N-Channel)

2.5A, 30V (P-Channel)

•r r

• Temperature Compensating PSPICE

= 0.060Ω (N-Channel)

DS(ON)

= 0.150Ω (P-Channel)

DS(ON)

®

Model

• Thermal Impedance PSPICE Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

D1(8) D1(7)

S1(1)

G1(2)

4330.1

Packaging

JEDEC MS-012AA

BRANDING DASH

1

2

D2(6) D2(5)

S2(3)

G2(4)

5

3

4

9-16

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

LittleFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

RF1K49224

Absolute Maximum Ratings T

= 25oC Unless Otherwise Speciﬁed

A

N-CHANNEL P-CHANNEL UNITS

Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS= 20kΩ ) . . . . . . . . . . . . . . .V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

30 -30 V 30 -30 V

±20 ±20 V

Drain Current

Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . .I

Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DM

AS

D

Refer to Peak Current Curve

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

L

pkg

3.5

2.5

Refer to Peak Current Curve

Refer to UIS Curve Refer to UIS Curve

2

0.016

2

0.016

-55 to 150 -55 to 150

300 260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 125oC.

N-Channel Electrical Speciﬁcations T

= 25oC, Unless Otherwise Speciﬁed

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV Gate to Source Threshold Voltage V Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I Drain to Source On Resistance r

DS(ON)ID

DSSID

GS(TH)VGS

DSS

GSS

= 250µA, VGS = 0V 30 - - V

= VDS, ID = 250µA 1-3V

VDS = 30V, VGS = 0V

TA = 25oC--1µA TA = 150oC--50µA

VGS = ±20V - - 100 nA

= 3.5A VGS = 10V - - 0.060 Ω

VGS = 4.5V 0.132 Ω Turn-On Time t Turn-On Delay Time t

d(ON)

Rise Time t Turn-Off Delay Time t

d(OFF)

Fall Time t Turn-Off Time t Total Gate Charge Q

g(TOT)VGS

Gate Charge at 10V Q Threshold Gate Charge Q Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Thermal Resistance Junction to Ambient R

ON

OFF

g(10)

g(TH)

ISS

OSS

RSS

θ

VDD = 15V, I RL = 4.29Ω, VGS = 10V, RGS = 25Ω

r

≅ 3.5A,

D

- - 50 ns

-10-ns

-30-ns

-60-ns

f

-45-ns

- - 130 ns

= 0V to 20V VDD = 24V,

I

≅ 3.5A,

VGS = 0V to 10V - 13 17 nC VGS = 0V to 2V - 2.3 2.9 nC

D

RL = 6.86Ω

I

= 1.0mA

g(REF)

VDS = 25V, VGS = 0V, f = 1MHz

-3545nC

- 575 - pF

- 275 - pF

- 100 - pF

JA

Pulse width = 1s

- - 62.5

Device mounted on FR-4 material

o

C/W

N-Channel Source to Drain Diode Speciﬁcations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V Reverse Recovery Time t

9-17

SD

ISD = 3.5A - - 1.25 V ISD = 3.5A, dISD/dt = 100A/µs--45ns

rr

RF1K49224

P-Channel Electrical Speciﬁcations T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV Gate to Source Threshold Voltage V Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I Drain to Source On Resistance r

Turn-On Time t Turn-On Delay Time t Rise Time t Turn-Off Delay Time t Fall Time t Turn-Off Time t Total Gate Charge Q Gate Charge at -10V Q Threshold Gate Charge Q Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Thermal Resistance Junction to Ambient R

= 25oC, Unless Otherwise Speciﬁed

A

DSSID

GS(TH)VGS

DSS

GSS

DS(ON)ID

= 250µA, VGS = 0V -30 - - V

= VDS, ID = 250µA -1 - -3 V

VDS = -30V, VGS = 0V

TA = 25oC---1µA TA = 150oC - - -50 µA

VGS = ±20V - - 100 nA

= 2.5A VGS = -10V - - 0.150 Ω

VGS = -4.5v 0.360 Ω

ON

VDD = -15V, I

≅ 2.5A,

D

RL = 6Ω, VGS = -10V,

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(-10) g(TH)

ISS

RGS = 25Ω

r

f

= 0V to -20V V VGS = 0V to -10V - 15 19 nC VGS = 0V to -2V - 1.5 1.9 nC

I RL = 9.6Ω I

VDS = -25V, VGS = 0V, f = 1MHz

OSS RSS

θJA

Pulse width = 1s Device mounted on FR-4 material

DD

≅ 2.5A,

D

g(REF)

= -24V,

= -1.0mA

- - 40 ns

-9-ns

-19-ns

-60-ns

-34-ns

- - 140 ns

-2835nC

- 580 - pF

- 260 - pF

-38-pF

- - 62.5

o

C/W

P-Channel Source to Drain Diode Speciﬁcations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V Reverse Recovery Time t

ISD = -2.5A - - -1.25 V

SD

ISD = -2.5A, dISD/dt = -100A/µs--49ns

rr

Typical Performance Curves (N-Channel)

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TA, AMBIENT TEMPERATURE (oC)

FIGURE 1. NORMALIZEDPOWER DISSIPATIONvs AMBIENT

TEMPERATURE

125

4.0

3.5

3.0

2.5

2.0

1.5

, DRAIN CURRENT (A)

1.0

D

I

0.5 0

25

50

TA, AMBIENT TEMPERATURE (oC)

75 100 125 150

FIGURE 2. MAXIMUM CONTINUOUSDRAINCURRENTvs

AMBIENT TEMPERATURE

9-18

RF1K49224

Typical Performance Curves (N-Channel)

10

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

1

0.05

0.02

0.01

0.1

, NORMALIZED

JA

θ

Z

0.01

THERMAL IMPEDANCE

0.001

-5

10

100

10

1

, DRAIN CURRENT (A)

D

0.1

OPERATION IN THIS

I

AREA MAY BE LIMITED BY r

0.01

0.1 VDS, DRAIN TO SOURCE VOLTAGE (V)

DS(ON)

SINGLE PULSE

-4

10

-3

10

-2

10

t, RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

TJ = MAX RATED T

= 25oC

A

5ms

10ms

100ms

1s

V

DSS(MAX)

= 30V

1 10 100

DC

(Continued)

10

-1

10

200

100

VGS = 10V

10

TRANSCONDUCTANCE MAY LIMIT CURRENT

, PEAK CURRENT (A)

IN THIS REGION

DM

I

1

-5

10

P

DM

t

1

t

NOTES: DUTY FACTOR: D = t

PEAK TJ = PDM x Z

0

1

10

TA = 25oC

θ

FOR TEMPERATURES ABOVE 25

2

1/t2

x R

JA

+ T

JA

θ

2

10

o

C DERATE PEAK

A

3

10

CURRENT AS FOLLOWS:

150 - T

I = I

25

-4

10

-3

10

-2

10

A

125

-1

0

10

1

10

t, PULSE WIDTH (s)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

20

If R = 0 tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

10

DSS

- VDD)

DSS

- VDD) +1]

25

V

= 20V

20

GS

VGS = 10V

15

, AVALANCHE CURRENT (A)

AS

I

STARTING TJ = 150oC

1

0.1 tAV, TIME IN AVALANCHE (ms)

STARTING TJ = 25oC

1 10 100

10

, DRAIN CURRENT (A)

D

I

5

0

012345

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

= 25oC

T

A

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

FIGURE 7. SATURATION CHARACTERISTICS

9-19

VGS = 5V

VGS = 4.5V

VGS = 4V

V

= 3V

GS

RF1K49224

Typical Performance Curves (N-Channel)

25

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

20

15

10

5

, ON-STATE DRAIN CURRENT (A)

D(ON)

I

0

VGS, GATE TO SOURCE VOLTAGE (V)

3.0 4.5 6.0 7.51.5

25oC

-55oC 150oC

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCEvsGATE

2.0

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 3.5A

1.5

V

= 15V

DD

(Continued)

250

= 7.0A

I

200

150

100

, DRAIN TO SOURCE

ID = 0.5A

ON RESISTANCE (mΩ)

DS(ON)

50

r

0

38910

D

I

= 3.5A

D

ID = 1.75A

VGS, GATE TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD= 15V

6475

VOLTAGE AND DRAIN CURRENT

2.0 VGS = VDS, ID = 250µA

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED DRAIN TOSOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

2.0 ID = 250µA

1.5

1.0

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80

-40 0 40 80 120 , JUNCTION TEMPERATURE (oC)

T

J

160

1.0

0.5

NORMALIZED GATE

THRESHOLD VOLTAGE

0

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

1000

750

C

ISS

500

C

OSS

C, CAPACITANCE (pF)

250

C

RSS

0

0 5 10 15 20

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 0V, f = 1MHz

= CGS + C

C C C

ISS RSS OSS

= C

GD

= CDS + C

GD

25

FIGURE 12. NORMALIZEDDRAINTO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

9-20

FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

RF1K49224

Typical Performance Curves (N-Channel)

30

VDD = BV

DSS

22.5

15

PLATEAU VOLTAGES IN DESCENDING ORDER:

7.5

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

I

g REF()

20

----------------------- I

g ACT()

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT

Test Circuits and Waveforms (N-Channel)

V

DS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

DUT

+

V

DD

-

(Continued)

R

= 8.57Ω

L

I

= 0.75mA

g(REF)

VGS = 10V

VDD = BV VDD = 0.75 BV VDD = 0.50 BV VDD = 0.25 BV

DSS

t, TIME (ms)

DSS DSS DSS

80

VDD = BV

I

g REF()

----------------------- I

gACT()

DSS

10.0

7.5

5.0

2.5

0

, GATE TO SOURCE VOLTAGE (V)

GS

V

BV

DSS

t

P

I

AS

V

DS

V

DD

0V

P

I

AS

0.01Ω

0

t

AV

t

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

d(ON)

t

R

L

V

GS

DS

+

V

DD

-

V

DS

90%

0

r

10%

DUT

R

GS

V

GS

V

GS

10%

0

50%

PULSE WIDTH

t

d(OFF)

90%

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

t

OFF

50%

t

f

10%

90%

9-21

RF1K49224

Test Circuits and Waveforms (N-Channel)

V

DS

R

L

V

I

g(REF)

GS

DUT

+

V

DD

-

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORM

Typical Performance Curves (P-Channel)

1.2

1.0

(Continued)

V

I

g(REF)

DD

V

VGS= 2V

0

-3.0

-2.5

GS

Q

g(TH)

Q

V

DS

g(10)

Q

g(TOT)

VGS= 20V

VGS = 10V

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TA, AMBIENT TEMPERATURE (oC)

125

FIGURE 21. NORMALIZEDPOWER DISSIPATIONvs AMBIENT

TEMPERATURE

10

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

1

0.05

0.02

0.01

0.1

, NORMALIZED

JA

θ

Z

0.01

THERMAL IMPEDANCE

0.001

-5

10

SINGLE PULSE

-4

10

-3

10

-2

10

t, RECTANGULAR PULSE DURATION (s)

-2.0

-1.5

-1.0

, DRAIN CURRENT (A)

D

I

-0.5

0

25

50

TA, AMBIENT TEMPERATURE (oC)

75 100 125 150

FIGURE 22. MAXIMUM CONTINUOUSDRAINCURRENTvs

AMBIENT TEMPERATURE

P

DM

t

1

t

JA

1/t2

10

x R

2

+ T

JA

θ

NOTES: DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-1

10

0

10

1

10

θ

A

3

10

FIGURE 23. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

9-22

RF1K49224

Typical Performance Curves (P-Channel)

-50

-10

-1

, DRAIN CURRENT (A)

-0.1

D

I

OPERATION IN THIS AREA MAY BE LIMITED BY r

-0.01

-0.1 VDS, DRAIN TO SOURCE VOLTAGE (V)

V

DS(ON)

-1 -10

DSS(MAX)

TJ = MAX RATED

= 25oC

T

A

= -30V

5ms

10ms

100ms

1s

DC

(Continued)

-100

-10

, PEAK CURRENT (A)

DM

I

VGS = -20V

VGS = -10V

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

-1

-5

10

-4

10

TA = 25oC

-3

10

t, PULSE WIDTH (s)

FOR TEMPERATURES ABOVE 25 CURRENT AS FOLLOWS:

I = I

-2

10

25

10

FIGURE 24. FORWARD BIAS SAFE OPERATING AREA FIGURE 25. PEAK CURRENT CAPABILITY

-15 If R = 0 tAV = (L)(IAS)/(1.3*RATED BV

-10

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

- VDD)

DSS

STARTING TJ = 25oC

- VDD) +1]

-20

-16

-12

VGS = -20V

VGS = -10V

VGS = -8V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VGS = -7V

VGS = -6V

o

C DERATE PEAK

150 - T

A

125

-1

0

10

T

= 25oC

A

VGS = -5V

1

10

STARTING TJ = 150oC

, AVALANCHE CURRENT (A)

AS

I

-1

0.1

1 10 100

tAV, TIME IN AVALANCHE (ms)

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 26. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

-20

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX V

= -15V

DD

-16

-12

-8

-4

, ON-STATE DRAIN CURRENT (A)

D(ON)

I

0

0 -4-6-8-10-2

VGS, GATE TO SOURCE VOLTAGE (V)

-55oC

25oC

150oC

-8

, DRAIN CURRENT (A)

D

I

-4

0

0 -1.5 -3.0 -4.5 -6.0 -7.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = -4.5V

FIGURE 27. SATURATION CHARACTERISTICS

500

400

300

200

, DRAIN TO SOURCE

ON RESISTANCE (mΩ)

100

DS(ON)

r

ID = -0.625A

0

-2

ID = -5.0A I

D

ID = -1.25A

VGS, GATE TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

= -2.5A

-6-4

-8 -10

VDD= -15V

FIGURE 28. TRANSFER CHARACTERISTICS FIGURE 29. DRAIN TO SOURCE ON RESISTANCEvs GATE

VOLTAGE AND DRAIN CURRENT

9-23

RF1K49224

Typical Performance Curves (P-Channel)

2.0

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX V

= -10V, ID = -2.5A

GS

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

FIGURE 30. NORMALIZED DRAIN TOSOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

1.2 ID = -250µA

1.1

1.0

(Continued)

1.2

1.0

0.8

NORMALIZED GATE

0.6

THRESHOLD VOLTAGE

0.4

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = -250µA

FIGURE 31. NORMALIZED GATE THRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

750

C

ISS

600

VGS = 0V, f = 1MHz

= CGS + C

C

450

300

C

OSS

ISS

C

RSS

C

OSS

= C = CDS + C

GD

0.9

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.8

-80 -40 0 40 80 120 160 T

, JUNCTION TEMPERATURE (oC)

J

FIGURE 32. NORMALIZEDDRAINTO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

-30.0

-22.5

-15.0

-7.5

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

VDD = BV

0

DSS

RL = 12Ω I

VGS = -10V

PLATEAU VOLTAGES IN DESCENDING ORDER:

I

g REF()

20

----------------------- I

g ACT()

= -0.26mA

g(REF)

VDD = BV VDD = 0.75 BV VDD = 0.50 BV VDD = 0.25 BV

DSS

t, TIME (µs)

C, CAPACITANCE (pF)

150

0

0 -5 -10 -15 -20

C

RSS

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 33. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

-10.0

DSS DSS DSS

VDD = BV

80

DSS

I

g REF()

-------------------- -

I

g ACT()

-7.5

-5.0

-2.5

0

, GATE TO SOURCE VOLTAGE (V)

GS

V

-25

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 34. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT

9-24

RF1K49224

Test Circuits and Waveforms (P-Channel)

V

DS

VARY t

TO OBTAIN

P

REQUIRED PEAK I

0V V

GS

t

P

AS

L

R

G

-

V

DD

+

DUT

I

AS

0.01Ω

0

V

DD

I

AS

t

P

FIGURE 35. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 36. UNCLAMPED ENERGY WAVEFORMS

BV

t

AV

DSS

V

DS

t

ON

t

d(ON)

t

R

L

V

GS

V

GS

R

GS

DS

DUT

-

V

DD

+

0

V

DS

V

GS

0

10%

r

10%

90%

50%

PULSE WIDTH

FIGURE 37. SWITCHING TIME TEST CIRCUIT FIGURE 38. RESISTIVE SWITCHING WAVEFORMS

V

I

g(REF)

DS

R

L

0

VGS= -2V

V

GS

DUT

V

DD

+

V

0

I

g(REF)

-V

DD

GS

Q

g(TH)

Q

g(-10)

Q

g(TOT)

VGS= -10V

t

d(OFF)

V

DS

t

OFF

50%

90%

t

f

10%

VGS= -20V

FIGURE 39. GATE CHARGE TEST CIRCUIT FIGURE 40. GATE CHARGE WAVEFORMS

9-25

RF1K49224

Soldering Precautions

The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected.

1. Always preheat the device.

2. Thedeltatemperature betweenthepreheatandsoldering should always be less than 100 device can result in excessive thermal stress which can damage the device.

o

C.Failuretopreheat the

3. Themaximumtemperaturegradientshouldbeless than5 per second when changing from preheating to soldering.

4. The peak temperatureinthesolderingprocessshouldbe at least 30oC higher than the melting point of the solder chosen.

5. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device.

6. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperaturegradientand may result in latent failure due to mechanical stress.

7. During cooling, mechanical stress or shock should be avoided.

o

C

9-26

RF1K49224

PSPICE Electrical Model (N-Channel)

SUBCKT RF1K49224 2 1 3 ; N-Channel Model rev 12/15/94

CA 12 8 1.75e-9 CB 15 14 1.80e-9 CIN 6 8 1.20e-9

DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 33.29 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1

IT 8 17 1

GATE

LDRAIN 2 5 1e-9 LGATE 1 9 1.233e-9 LSOURCE 3 7 0.452e-9

MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01

9

1

LGATE

20

RGATE

EVTO

+

ESG

18

8

10

6 8

+

RIN

DPLCAP

6

VTO

+

CIN

16

5

RDRAIN

MOS1

DRAIN

LDRAIN

DBREAK

11

+

7

DBODY

LSOURCE

EBREAK

8

MOS2

RSOURCE

21

17

18

2

3 SOURCE

RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 1e-4 RGATE 9 20 1.83 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 13.5e-3 RVTO 18 19 RVTOMOD 1

S1A 6 12 13 8 S1AMOD

S1A

12

13814

S1B

CA

EGS

S2A

15

13

S2B

13

CB

14

EDS

+

5 8

+

6 8

RBREAK

17

IT

S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1 VTO 21 6 0.1

.MODEL DBDMOD D (IS = 2.50e-13 RS = 1.35e-2 TRS1 = 4.31e-5 TRS2 = 2.15e-5 CJO = 9.33e-10 TT = 2.08e-8) .MODEL DBKMOD D (RS = 1.14 TRS1 = 2.23e-3 TRS2 = -8.91e-6) .MODEL DPLCAPMOD D (CJO = 7.99e-10 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 2.15 KP = 6.25 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.74e-4 TC2 = 1.13e-6) .MODEL RDSMOD RES (TC1 = 4.5e-3 TC2 = -7.45e-7) .MODEL RVTOMOD RES (TC1 = -4.16e-3 TC2 = 2.16e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.15 VOFF= -5.15) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.15 VOFF= -7.15) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.6 VOFF= 2.4) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.4 VOFF= -2.6)

.ENDS

18

RVTO

19

VBAT

+

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.

9-27

RF1K49224

PSPICE Electrical Model (P-Channel)

SUBCKT RF1K49224 2 1 3 ; P-Channel Model rev 4/7/97

CA 12 8 7.29e-10 CB 15 14 5.01e-10 CIN 6 8 5.55e-10

DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DPLCAP 10 6 DPLCAPMOD

EBREAK 5 11 17 18 -35.46 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTHRES 6 21 19 8 1 EVTEMP 6 20 18 22 1

IT 8 17 1

GATE

1

LDRAIN 2 5 1e-9 LGATE 1 9 1.27e-9 LSOURCE 3 7 4.20e-10

MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 19.3e-3 RGATE 9 20 7.44 RLDRAIN 2 5 10 RLGATE 1 9 12.7 RLSOURCE 3 7 4.2 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 65.37e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1

LGATE

RLGATE

RGATE

9

CA

DPLCAP

EVTEMP

-

18 22

20

S1A

12

13

S1B

EGS EDS

ESG

10

8

8 6

RSLC2

EVTHRES

+

6

+

S2A

14 13

S2B

13

+

6 8

-

5

+-

RSLC1

51

+

5

ESLC

51

-

50 RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

+

8

14

5 8

-

EBREAK

MWEAK

MMED

DBREAK

RSOURCE

17 18

IT

8

17 18

RBREAK

RVTHRES

S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*48),2.5))} .MODEL DBODYMOD D (IS = 3.30e-13 RS = 4.56e-2 TRS1 =6.98e-4 TRS2 =8.08e-7 CJO = 8.21e-10 TT = 3.51e-8 M=0.4)

.MODEL DBREAKMOD D (RS = 8.18e-1 TRS1 =5.28e-3 TRS2 = -7.18e-5 .MODEL DPLCAPMOD D (CJO = 2.52e-10 IS = 1e-30 N = 10 M=0.6) .MODEL MMEDMOD PMOS (VTO= -1.95 KP=0.75 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=7.44) .MODEL MSTROMOD PMOS (VTO= -2.44 KP= 7.25 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MWEAKMOD PMOS (VTO= -1.68 KP=0.045 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=74.4 RS=0.1) .MODEL RBREAKMOD RES (TC1 = 9.45e-4 TC2 = -1.01e-7) .MODEL RDRAINMOD RES (TC1 = 3.69e-3 TC2 = 5.90e-6) .MODEL RSLCMOD RES (TC1=3.46e-3 TC2= 1.26e-6) .MODEL RSOURCEMOD RES (TC1=3.69e-3 TC2=5.90e-6) .MODEL RVTHRESMOD RES (TC=-5.19e-4 TC2= 5.02e-6) .MODEL RVTEMPMOD RES (TC1 = -3.54e-3 TC2 = -6.53e-7)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 6.94 VOFF= 3.94) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.94 VOFF= 6.94) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.40 VOFF= -2.60) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.60 VOFF= 0.40)

.ENDS NOTE:For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options;IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

LDRAIN

RLDRAIN

+

-

DBODY

11

LSOURCE

7

RLSOURCE

RVTEMP 19

-

VBAT

+

22

DRAIN

2

SOURCE

3

9-28

PSpice Thermal Model

REV 28 Feb 97

RF1K49224

CTHERM1 7 6 1.00e-7 CTHERM2 6 5 9.00e-4 CTHERM3 5 4 3.00e-3 CTHERM4 4 3 4.00e-2 CTHERM5 3 2 5.20e-3 CTHERM6 2 1 1.90e-2

RTHERM1 7 6 7.10e-2 RTHERM2 6 5 1.90e-1 RTHERM3 5 4 5.95e-1 RTHERM4 4 3 4.27 RTHERM5 3 2 1.2e1 RTHERM6 2 1 1.04e2

RF1K49224

RTHERM1

RTHERM2

JUNCTION

7

CTHERM1

6

CTHERM2

5

RTHERM3

RTHERM4

RTHERM5

RTHERM6

CTHERM3

4

CTHERM4

3

CTHERM5

2

CTHERM6

CASE

1

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

9-29