These P-Channel power MOSFETs are manufacturedusing
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. These transistors can be operated
directly from integrated circuits.
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
-30V
-30V
±20V
60
Figure 6
176
1.17
-55 to 175
300
260
A
W
W/oC
o
C
o
C
o
C
NOTE:
1. TJ = 25oC to 150oC.
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Drain to Source Breakdown VoltageBV
Gate Threshold VoltageV
GS(TH)VGS
Zero Gate Voltage Drain CurrentI
Gate to Source Leakage CurrentI
Drain to Source On Resistance (Note 2)r
DS(ON)ID
Turn-On Timet
Turn-On Delay Timet
d(ON)
Rise Timet
Turn-Off Delay Timet
d(OFF)
Fall Timet
Turn-Off Timet
Total Gate ChargeQ
g(TOT)VGS
Gate Charge at 10VQ
Threshold Gate ChargeQ
Input CapacitanceC
Output CapacitanceC
Reverse Transfer CapacitanceC
Thermal Resistance, Junction to CaseR
Thermal Resistance, Junction to AmbientR
DSSID
DSS
GSS
ON
r
f
OFF
g(-10)VGS
g(TH)VGS
ISS
OSS
RSS
θJC
θJA
= 250µA, VGS = 0V (Figure 11)-30--V
= VDS, ID = 250µA (Figure 10)-2--4V
VDS = Rated BV
VDS = 0.8 x Rated BV
, VGS = 0V---1µA
DSS
, TC = 150oC---50µA
DSS
VGS = ±20V--±100nA
= 60A, VGS = 10V--0.027Ω
VDD = 15V, I
VGS = -10V, RG = 2.5Ω,
(Figure 13)
≈ 60A, R
D
= 0.25Ω,
L
--140ns
-20-ns
-75-ns
-35-ns
-40-ns
--115ns
= 0 to -20VVDD = -24V, ID≈ 60A,
= 0 to -10V-100120nC
= 0 to -2V-7.59nC
NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring GlobalTemperature Options; authors, William J. Hepp and C. Frank Wheatley.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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