Datasheet RF1S60P03SM, RFP60P03 Datasheet (Intersil)

Page 1
RFG60P03, RFP60P03, RF1S60P03SM
Data Sheet July 1999
These P-Channel power MOSFETs are manufacturedusing the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits.
Formerly developmental type TA49045.
Ordering Information
PART NUMBER PACKAGE BRAND
RFG60P03 TO-247 RFG60P03 RFP60P03 TO-220AB RFP60P03 RF1S60P03SM TO-263AB F1S60P03
NOTE: When ordering,use theentirepart number. Add the suffix 9Ato obtain the TO-263AB variant in tape and reel, i.e. RF1S60P03SM9A.
File Number
Features
• 60A, 30V
DS(ON)
= 0.027
®
Model
•r
• Temperature Compensating PSPICE
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
o
C Operating Temperature
• 175
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”
Symbol
D
G
S
3951.3
Packaging
DRAIN
(BOTTOM
SIDE METAL)
JEDEC STYLE TO-247 JEDEC TO-220AB
SOURCE
DRAIN
GATE
JEDEC TO-263AB
GATE SOURCE
DRAIN
(FLANGE)
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
4-140
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
Page 2
RFG60P03, RFP60P03, RF1S60P03SM
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
C
RFG60P03, RFP60P03, RFS60P03SM UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Drain to Gate Voltage, (Rgs = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Continuous Drain Current (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
DSS
DGR
GS
DM
AS
D
Refer to Peak Current Curve
D
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ,T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
-30 V
-30 V
±20 V
60
Figure 6
176
1.17
-55 to 175
300 260
A
W
W/oC
o
C
o
C
o
C
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV Gate Threshold Voltage V
GS(TH)VGS
Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I Drain to Source On Resistance (Note 2) r
DS(ON)ID
Turn-On Time t Turn-On Delay Time t
d(ON)
Rise Time t Turn-Off Delay Time t
d(OFF)
Fall Time t Turn-Off Time t Total Gate Charge Q
g(TOT)VGS
Gate Charge at 10V Q Threshold Gate Charge Q Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Thermal Resistance, Junction to Case R Thermal Resistance, Junction to Ambient R
DSSID
DSS
GSS
ON
r
f
OFF
g(-10)VGS g(TH)VGS
ISS OSS RSS
θJC
θJA
= 250µA, VGS = 0V (Figure 11) -30 - - V
= VDS, ID = 250µA (Figure 10) -2 - -4 V VDS = Rated BV VDS = 0.8 x Rated BV
, VGS = 0V - - -1 µA
DSS
, TC = 150oC - - -50 µA
DSS
VGS = ±20V - - ±100 nA
= 60A, VGS = 10V - - 0.027
VDD = 15V, I VGS = -10V, RG = 2.5Ω, (Figure 13)
60A, R
D
= 0.25,
L
- - 140 ns
-20-ns
-75-ns
-35-ns
-40-ns
- - 115 ns = 0 to -20V VDD = -24V, ID≈ 60A, = 0 to -10V - 100 120 nC = 0 to -2V - 7.5 9 nC
RL = 0.4 I
= -3mA
g(REF)
VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)
- 190 230 nC
- 3000 - pF
- 1500 - pF
- 525 - pF
(Figure 3) - - 0.85oC/W TO-220AB, TO- 263AB - - 62 TO-247 - - 30
o o
C/W C/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage (Note 2) V Diode Reverse Recovery Time t
SD
rr
NOTE:
2. Pulse test: pulse width 300µs, duty cycle 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3)
4-141
ISD = -60A - - -1.75 V ISD = -60A, dISD/dt = 100A/µs - - 200 ns
Page 3
RFG60P03, RFP60P03, RF1S60P03SM
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 125 150 175
TC, CASE TEMPERATURE (oC)
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
1
-70
-60
-50
-40
-30
-20
, DRAIN CURRENT (A)
D
I
-10
0
25 50 75 100 125 150 175
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
0.5
0.2
0.1
THERMAL IMPEDANCE
0.01 10
-5
0.1
0.05
0.02
0.01 SINGLE PULSE
-4
10
NORMALIZED
JC,
θ
Z
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-500
-100
OPERATION IN THIS
-10
AREA MAY BE
, DRAIN CURRENT (A)
D
I
LIMITED BY r TC = 25oC
= MAX RATED
T
J
-1
-1 -10 -60
DS(ON)
, DRAIN TO SOURCE VOLTAGE (V)
V
DS
-3
10
t, RECTANGULAR PULSE DURATION (s)
100µs
1ms
10ms
100ms DC
-2
10
3
-10
, PEAK CURRENT (A)
2
DM
-10
I
-50 10
-1
10
TC = 25oC
VGS = -20V
VGS = -10V
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
-6
-5
10
10
P
DM
t
1
t
2
NOTES: DUTY FACTOR: D = t
PEAK TJ = PDM x Z
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS:
-4
-3
10
t, PULSE WIDTH (ms)
1/t2
x R
JC
θ
0
10
175 TC–

II
=
----------------------- -

25
150

-2
10
10
JC
θ
-1
+ T
10
C
1
10
0
1
10
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
4-142
Page 4
RFG60P03, RFP60P03, RF1S60P03SM
Typical Performance Curves
-200
-100
STARTING TJ = 150oC
If R = 0
, AVALANCHE CURRENT (A)
AS
I
= (L) (IAS) / (1.3RATED BV
t
AV
If R 0 t
= (L/R) ln [(IAS*R) / (1.3 RATED BV
AV
-10
0.01 0.1 1 10 t
, TIME IN AVALANCHE (ms)
AV
DSS
Unless Otherwise Specified (Continued)
STARTING TJ = 25oC
- VDD)
- VDD) + 1]
DSS
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
-120
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = -15V
-90
-55oC
25oC
-120 VGS = -20V
-90
-60
, DRAIN CURRENT (A)
-30
D
I
0
0 -1.5 -3.0 -4.5 -6.0 -7.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = -10V
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC
VGS = -4.5V
VGS = -8V
VGS = -7V VGS = -6V
VGS = -5V
FIGURE 7. SATURATION CHARACTERISTICS
2
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS= 1.5V, ID = 60A
1.5
175oC
-60
-30
, DRAIN TO SOURCE CURRENT (A)
DS(ON)
I
0
0 -2 -4 -6 -8 -10
V
, GATE TO SOURCE VOLTAGE (V)
GS
1
ON RESISTANCE
0.5
NORMALIZED DRAIN TO SOURCE
0
-80 -40 0 40 80 120 160 200 , JUNCTION TEMPERATURE (oC)
T
J
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TOSOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2
VGS = VDS, ID = 250µA
1.5
1
NORMALIZED GATE
0.5
THRESHOLD VOLTAGE
0
-80 -40 0 40 80 160120 200 TJ, JUNCTION TEMPERATURE (oC)
2
ID = 250µA
1.5
1
0.5
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
0
-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGEvs
JUNCTION TEMPERATURE
4-143
FIGURE 11. NORMALIZED DRAIN TOSOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Page 5
RFG60P03, RFP60P03, RF1S60P03SM
Typical Performance Curves
Unless Otherwise Specified (Continued)
5000
VGS = 0V, f = 1MHz
4000
ISS
C
= C
RSS
C
C
ISS
OSS
C
GD
DS
+ C
GD
GS
= CGS + C
C
3000
C
OSS
2000
C, CAPACITANCE (pF)
1000
C
RSS
0
0
-5 -10 -15 -20 -25 VDS, DRAIN TO SOURCE VOLTAGE(V)
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
V
DS
L
-30
-22.5
VDD = BV
DSS
VDD = BV
DSS
-10
-7.5
RL = 0.5
-15
-7.5
0.75 BV
0.50 BV
0.25 BV
G(REF)
V
GS
DSS DSS DSS
= -10V
0.75 BV
0.50 BV
0.25 BV
DSS DSS DSS
-5.0
-2.5
= -3mA
I
, DRAIN TO SOURCE VOLTAGE (V)
DS
V
0
I
20
G(REF)
I
G(ACT)
t, TIME (µs)
80
I
G(REF)
I
G(ACT)
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZED SWITCHING WAVEFORMSFOR
CONSTANT GATE CURRENT
t
AV
0
, GATE TO SOURCE VOLTAGE (V)
GS
V
VARY t
TO OBTAIN
P
REQUIRED PEAK I
0V V
GS
t
P
AS
R
G
DUT
I
AS
0.01
-
V
DD
+
V
DD
I
AS
t
P
BV
DSS
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORM
t
ON
t
d(ON)
10%
50%
t
r
90%
10%
V
DS
R
L
V
GS
-
V
DD
V
GS
R
GS
DUT
+
0
V
DS
V
GS
0
PULSE WIDTH
t
d(OFF)
V
DS
t
90%
OFF
90%
50%
t
f
10%
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
4-144
Page 6
RFG60P03, RFP60P03, RF1S60P03SM
Test Circuits and Waveforms
V
DS
V
GS
I
G(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
(Continued)
R
L
DUT
V
Q
GS
g(TH)
Q
g(-10)
Q
g(TOT)
0
VGS= -2V
­V
DD
+
V
0
I
G(REF)
-V
DD
DS
VGS= -10V
VGS= -20V
4-145
Page 7
RFG60P03, RFP60P03, RF1S60P03SM
PSPICE Electrical Model
.SUBCKT RFP60P03 2 1 3 REV 6/21/94
CA 12 8 5.01e-9 CB 15 14 3.9e-9 CIN 6 8 3.09e-9
DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 6 DPLCAPMOD
EBREAK 5 11 17 18 -36.59 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTO 20 6 8 18 1
IT 8 17 1
LDRAIN 2 5 1e-9 LGATE 1 9 4.92e-9 LSOURCE 3 7 2.36e-9
MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01
RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 1e-4 RGATE 9 20 3.25 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 11.28e-3 RVTO 18 19 RVTOMOD 1
S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD
GATE
1
LGATE
209
RGATE
10
DPLCAP
EVTO
+
18
8
S1A S2A
12
13
8
CA
EGS EDS
5
+
-
6 8
ESG
RDRAIN
EBREAK
16
VTO
+
-
6
RIN
+
-
14 13
6 8
CIN
15
S2BS1B
13
CB
21
MOS1
14
+
5 8
-
8
MOS2
DBREAK
RSOURCE
17 18
11
17 18
+
-
LSOURCE
7
RBREAK
IT
LDRAIN
DBODY
RVTO
19
VBAT
+
DRAIN 2
3
SOURCE
VBAT 8 19 DC 1 VTO 21 6 -0.92
.MODEL DBDMOD D (IS=4.21e-13 RS=1e-2 TRS1=-2.69e-4 TRS2=-1.33e-6 CJO=5.05e-9 TT=5.33e-8) .MODEL DBKMOD D (RS=3.80e-2 TRS1=-4.76e-4 TRS2=-4.17e-12) .MODEL DPLCAPMOD D (CJO=4.05e-9 IS=1e-30 N=10) .MODEL MOSMOD PMOS (VTO=-3.98 KP=16.27 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=8.05e-4 TC2=1.48e-6) .MODEL RDSMOD RES (TC1=2.80e-3 TC2=2.62e-6) .MODEL RVTOMOD RES (TC1=-3.34e-3 TC2=1.46e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=7.5 VOFF=4.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.5 VOFF=7.5) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.43 VOFF=-3.57) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.57 VOFF=1.43)
.ENDS
NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; authors, William J. Hepp and C. Frank Wheatley.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
4-146
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