Datasheet RF1S45N06SM, RFG45N06 Datasheet (Intersil)

RFG45N06, RFP45N06, RF1S45N06SM

Data Sheet July 1999 File Number

45A, 60V, 0.028 Ohm, N-Channel Power
MOSFETs

These are N-Channel enhancement mode silicon gate
power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a
specified level of energy in the breakdown avalanche mode
of operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching
convertors, motor drivers, relay drivers, and drivers for high
power bipolar switching transistors requiring high speed and
low gate drive power. These types can be operated directly
from integrated circuits.

Formerly developmental type TA49028.

Ordering Information

PART NUMBER PACKAGE BRAND

RFG45N06 TO-247 RFG45N06
RFP45N06 TO-220AB RFP45N06
RF1S45N06SM TO-263AB F1S45N06

NOTE: When ordering, use the entire part number. Addthesuffix,9A,
to obtain the TO-263AB variant in tape and reel, i.e.RF1S45N06SM9A.

Features

• 45A, 60V

DS(ON)

= 0.028Ω

®

Model

•r

• Temperature Compensating PSPICE

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

• 175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

DRAIN

GATE

SOURCE

3574.4

Packaging

DRAIN

(BOTTOM

SIDE METAL)

JEDEC STYLE TO-247 JEDEC TO-220AB

SOURCE

DRAIN

GATE

JEDEC TO-263AB

GATE
SOURCE

DRAIN

(FLANGE)

DRAIN

(FLANGE)

SOURCE

DRAIN

GATE

4-455

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFG45N06, RFP45N06, RF1S45N06SM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFG45N06, RFP45N06

RF1S45N06SM UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RG = 20KΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

DSS

DGR

DM

GS

AS

D

Refer to Peak Current Curve

D

Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

60 V
60 V
45

±20 V

Refer to UIS Curve

131

0.877

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 150oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain Source On Resistance (Note 2) r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)VGS

Gate Charge at 10V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

DSSID

DSS

GSS

ON

r

f

OFF

g(10)

g(TH)

ISS
OSS
RSS

θJC

θJA

= 250µA, VGS = 0V (Figure 11) 60 - - V

= VDS, ID = 250µA (Figure 10) 2 - 4 V
VDS = Rated BV
VDS = 0.8 x Rated BV

, VGS = 0V - - 1 µA

DSS

, VGS = 0V (125oC) - - 25 µA

DSS

VGS = ±20V - - ±100 nA

= 45A, VGS = 10V (Figure 9) - - 0.028 Ω

VDD = 30V, ID = 45A
RL = 0.667Ω, VGS = +10V
RG = 3.6Ω (Figure 13)

- - 120 ns

-12- ns

-74- ns

-37- ns

-16- ns

- - 80 ns

= 0 to 20V VDD = 48V, ID = 45A,
VGS = 0 to 10V - 67 80 nC
VGS = 0 to 2V - 3.7 4.5 nC

RL = 1.07Ω
I

= 1.5mA

g(REF)

(Figure 13)

VDS = 25V, VGS = 0V
f = 1MHz (Figure 12)

- 125 150 nC

- 2050 - pF

- 600 - pF

- 200 - pF

- - 1.14

o

C/W

--80oC/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Diode Reverse Recovery Time t

SD

rr

NOTES:

2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current
Capability Curve (Figure 5).

4-456

ISD = 45A - - 1.5 V
ISD = 45A, dISD/dt = 100A/µs - - 125 ns

RFG45N06, RFP45N06, RF1S45N06SM

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 125 150 175

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TEMPERATURE

1

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

25 50 75 100 125 150 175

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

0.5

0.2

0.1

0.1

0.05

0.02

THERMAL IMPEDANCE

, NORMALIZED TRANSIENT

JC

θ

Z

0.01

0.01
SINGLE PULSE

-5

10

-4

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

400

100

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

1 10 100

DS(ON)

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

DSS(MAX)

T

= MAX RATED

J

SINGLE PULSE

= 60V

-3

10

t, RECTANGULAR PULSE DURATION (s)

TC = 25oC

100µs

1ms

10ms

100ms

DC

-2

10

3

10

VGS = 20V

, PEAK CURRENT (A)

2

10

DM

I

40

10-310

NOTES:
DUTY FACTOR: D = t1/t

PEAK TJ = PDM x Z

-1

10

VGS = 10V

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-2

-1

10

t, PULSE WIDTH (ms)

P

DM

t

1

t

2

2

x R

JC

θ

175 TC–

----------------------- ­150

2

10

+ T

C

TC = 25oC

3

10

JC

θ

0

10

FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:



II

=



25



0

10

1

10

1

10

4

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

4-457

RFG45N06, RFP45N06, RF1S45N06SM

Typical Performance Curves

300

100

STARTING TJ = 150oC

10

If R = 0

AVALANCHE CURRENT (A)

tAV = (L) (IAS) / (1.3 RATED BV

AS,

I

If R ≠ 0

= (L/R) ln [(IAS*R) / (1.3 RATED BV

t

AV

1

0.01 0.1 1 10

STARTING TJ = 25oC

DSS

TIME IN AVALANCHE (ms)

t

AV,

Unless Otherwise Specified (Continued)

- VDD)

- VDD) + 1]

DSS

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

125

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V

100

-55

o

25oC

C

175oC

125

100

75

50

, DRAIN CURRENT (A)

D

I

25

0

0 1.5 3 4.5 6 7.5

VGS = 10V

V

DRAIN TO SOURCE VOLTAGE (V)

DS,

VGS = 8V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VGS = 7V

T

C

VGS = 6V

VGS = 5V

VGS = 4.5V

FIGURE 7. SATURATION CHARACTERISTICS

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5%MAX
VGS= 10V, ID = 45A

2

= 25oC

75

50

25

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

0

I

012345678910

, GATE TO SOURCE VOLTAGE (V)

V

GS

1.5

1

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
TJ,JUNCTION TEMPERATURE (oC)

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

2.0
VGS = VDS, ID = 250µA

1.5

1.0

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80 -40 0 40 80 160120 200
TJ,JUNCTION TEMPERATURE (oC)

2.0
ID = 250µA

1.5

1.0

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
TJ,JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

4-458

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

RFG45N06, RFP45N06, RF1S45N06SM

Typical Performance Curves

Unless Otherwise Specified (Continued)

4000

VGS = 0V, f = 1MHz
C

= CGS + C

3000

ISS

C

= C

RSS

C

≈ CDS + C

OSS

C

ISS

GD

GD

GD

2000

C

C

OSS

RSS

1000

C, CAPACITANCE (pF)

0

0 5 10 15 20 25

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

Test Circuits and Waveforms

V

DS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

DUT

+

-

60

45

30

15

DRAIN TO SOURCE VOLTAGE (V)

DS,

V

0

VDD = BV

I

G(REF)

20

I

G(ACT)

DSS

0.75 BV

0.50 BV

0.25 BV

DSS
DSS
DSS

RL = 1.33Ω

= 1.5mA

I

G(REF)

V

= 10V

GS

t, TIME (µs)

0.75 BV

0.50 BV

0.25 BV

VDD = BV

DSS
DSS
DSS

80

DSS

I

G(REF)

I

G(ACT)

10

7.5

5.0

2.5

0

GATE TO SOURCE VOLTAGE (V)

GS,

V

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

BV

DSS

t

P

I

AS

V

DD

V

DS

V

DD

0V

P

I

AS

0.01Ω

0

t

AV

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

d(ON)

t

R

L

+

V

R

G

DD

-

V

DS

90%

0

r

10%

DUT

V

GS

V

GS

10%

0

50%

PULSE WIDTH

t

d(OFF)

90%

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

t

OFF

50%

t

f

90%

10%

4-459

RFG45N06, RFP45N06, RF1S45N06SM

Test Circuits and Waveforms

V

DS

V

GS

I

g(REF)

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS

DUT

V

R

L

+

V

DD

-

DD

VGS= 2V

0

I

g(REF)

0

Q

V

GS

Q

g(TH)

V

DS

g(10)

Q

g(TOT)

VGS= 20V

VGS = 10V

4-460

PSPICE Electrical Model

.SUBCKT RFP45N06213
REV 1/18/93

*NOM TEMP = +25

o

C

RFG45N06, RFP45N06, RF1S45N06SM

CA 12 8 3.49E-9
CB 15 14 3.8E-9
CIN 6 8 2E-9

DBODY 7 5 DBDMOD
DBREAK 5 11DBKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 66.5
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1

IT 8 17 1

LDRAIN 2 5 1E-9
LGATE 1 9 5.65E-9
LSOURCE 3 7 4.13E-9

MOS1 16 6 8 8 MOSMOD M=0.99
MOS2 16 21 8 8 MOSMOD M=0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 3.58E-3
RGATE 9 20 0.681
RIN 6 8 1E9
RSOURCE 8 7 RDSMOD 13.6E-3
RVTO 18 19 RVTOMOD 1

GATE
1

LGATE

RGATE

ESG

EVTO

+

209

S1A S2A

12

10

-

+

-

18

8

13

8

DPLCAP

6
8

+

-

VTO

-

6

RIN CIN

15

14
13

S2BS1B
13

6

EDSEGS

8

5

RDRAIN

16
+

MOS1

CBCA

14

+

5
8

-

DBREAK

8

MOS2

EBREAK

RSOURCE

11

+

17
18

-

7

RBREAK

21

DRAIN

LDRAIN

DBODY

LSOURCE

SOURCE

1817

RVTO

19IT

-

VBAT

+

2

3

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1
VTO 21 6 0.92

.MODEL DBDMOD D (IS=8.2E-13 RS=7.86E-3 TRS1=2.26E-3 TRS2=2.90E-6 CJO=2.07E-9 TT=5.72E-8)
.MODEL DBKMOD D (RS=1.93E-1 TRS1=5.13E-4 TRS2=-2.15E-5)
.MODEL DPLCAPMOD D (CJO=1.25E-9 IS=1E-30 N=10)
.MODEL MOSMOD NMOS (VTO=3.862 KP=55.57 IS=1E-30 N=10 TOX=1 L=1U W=1U)
.MODEL RBKMOD RES (TC1=1.12E-3 TC2=-5.18E-7)
.MODEL RDSMOD RES (TC1=4.64E-3 TC2=1.58E-5)
.MODEL RVTOMOD RES (TC1=-4.27E-3 TC2=-6.55E-6)
.MODEL S1AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-6.5 VOFF=-1.7)
.MODEL S1BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-1.7 VOFF=-6.5)
.MODEL S2AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-3.0 VOFF=2)
.MODEL S2BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=2.0 VOFF=-3.0)

.ENDS

NOTE: For furtherdiscussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature
Options; authors, William J. Hepp and C. Frank Wheatley.

4-461

RFG45N06, RFP45N06, RF1S45N06SM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

4-462

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]