Datasheet RF1K49221 Datasheet (Intersil)

RF1K49221

Data Sheet August 1999

2.5A, 60V, 0.130 Ohm, ESD Rated, Dual
N-Channel LittleFET™ Power MOSFET

The RF1K49221 Dual N-Channel power MOSFET is
manufactured using an advanced MegaFET process. This
process, which uses feature sizes approaching those of LSI
integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. It is designed for use
in applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low voltage bus
switches. This device can be operated directly from
integrated circuits.

The RF1K49221 incorporates ESD protection and is
designed to withstand 2kV (Human Body Model) of ESD.

Formerly developmental type TA49221.

Ordering Information

PART NUMBER PACKAGE BRAND

RF1K49221 MS-012AA RF1K49221

NOTE: When ordering, use the entire part number. For ordering in
tape and reel, add the suffix 96 to the part number, i.e.RF1K4922196.

File Number

Features

• 2.5A, 60V

DS(ON)

= 0.130Ω

•r

• 2kV ESD Protected

®

• Temperature Compensating PSPICE

Model

• Thermal Impedance PSPICE Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D1(8)
D1(7)

S1(1)

G1(2)

4314.1

Packaging

JEDEC MS-012AA

BRANDING DASH

1

2

D2(6)
D2(5)

S2(3)

G2(4)

5

3

4

8-136

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

LittleFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RF1K49221

Absolute Maximum Ratings T

= 25oC Unless Otherwise Specified

A

RF1K49221 UNITS

Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS= 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

60 V
60 V

±20 V

Drain Current

Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DM

AS

D

Refer to Peak Current Curve

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . . . . . . . ESD 2 kV

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

2.5

Refer to UIS Curve

2

0.016

-55 to 150

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Source Threshold Voltage V
Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

DSSID

GS(TH)VGS

DSS

GSS

= 250µA, VGS = 0V, (Figure 12) 60 - - V

= VDS, ID = 250µA, (Figure 11) 1 - 3 V

VDS = 60V,
VGS = 0V

TA = 25oC--1µA

TA = 150oC--50µA
VGS = ±20V, TA = 25oC--10µA
VGS = ±10V, TA = 85oC--25µA

Drain to Source On Resistance r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)VGS

Gate Charge at 10V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Ambient R

ON

r

f

OFF

g(10)

g(TH)

ISS

OSS

RSS

θJA

= 2.5A,

(Figures 9, 10)

VDD = 30V, I
RL = 12Ω, VGS = 10V,
RGS = 25Ω,
(Figure 14)

VGS = 10V - - 0.130 Ω

VGS = 4.5V - - 0.350 Ω

≅ 2.5A,

D

- - 50 ns

-10-ns

-25-ns

-68-ns

-32-ns

- - 150 ns

= 0V to 20V VDD = 48V, I
VGS = 0V to 10V - 13 16 nC
VGS = 0V to 2V - 0.8 1.0 nC

RL = 19.2Ω
I

g(REF)

(Figure 14)

VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)

D

= 1.0mA

≅ 2.5A,

-2429nC

- 365 - pF

- 140 - pF

-40-pF

Pulse Width = 1s

- - 62.5

o

C/W

Device mounted on FR-4 material

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t

8-137

SD

rr

ISD = 2.5A - - 1.25 V
ISD = 2.5A, dISD/dt = 100A/µs--58ns

Typical Performance Curves

1.2

RF1K49221

3.0

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

125

TA, AMBIENT TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWERDISSIPATION vs AMBIENT

TEMPERATURE

10

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

1

0.05

0.02

0.01

0.1

, NORMALIZED

JA

θ

Z

0.01

THERMAL IMPEDANCE

0.001

-5

10

SINGLE PULSE

-4

10

-3

10

10

t, RECTANGULAR PULSE DURATION (s)

2.5

2.0

1.5

1.0

, DRAIN CURRENT (A)

D

I

0.5

0

25

50

75 100 125 150

TA, AMBIENT TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

AMBIENT TEMPERATURE

P

DM

t

1

t

NOTES:
DUTY FACTOR: D = t1/t

PEAK TJ = PDM x Z

-2

-1

10

0

10

1

10

θ

2

2

x R

JA

+ T

JA

A

θ

2

10

3

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

50

10

1

, DRAIN CURRENT (A)

0.1

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

0.01

0.1
V

DS

TJ = MAX RATED
T

= 25oC

A

5ms

10ms

100ms

1s

DS(ON)

V

DSS(MAX)

1 10 200

= 60V

DC

100

, DRAIN TO SOURCE VOLTAGE (V)

100

VGS = 20V

VGS = 10V

10

TRANSCONDUCTANCE
MAY LIMIT CURRENT

, PEAK CURRENT (A)

IN THIS REGION

DM

I

1

-5

10

-4

10

TA = 25oC

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

I = I

-3

10

-2

10

t, PULSE WIDTH (s)

o

25

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

8-138

C DERATE PEAK

150 - T

A

125

-1

0

10

1

10

RF1K49221

Typical Performance Curves

15

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

10

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

, AVALANCHE CURRENT (A)

AS

I

STARTING TJ = 150oC

1

0.1
tAV, TIME IN AVALANCHE (ms)

1 10 100

DSS

STARTING TJ = 25oC

- VDD)

DSS

(Continued)

- VDD) +1]

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

20

PULSE TEST
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX

16

12

-55oC

25oC

150oC

= 15V

V

DD

20

VGS = 20V
VGS = 10V

16

12

8

, DRAIN CURRENT (A)

D

I

4

0

0 1.5 3.0 4.5 6.0 7.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

T

= 25oC

VGS = 8V

VGS = 7V

A

FIGURE 7. SATURATION CHARACTERISTICS

500

400

300

PULSE DURATION = 250µs, VDD= 15V
DUTY CYCLE = 0.5% MAX

I

= 5.0A

D

ID = 2.5A

ID = 1.25A

VGS = 6V

VGS = 5V

VGS = 4.5V

ID = 0.625A

8

4

, ON-STATE DRAIN CURRENT (A)

D(ON)

I

0

0468102

VGS, GATE TO SOURCE VOLTAGE (V)

200

, DRAIN TO SOURCE

ON RESISTANCE (mΩ)

100

DS(ON)

r

0

3

VGS, GATE TO SOURCE VOLTAGE (V)

6475

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

2.0

PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX

= 10V, ID = 2.5A

V

GS

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

1.2

1.0

0.8

NORMALIZED GATE

0.6

THRESHOLD VOLTAGE

0.4

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

8910

FIGURE 10. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

8-139

FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

O

SO

C

O

G

(

)

RF1K49221

Typical Performance Curves

1.2
ID = 250µA

1.1

1.0

0.9

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.8

-80

-40 0 40 80 120
, JUNCTION TEMPERATURE (oC)

T

J

(Continued)

FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

60

V
E

LTA
E V

UR

, DRAIN T

DS

V

VDD = BV

45

30

15

0

DSS

I

g REF()

20

----------------------- ­I

g ACT()

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT

500

C, CAPACITANCE (pF)

100

160

FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

RL = 24W
I

= 0.30mA

g(REF)

V

= 10V

GS

PLATEAU VOLTAGES IN
DESCENDING ORDER:

VDD = BV
VDD = 0.75 BV
VDD = 0.50 BV
VDD = 0.25 BV

DSS

t, TIME (ms)

DSS
DSS
DSS

80

C

, GATE TO SOURCE VOLTAGE (V)

GS

V

C

C

ISS

OSS

RSS

400

300

200

0

0 5 10 15 20

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

VDD = BV

I

gREF()

----------------------- ­I

gACT()

DSS

10.0

7.5

5.0

2.5

0

VGS = 0V, f = 1MHz
C

= CGS + C
C
C

ISS
RSS
OSS

= C

GD

= CDS + C

GD

GD

25

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY tP TO OBTAIN
REQUIRED PEAK I

V

GS

t

0V

P

AS

R

G

DUT

I

AS

0.01Ω

+

V

DD

-

0

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

8-140

t

P

I

AS

t

AV

V

DS

V

DD

RF1K49221

Test Circuits and Waveforms

V

GS

0V

R

GS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

V

DS

V

GS

I

G(REF)

(Continued)

R

L

DUT

R

L

DUT

t

ON

t

d(ON)

t

50%

Q

10%

g(TH)

r

PULSE WIDTH

V

DS

Q

g(10)

Q

g(TOT)

VGS= 10V

V

DS

90%

+

-

+

V

DD

-

0

V

GS

10%

0

V

DD

V

VGS= 2V

GS

t

d(OFF)

90%

t

OFF

50%

t

f

10%

VGS= 20V

90%

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

Soldering Precautions

The soldering process createsa considerablethermal stress
on any semiconductor component. The melting temperature
of solder is higher than the maximum rated temperature of
the device. The amount of time thedeviceis heatedto a high
temperature should be minimizedto assure device reliability.
Therefore, the following precautions should always be
observed in order to minimize the thermal stress to which
the devices are subjected.

1. Always preheat the device.

2. Thedelta temperaturebetweenthepreheatand soldering
should always be less than 100
device can result in excessive thermal stress which can
damage the device.

o

C.Failureto preheatthe

I

g(REF)

3. Themaximumtemperaturegradientshouldbeless than5
per second when changing from preheating to soldering.

4. The peak temperatureinthe soldering process should be
at least 30oC higher than the melting point of the solder
chosen.

5. The maximum soldering temperature and time mustnot
exceed 260oC for 10 seconds on the leads and case of
the device.

6. After soldering is complete, the device should be allowed
to cool naturally for at least three minutes, as forced cool­ing will increase the temperaturegradient and may result
in latent failure due to mechanical stress.

7. During cooling,mechanical stress or shockshould be
avoided.

o

C

8-141

RF1K49221

PSPICE Electrical Model

SUBCKT RF1K49221 2 1 3 ; rev 4/8/97

CA 12 8 5.60e-10
CB 15 14 5.30e-10
CIN 6 8 3.40e-10

7

18

RVTEMP

19

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DESD1 91 9 DESD1MOD

DPLCAP

10

5

DESD2 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 67.29
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

IT 8 17 1
LDRAIN 2 5 1e-9

LGATE 1 9 1.12e-9
LSOURCE 3 7 4.50e-10

GATE

1

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 28.58e-3
RGATE 9 20 15.34
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RLDRAIN 2 5 10
RLGATE 1 9 11.2
RLSOURCE 3 7 4.5
RSOURCE 8 7 RSOURCEMOD 28.85e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD

LGATE

RLGATE

RGATE

9

DESD1

91

DESD2

ESG

EVTEMP

+

20

S1A

12

S1B

CA

18
22

13

8

EGS

+

6
8

13

RSLC2

6

RIN

14
13

+

6
8

EVTHRES

+

19

8

S2A

15

S2B

EDS

CIN

CB

+

5
8

RSLC1

51

+

5

51

50

RDRAIN

MSTRO

14

ESLC

16

21

8

MMED

8

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17

IT

RVTHRES

11

+

17

18

S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*30),2.5))}
.MODEL DBODYMOD D (IS = 1.95e-13 RS = 2.58e-2 TRS1 = 2.00e-3 TRS2 =-4.39e-7 CJO = 5.15e-10 TT = 5.23e-8 M=0.5)

.MODEL DBREAKMOD D (RS = 6.24e-1 TRS1 =-3.03e-4 TRS2 = 4.27e-6
.MODEL DESD1MOD D (BV=32.3 TBV1=0 TBV2=0 RS=0 TRS1=0 TRS2=0
.MODEL DESD2MOD D (BV=32.5 TBV1=0 TBV2=0 RS=25 TRS1=5.18e-4 TRS2=-1.52e-6)
.MODEL DPLCAPMOD D (CJO = 1.80e-10 IS = 1e-30 N = 10 M=0.5)
.MODEL MMEDMOD NMOS (VTO=2.755 KP=0.21 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=15.34)
.MODEL MSTROMOD NMOS (VTO=3.165 KP=3.75 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MWEAKMOD NMOS (VTO=2.520 KP=0.040 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=153.4 RS=0.1)
.MODEL RBREAKMOD RES (TC1 = 1.10e-3 TC2 = -1.09e-6)
.MODEL RDRAINMOD RES (TC1 = 1.15e-2 TC2 = 4.09e-5
.MODEL RSLCMOD RES (TC1=3.03e-3 TC2=4.52e-6)
.MODEL RSOURCEMOD RES (TC1=0 TC2=0)
.MODEL RVTHRESMOD RES (TC=-7.20e-4 TC2=-7.11e-6)
.MODEL RVTEMPMOD RES (TC1 = -3.01e-3 TC2 = 1.81e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.80 VOFF= -4.80)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.80 VOFF= -7.80)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.10 VOFF= 4.10)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.10 VOFF= 1.10)

.ENDS
NOTE:For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options;IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

DRAIN

2

SOURCE

3

8-142

RF1K49221

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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8-143

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