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NTE2532
Integrated Circuit
NMOS, 32K EPROM, 300ns
Description:
The NTE2532 is a 32,768–bit, ultraviolet–light–erasable, electrically–programmable read–only
memory in a 24–Lead DIP type package. This device is fabricated using N–channel silicon–gate
technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including
program data inputs) can be directly driven by Series 74 TTL circuits without the use of external pull–
up reistors, and each output can drive one Series 74 circuit without external resistors. The data outputs are three–state for connecting mutiple devices to a common bus.
Since the NTE2532 operates from a single +5V supply (in the read mode), it is ideal for use in microprocessor systems. One other (+25V) supply is needed for programming but all programming signals
are TTL level, requiring a single 10ms pulse. For programming outside of the system, existing
EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random.
Total programming time for all bits is 41 seconds.
Features:
D Organization: 4096 x 8
D Single +5V Power Supply
D All Inputs/Outputs Fully TTL Compatible
D Static Operation (No Clocks, No Refresh)
D Max Acces/Min Cycle Time: 300ns
D 8–Bit Output for Use in Microprocessor Based Systems
D N–Channel Silicon–Gate Technology
D 3–State Output Buffers
D Low Power Dissipation:
Active – 400mW Typical
Standby – 100mW Standby
D Guaranteed DC Noise Immunity with Standard TTL Loads
D No Pull–Up Resistors Required
Absolute Maximum Ratings:
Supply Voltage (Note 2), V
Supply Voltage (Note 2), V
(TA = 0° to +70°C, Note 1 unless otherwise specified)
CC
PP
–0.3V to +7V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–0.3V to +28V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All Input Voltages (Note 1) –0.3V to +7V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage (Operating, with Respect to V
Operating Ambient Temperature Range, T
Storage Temperature Range, T
stg
) –0.3V to 7V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SS
A
0° to +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–55° to +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. Stres ses bey ond th ose l iste d u nder “ Absolute M aximum Ratings” m ay c ause p ermanent d am-
age to the device. This is a stress rating only and functional operation of the device at these
or any other conditions beyond t hose i ndicated i n t he “Recommended Operation Conditions”
section of this specification is not implied. Exposure to absolute–maximum–rated conditions
for extended periods may affect device reliability.
Note 2. Under absolute m aximum r atings, v oltage v alues a re w ith r espect t o t he m ost n egative s upply
voltage, V
(substrate).
S
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Recommended Operating Conditions:
Parameter Symbol Test Conditions Min Typ Max Unit
Supply Voltage V
V
V
High Level Input Voltage V
Low Level Input Voltage V
Read Cycle Time t
Operating Ambient Temperature T
CC
PP
SS
c(rd)
Note 3 4.75 5.0 5.25 V
Note 4 – V
CC
– 0 – V
IH
IL
2 – VCC+1 V
–0.1 – +0.8 V
300 – – ns
A
0 – 70 °C
– V
Note 3. VCC must be applied before or at the same time as VPP and removed after or at the same
time as V
. The device must not be inserted into or removed from the board when VPP is
PP
applied.
Note 4. V
can be connected to VCC directly (except in the programming mode). VCC supply current
PP
in this case would be ICC + IPP. During programming, VPP must be maintained at 2 5 V (±1V).
Electrical Characteristics:
Parameter Symbol Test Conditions Min Typ Max Unit
High Level Output Voltage V
Low Level Output Voltage V
Input Current (Leakage) I
Output Current (Leakage) I
VPP Supply Current I
VPP Supply Current (During Program Pulse) I
VCC Supply Current (Standby) I
VCC Supply Current (Active) I
(Over full range of recommended operating conditions)
OH
OL
PP1
PP2
CC1
CC2
IOH = –400µA 2.4 – – V
IOL = 2.1mA – – 0.45 V
VI = 0V to 5.25V – – ±10 µA
l
VO = 0.4V to 5.25V – – ±10 µA
O
VPP = 5.25V, PD/PGM = V
PD/PGM = V
PD/PGM = V
PD/PGM = V
IL
IH
IL
– – 12 mA
IL
– – 30 mA
– 20 –30 mA
– 80 160 mA
Capacitance: (Over recommended voltage and operating ambient temperature range, f = 1MHz,
Note 5, Note 6)
Parameter Symbol Test Conditions Min Typ Max Unit
Input Capacitance C
Output Capacitance C
VI = 0V, f = 1MHz – 4 6 pF
i
VO = 0V, f = 1MHz – 8 12 pF
o
Note 5. All typical values are at TA = +25°C and nominal voltages.
Note 6. Capacitance measurements are made on a sample basis only.
Switching Characteristics:
Parameter Symbol Test Conditions Min Typ Max Unit
Access Time from Address t
Access Time from PD/PGM t
Output Data Valid after Address Change t
Output Disable Time from PD/PGM (Note 7) t
(Over full range of recommended operating conditions, Note 5, Note 8)
a(A)
a(PR)
v(A)
dis
CL = 100pF,
1 Series 74 TTL Load,
t
≤ 20ns, tf ≤ 20ns,
tr ≤ 20ns, tf ≤ 20ns,
r
Note 8, Note 9
– – 300 ns
– – 300 ns
0 – – ns
– – 100 ns
Note 5. All typical values are at TA = +25°C and nominal voltages.
Note 7. Value calculated from 0.5V delta to measured output level
Note 8. Timing measurement reference levels: inputs 0.8V and 2V, outputs 0.65V and 2.2V.
Note 9. Common test conditions apply for t
PD/PGM
= VIL.
except during programming. For t
dis
a(A)
and t
dis
,
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Recommended Timing Requirement for Programming: (TA = +25°C, Note 8, Note 10)
Parameter Symbol Test Conditions Min Typ Max Unit
Pulse Duration, Program Pulse t
Rise Time, Program Pulse t
Fall Time, Program Pulse t
Address Setup Time t
Data Setup Time t
Setup Time for V
Address Hold Time t
Data Hold Time t
Program Pulse Hold Time t
VPP Hold Time t
PP
t
w(PR)
r(PR)
f(PR)
su(A)
su(D)
su(VPP)
h(A)
h(D)
h(PR)
h(VPP)
9 – – ms
5 – – ns
5 – – ns
2 – – µs
2 – – µs
0 – – ns
2 – – µs
2 – – µs
0 – – ns
2 – – µs
Note 8. Timing measurement reference levels: inputs 0.8V and 2V, outputs 0.65V and 2.2V.
Note10. Typical values are at nominal voltages.
Operation:
Function (Pins) Mode
Read Output Disable Power Down Start Programming Inhibit Programming
PD/PGM (20) V
VPP (21) +5V +5V +5V +25V +25V
VCC (24) +5V +5V +5V +5V +5V
Q (9 to 11, 13 to 17) Q High–Z High–Z D High–Z
IL
V
IH
V
IH
Pulsed VIH to V
IL
V
IH
Read/Out Disable
When t he o utputs o f t wo o r m ore N TE2532s a re connected o n t he s ame b us, t he o utput o f a ny particular
device in the circuit can be read with no interference from the cpmpeting outputs of the other devices.
The device whose output i s t o b e r ead s hould h ave a low–level TTL signal applied t o t he P D/PGM
pin.
Output data is accessed at pins Q1 through Q8.
Power Down
Active power dissipation can be cut by over 70% by applying a high TTL signal to the PD/PGM
pin.
In this mode all outputs are in a high–impedance state.
Erasure
Before programming, the NTE2532 is erased by exposing the chip through the transparent lid to high–
intensity ultraviolet light having a wavelength of 253.7nm (2537 angstroms). The recommended minimum exposure dose (UV intensity time exposure time) is fifteen watt–seconds per square centimeter.
Thus, a typical 12 miliwatt per square centimeter filterless UV lamp will erase the device in a minimum
of 21 minutes. The lamp should be located about 2.5 centimeters (1 inch) above the chip during erasure. After erasure, all bits are in the “1” state (assuming high–level output corresponds to logic “1”).
It should be noted that normal ambient light contains the correct wavelenght for erasure. Therefore
when using the NTE2532, th window should be covered with an opaque label.
Start Programming
After erasure (all bits in logic “1” state), logic “0’s” are programmed into the desited locations. A “0”
can be erasedonly by ultraviolet light. The programming mode is achieved when V
is 25V. Data is
PP
presented in parallel (8 bits) on pins Q1 through Q8. Once addresses and data are stable, a 10–millisecond TTL low–level pulse should be applied the the PGM
pin at each address location to be programmed. Maximum pulse width is 44 milliseconds. Locations can be programmed in any order. Several NTE2532s can be programmed simultaneously when the devices are connected in parallel.
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Inhibit Programming
When two or more devices are connected in parallel, data can be programmed into all devices or only
chosen devices. Any NTE2532 not intended to be programmed should have a high level applied to
PD/PGM
.
Programming Verification
The NTE2532 program verification is simply the read operation, which can be performed as soon as
returns to +5V ending the program cycle.
V
PP
Pin Connection Diagram
A7
1
A6
2
3
A5
4
A4
5A3
6A2
7
A1
8A0
9
Q1
10
Q2
11
Q3
12 13
V
SS
24
V
CC
23
A8
22
A9
21
V
PP
20
PD/PGM
19 A10
18
A11
17
Q8
16
Q7
Q6
15
14
Q5
Q4
1.290 (32.76) Max
.600 (15.24) Max Glass
24 13
.520
(13.2)
112
.280 (7.11) Dia UV Window
Glass Sealant
.160 (4.06) Max
.200 (5.08)
Max
.100 (2.54)
.125
(3.17)
.670 (17.02)
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