Datasheet NTE2053 Datasheet (NTE)

NTE2053

Integrated Circuit

8–Bit MPU Compatible A/D Converter

Description:

The NT E2053 i s a C MOS 8–bi t s uccessive appr oximation Analog t o D igi tal converter i n a 2 0–Lead DIP
type p ackage w hich uses a d if ferential potentiometr ic l adder – s imilar t o t he 256R products. T his d evice
is d esigned t o a llow o perati on w i th the N SC800 a nd I NS8080A d erivative c ontrol b us, a nd T RI–STA TE
output latches d i rectly d rive t he d ata b us. These A/Ds a ppear l ike memory locations o r I /O p orts t o t he
microprocessor and no interfacing logic is needed.

A new differential analog voltage input allows increasing the common–mode rejection and offsetting
the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow
encoding any similar analog voltage span to the full 8 bits of resolution.

Features:

D Compatible With 8080 MPU Derivatives – No Interfacing Logic Needed – Access Time: 135ns
D Easy Interface to all Microprocessors, or Operates “Stand Alone”
D Differential Analog Voltage Inputs
D Logic Inputs and Outputs Meet Both MOS and TTL Voltage Level Specifications
D Works With 2.5V (NTE952) Voltage Reference
D On–Chip Clock Generator
D 0V to 5V Analog Input Voltage Range with Single 5V Supply
D No Zero Adjust Required
D Operates Ratiometrically or with 5V, 2.5V, or Analog Span Adjusts Voltage Reference

R

Absolute Maximum Ratings: (Note 1, Note 2)
Supply Voltage (Note 3), V

CC

6.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage at Logic Control Inputs –0.3V to +18V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage at All Other Inputs and Outputs –0.3V to VCC +0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage Temperature Range, T
Power Dissipation (TA = +25°C), P

stg

D

Lead Temperature (During Soldering, 10sec), T

L

–65° to +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

875mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions: (Note 1, Note 2)
Operating Temperature Range, T
Supply Voltage Range, V

CC

A

0° to +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5V to 6.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Note 1. Absolute Maximum Ratings are those values beyond which the life of the device may be im-

paired.

Note 2. All voltage are measured with respect to GND, unless otherwise specified. The separate

A GND point should always be wired to the D GND.

Note 3. A zener d i ode exists, internal ly, f rom VCC to G N D a nd h as a typical breakdown v ol tage o f 7V.

Electrical Characteristics: (VCC = 5V, TA = 0° to +70°C, f

Parameter Test Conditions Min Typ Max Unit

= 640kHz unless otherwise specified)

CLK

Total Unadjusted Error (Note 4) V
V

/2 Input Resistance 2.5 8.0 – kΩ

REF

Analog Input Voltage Range V(+) or V(–), Note 5 GND–0.05 – VCC+0.05 V
DC Common–Mode Error Over Analog Input Voltage Range – ±1/
Power Supply Sensitivity VCC = 5V ±10% Over Allowed

/2 = 2.500V – – ±1/

REF

±1/

VIN(+) and VIN(–) Voltage Range,
Note 5

16
16

±1/
±1/

2

8
8

LSB

LSB
LSB

Note 4. The NTE2053 A/D does not require a zero adjust.
Note 5. For VIN(–) ≥ VIN(+) the digital output code will be 0000 0000. Two on–chip diodes are tied

to each analog input which will forward conduct for analog input voltages one diode drop bel­wo GND or one diode drop greater than the VCC supply . Be careful, during testing at low V

CC

levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct – espe­cially at elevated temperatures, and cause errors for analog inputs near full–scale. The spec
allows 50mV forward bias of either diode. This means that as long as the analog VIN does
not exceed the supply voltage by more than 50mV, the output code will be correct. To
achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply
voltage of 4.950V over temperature variations, initial tolerance, and loading.

AC Electrical Characteristics: (VCC = 5V, TA = +25°C unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

Conversion Time T

Clock Frequency f
Clock Duty Cycle Note 6 40 – 60 %
Conversion Rate in Free–Running

Mode
Width of WR Input (Start Pulse Width) t
Access Time (Delay from Falling Edge

of RD to Output Data Valid)
TRI–STATE Control (Delay from Rising

Edge of RD to Hi–Z State)
Delay from Falling Edge of WR or RD

to Reset of INTR
Input Capacitance of Logic

Control Inputs
TRI–STATE Output Capacitance

(Data Buffers)

CLK

CR INTR tied to WR with

W(WR)L

t

ACC

t1H, t

tWI, t

C

C

OUT

Note 6. Accuracy is guaranteed at f

f

C

0HCL

RI

IN

CLK

= 640kHz, Note 7 103 – 114 µs

CLK

Note 6, Note 7 66 – 73 1/f
VCC = 5V, Note 6 100 640 1460 kHz

– – 8770 conv/s

CS = 0V, f
CS = 0, Note 8 100 – – ns
CL = 100pF – 135 200 ns

= 10pF, RL = 10k – 125 200 ns

= 640kHz

CLK

– 300 450 ns

– 5 7.5 pF

– 5 7.5 pF

= 640kHz. At higher clock frequencies accuracy can de-

CLK

grade. For lower clock frequencies, the duty cycle limits can be extended so long as the mini­mum clock high time interval or minimum clock low time interval is no less than 275ns.

Note 7. With an asynchronous start pulse, up to 8 clock periods may be required before the internal

clock phases are proper to start the conversion process. The start request is internally
latched.

Note 8. The CS input is assumed to bracket the WR strobe input and therefore timing is dependent

on the WR pulse width. An arbitrary wide pulse width will hold the converter on a reset mode
and the start of conversion is initiated by the low to high transition of the WR pulse.

Electrical Characteristics (Cont’d): (VCC = 5V, TA = 0° to +70°C unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

Control Inputs (Note: CLK IN (Pin4) is the input of a Schmitt trigger circuit and is therefore specified separately)

Logical “1” Input V oltage

VIN(1) VCC = 5.25V 2.0 – 15 V

(Except Pin4 CLK IN)
Logical “0” Input V oltage

VIN(0) VCC = 4.75V – – 0.8 V

(Except Pin4 CLK IN)
Logical “1” Input Current (All Inputs) IIN(1) VIN = 5V – 0.005 1 µA
Logical “0” Input Current (All Inputs) IIN(0) VIN = 0V –1 –0.005 – µA

CLOCK IN and CLOCK R

CLK IN (Pin4) Positive Going

VT+ 2.7 3.1 3.5 V

Threshold Voltage
CLK IN (Pin4) Negative Going

VT– 1.5 1.8 2.1 V

Threshold Voltage
CLK IN (Pin4) Hysteresis (VT+)–(VT–) V
Logical “0” CLK R Output Voltage V
Logical “1” CLK R Output V oltage V

OUT
OUT

H

(0) VCC = 4.75V, IO = 360µA – – 0.4 V
(1) VCC = 4.75V, IO = –360µA 2.4 – – V

0.6 1.3 2.0 V

Data Outputs and INTR

Logical “0” Output V oltage

Data Outputs

INTR Outputs VCC = 4.75V, I

Logical “1” Output V oltage V

V

(0)

OUT

OUT

VCC = 4.75V, I

= 1.6mA – – 0.4 V

OUT

= 1.0mA – – 0.4 V

OUT

(1) VCC = 4.75V, IO = –360µA 2.4 – – V

VCC = 4.75V, IO = –10µA 4.5 – – V
V

TRI–STATE Disable Output Leakage I

(All Data Buffers)
Source Current I

SOURCEVOUT

OUT

= 0V –3 – – µA

OUT

V

= 5V – – 3 µA

OUT

Short to GND,

4.5 6.0 – mA

TA = +25°C

Sink Current I

SINK

V

Short to VCC,

OUT

9.0 16 – mA

TA = +25°C

Power Supply

Supply Current (Includes Ladder

Current)

I

CC

f

= 640kHz,

CLK

V

/2 = NC. TA = +25°C,

REF

– 1.1 1.8 mA

CS = “1”

Functional Description:

The NTE2053 contains a circui t equivalent to the 256R network. Analog s witches are sequenced by
successive a pproximation l ogic t o m atch t he a nalog d iffer ence input v oltage [ VIN(+) – VIN(–)] t o a c orre­sponding tap on t he R n etwork. T he m ost s igni ficant b it i s t ested f irst and a fter 8 c omparisons ( 64 c l ock
cycles) a digital 8–bit binary code (1111 1111 = full–scale) is t ransfer red to an output latch and then an
interrupt i s a sserted ( INTR makes a high–to–low t ransition). A c onversion in p rocess c an be inter rupted
by i ssuing a s econd s tart c ommand. The d evice may b e operated i n t he free–running m ode b y c onnect­ing INTR to the WR input w ith C S = 0. To insure start–up u nder a ll possible condi tions, a n e xternal WR
pulse is required during the first power–up cycle.

On the h igh–to–low t ransition o f t he W R input the i nternal S AR l atches a nd t he s hift r egister s tages a re
reset. A s long as the CS i nput and WR input r emain l ow . t he A /D w ill r emain i n a r eset s tate. Conversion
will start from 1 to 8 clock periods after at least one of these inputs makes a low–to–high transition.

Functional Description (Cont’d):

The converter is started by having CS and WR simultaneously low. This sets the start flip–flop (F/F)
and the resulting “1” level resets the 8–bit shift r egi ster, resets t he interrupt (INTR) F/F and i nputs a “1”
to the D f lop, F /F1, whic h i s at t he i nput e nd of t he 8 –bit shift r egister . I nternal clock si gnals then tr ansfer
this “1” to the Q o utput of F /F1. T he A ND g ate, G 1, com bines t his “1” o utput w ith a c lock s ignal t o p rovide
a reset signal to the s tart F /F. If the set signal is no longer present (either WR or CS is a “1”) the start
F/F is reset and the 8–bit shift register then can have the “1” clocked in, which starts the conversion
process. If the set signal were to still be present, this reset pulse would have no effect (both outputs
of t he start F /F w ould m omentari ly b e at a “1” level) and the 8–bit shift r egister w ould c ontinue t o be held
in the reset m ode. This logic therefore a ll ows f or wide CS and WR signals and the converter will s tart
after at least one of these si gnal s returns high and the internal clocks again provide a reset signal for
the start F/F.

After the “1” is c locked t hrough t he 8 –bit shift register ( w hich c om pletes t he SAR search) it appears a s
the input to the D–type latch, LATCH 1. As soon as this “1” is output from the shift register, the AND
gate, G2, causes the new digital word to transfer to the TRI–STATE output latches. When LATCH 1
is subsequently enabled, the Q output m akes a high–to–low transition which c auses the INTR F/F to
set. An inverting buffer then supplies the INTR input signal.

Note that the SET control o f t he I NTR F /F r emains l ow f or 8 o f t he e xternal c lock p eriods ( as the i nternal
clocks run a t 1/8 of the frequency of the external clock). If the data output is continuously enabled (CS
and RD both are held low), the INTR output will still signal the end of conversion (by a high–to–low
transition), because the SET input can control the Q output of the INTR F/F even though the RESET
input is constant at a “1” level in this operating mode. This INTR output will therefore stay low for the
duration of the SET signal, which is 8 periods of the external clock frequency (assuming the A/D is
not started during this interval).

When o perating i n t he f ree–r unning or c ontinuous c onversion m ode ( INT R pin tied to WR and CS wired
low), the ST ART F/F is SET by the high–to–low transition of the INTR signal. This resets the SHIFT
REGISTER whi ch causes the input t o t he D–type latch, L ATCH 1, t o g o low. A s t he latch enable input
is still present, the Q output will go hi gh, which then allows the INTR F/F t o b e RESET. This reduces
the width of the resulting INTR output pulse to only a few propagation delays (approximately 300ns).

When data is to be read, the combination of both CS and RD being low will c ause the INTR F /F to b e
reset and the TRI–STATE output latches will be enables to provide the 8–bit digital outputs.

Pin Connection Diagram

CS V

1
2

RD

WR

3

CLK IN

INTR

VIN (+)
VIN (–)

A GND

V

REF

D GND DB7 (MSB)10 11

4
5

6
7

8 13

/2

20
19
18
17
16

15 DB3
14 DB4

CC

CLK R
DB0 (LSB)

DB1
DB2

DB5
DB69 12

20 11

.280 (7.12) Max

110

.995 (25.3) Max .300

(7.62)

.280

(7.1)

.100 (2.54) .125 (3.17) Min

.385 (9.8)