Datasheet NDH853N Datasheet (Fairchild Semiconductor)

May 1997

NDH853N
N-Channel Enhancement Mode Field Effect Transistor

General Description Features

These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as battery powered
circuits or portable electronics where fast switching, low in-line
power loss, and resistance to transients are needed.

___________________________________________________________________________________________

7.6 A, 30 V. R
R

High density cell design for extremely low R

= 0.017 Ω @ VGS = 10 V

DS(ON)

= 0.025 Ω @ VGS = 4.5 V.

DS(ON)

DS(ON)

.

Proprietary SuperSOTTM-8 small outline surface mount
package with high power and current handling capability.

Absolute Maximum Ratings T

= 25°C unless otherwise noted

A

5

6
7

8

4
3

2
1

Symbol Parameter NDH853N Units

V

DSS

V

GSS

I

D

Drain-Source Voltage 30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) 7.6 A

- Pulsed 23

P

D

TJ,T

Maximum Power Dissipation (Note 1a) 1.8 W

(Note 1b)

(Note 1c)

Operating and Storage Temperature Range -55 to 150 °C

STG

1

0.9

THERMAL CHARACTERISTICS

R

θJA

R

θJC

Thermal Resistance, Junction-to-Ambient (Note 1a) 70 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 20 °C/W

© 1997 Fairchild Semiconductor Corporation

NDH853N Rev. C

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BV
I

I
I

DSS

DSS

GSSF

GSSR

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current

VDS = 24 V, V

GS

= 0 V

TJ= 55°C

1 µA

10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse

VGS = -20 V, VDS= 0 V

-100 nA

ON CHARACTERISTICS (Note 2)

V

R

I
g

GS(th)

DS(ON)

D(on)

FS

Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.5 2 V

TJ= 125°C

0.7 1 1.6

Static Drain-Source On-Resistance VGS = 10 V, ID = 7.6 A 0.014 0.017

0.02 0.031

0.021 0.025

23 A

18 S

On-State Drain Current
Forward Transconductance

TJ= 125°C
VGS = 4.5 V, ID = 6.7 A
VGS = 10 V, VDS = 5 V
VDS = 10 V, ID = 7.6 A

Ω

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 630 pF

VDS = 15 V, V
f = 1.0 MHz

GS

= 0 V,

Reverse Transfer Capacitance 210 pF

1140 pF

SWITCHING CHARACTERISTICS (Note 2)

t
t
t
t
Q
Q
Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time VDD = 10 V, ID = 1 A,

V

= 10 V, R

Turn - On Rise Time 24 50 ns

GEN

GEN

= 6 Ω

14 30 ns

Turn - Off Delay Time 73 120 ns
Turn - Off Fall Time 48 80 ns
Total Gate Charge VDS = 15 V,
Gate-Source Charge 2.8 nC

ID = 7.6 A, VGS = 10 V

38 50 nC

Gate-Drain Charge 12.7 nC

NDH853N Rev. C

ELECTRICAL CHARACTERISTICS (T

TJ−

T

TJ−

T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

Notes:

1. R

θ

design while R

P

Typical R

Maximum Continuous Drain-Source Diode Forward Current 1.5 A
Drain-Source Diode Forward Voltage

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

D

is determined by the user's board design.

CA

θ

A

(t)

=

(t)

R

θJA

using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

JA

θ

a. 70oC/W when mounted on a 1 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.026 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.005 in2 pad of 2oz copper.

=

R

θJC+RθCA

A

2

(t)

= I

× R

DS(ON)@T

D

(t)

J

1a

VGS = 0 V, IS = 1.5 A (Note 2)

1b

1c

0.72 1.2 V

is guaranteed by

JC

θ

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

NDH853N Rev. C

Typical Electrical Characteristics

30

V =10V

GS

6.0

25

4.5

20

15

10

5

D

I , DRAIN-SOURCE CURRENT (A)

0

0 0.5 1 1.5 2 2.5 3

4.0

3.5

3.0

V , DRAIN-SOURCE VOLTAGE (V)

DS

2.5

3

V = 3.5V

2.5

2

1.5

DS(on)

R , NORMALIZED

1

DRAIN-SOURCE ON-RESISTANCE

0.5
0 5 10 15 20 25 30

GS

I , DRAIN CURRENT (A)

D

4.0

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation

withDrain Current and Gate Voltage.

1.6

I = 7.6A

D

1.4

V = 10V

GS

1.2

1

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

1.8

V = 10 V

GS

1.6

1.4

1.2

1

DS(on)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6
0 5 10 15 20

T = 125°C

J

I , DRAIN CURRENT (A)

D

4.5

5.0

6.0
10

25°C

-55°C

Figure 3. On-Resistance Variation

with Temperature.

30

V = 10V

DS

25

20

15

10

D

I , DRAIN CURRENT (A)

5

0

0.5 1 1.5 2 2.5 3 3.5 4 4.5
V , GATE TO SOURCE VOLTAGE (V)

GS

T = -55°C

J

125°C

Figure 5. Transfer Characteristics.

25°C

Figure 4. On-Resistance Variation

with Drain Current and Temperature.

1.2

V = V

1.1

1

0.9

0.8

th

V , NORMALIZED

0.7

0.6

GATE-SOURCE THRESHOLD VOLTAGE

0.5

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

DS

I = 250µA

D

Figure 6. Gate Threshold Variation

with Temperature.

GS

NDH853N Rev. C

T , JUNCTION TEMPERATURE (°C)

Typical Electrical Characteristics (continued)

1.1

I = 250µA

D

1.08

1.06

1.04

1.02

DSS

1

BV , NORMALIZED

0.98

0.96

DRAIN-SOURCE BREAKDOWN VOLTAGE

0.94

-50 -25 0 25 50 75 100 125 150

J

Figure 7. Breakdown Voltage Variation with

Temperature.

3000

2000

1000

500

300

CAPACITANCE (pF)

f = 1 MHz

200

V = 0V

GS

100

0.1 0.2 0.5 1 2 5 10 20 30
V , DRAIN TO SOURCE VOLTAGE (V)

DS

C

C

30

V = 0V

GS

10

1

0.1

0.01

0.001

S

I , REVERSE DRAIN CURRENT (A)

0.0001
0 0.2 0.4 0.6 0.8 1 1.2

T = 125°C

J

V , BODY DIODE FORWARD VOLTAGE (V)

SD

25°C

-55°C

Figure 8. Body Diode Forward Voltage Variation

with Source Current and

Temperature.

10

I = 7.6A

D

iss

oss

C

rss

8

6

4

2

GS

V , GATE-SOURCE VOLTAGE (V)

0

0 10 20 30 40

Q , GATE CHARGE (nC)

g

V = 10V

DS

20V

15V

Figure 9. Capacitance Characteristics.

V

DD

V

IN

D

V

GS

R

GEN

G

S

Figure 11. Switching Test Circuit.

Figure 10. Gate Charge Characteristics.

t t

on off

t

R

d(on)

L

V

OUT

V

OUT

r

90%

10%

DUT

t

d(off)

90%

10%

tt

f

INVERTED

90%

V

IN

50%

50%

10%

PULSE WIDTH

Figure 12. Switching Waveforms.

NDH853N Rev. C

Typical Electrical and Thermal Characteristics (continued)

35

V =10V

DS

30

25

20

15

10

5

FS

g , TRANSCONDUCTANCE (SIEMENS)

0

0 5 10 15 20 25 30

I , DRAIN CURRENT (A)

D

T = -55°C

J

25°C

125°C

Figure 13. Transconductance Variation
with Drain Current and Temperature.

9

8

7

6

1b

1c

5

D

I , STEADY-STATE DRAIN CURRENT (A)

4

0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air
V = 10V

GS

2

1a

2.5

2

1.5

1b

1

1c

0.5

STEADY-STATE POWER DISSIPATION (W)

0

0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air

2

Figure 14. SOT-8 Maximum Steady-State Power

Dissipation versus Copper Mounting Pad
Area.

50
30

10

RDS(ON) LIMIT

3

1

0.3

V = 10V

0.1

D

I , DRAIN CURRENT (A)

0.03

0.01

GS

SINGLE PULSE

R =See Note1c

JA

θ

T = 25°C

A

0.1 0.2 0.5 1 2 5 10 30 50
V , DRAIN-SOURCE VOLTAGE (V)

DS

DC

100us

1ms

10ms

100ms

1s

10s

1a

Figure 15. Maximum Steady-State Drain Current

Figure 16. Maximum Safe Operating Area.

versus Copper Mounting Pad Area.

1

D = 0.5

0.5

0.3

0.2

0.2

0.1

0.05

0.03

r(t), NORMALIZED EFFECTIVE

0.02

TRANSIENT THERMAL RESISTANCE

0.01

0.1

0.05

0.02

0.01
Single Pulse

0.0001 0.001 0.01 0.1 1 10 100 300

Figure 17. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change

depending on the circuit board design.

t , TIME (sec)

1

R (t) = r(t) * R

JA

θ

R = See Note 1c

JA

θ

P(pk)

t

1

t

2

T - T = P * R (t)

J

A

Duty Cycle, D = t / t

JA

θ

JA

θ

2

1

NDH853N Rev. C