Datasheet NDH8503N Datasheet (Fairchild Semiconductor)

May 1997

NDH8503N Dual N-Channel Enhancement Mode Field Effect Transistor

General Description Features

SuperSOTTM-8 N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package.

____________________________________________________________________________________________

3.8 A, 30 V. R R

= 0.033 Ω @ VGS = 10 V

DS(ON)

= 0.05 Ω @ VGS = 4.5 V.

DS(ON)

Proprietary SuperSOTTM-8 package design using copper lead frame for superior thermal and electrical capabilities.

High density cell design for extremely low R

DS(ON)

.

Exceptional on-resistance and maximum DC current capability.

4

3 2

1

Absolute Maximum Ratings T

= 25°C unless otherwise note

A

5

6

7

8

Symbol Parameter NDH8503N Units

V

DSS

V

GSS

I

D

Drain-Source Voltage 30 V Gate-Source Voltage ±20 V Drain Current - Continuous (Note 1) 3.8 A

- Pulsed 10.5

P

D

TJ,T

Maximum Power Dissipation (Note 1 ) 0.8 W Operating and Storage Temperature Range -55 to 150 °C

STG

THERMAL CHARACTERISTICS

R

θJA

R

θJC

Thermal Resistance, Junction-to-Ambient (Note 1) 156 °C/W Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W

NDH8503N Rev.C

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS

BV I

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V Zero Gate Voltage Drain Current

VDS = 24 V, V

GS

= 0 V

1 µA

TJ = 55oC 10 µA

I

GSSF

I

GSSR

Gate - Body Leakage, Forward

VGS = 20 V, VDS = 0 V

Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA

100 nA

ON CHARACTERISTICS (Note 2)

V

GS(th)

Gate Threshold Voltage

VDS = VGS, ID = 250 µA

1 1.67 2 V

TJ = 125oC 0.8 1.04 1.6

R

DS(ON)

Static Drain-Source On-Resistance

VGS = 10 V, ID = 3.8 A

0.027 0.033

Ω

TJ = 125oC 0.04 0.06

0.041 0.05

9

I

g

D(on)

FS

VGS = 4.5 V, ID = 3.2 A

On-State Drain Current VGS = 10 V, VDS = 5 V 10.5 A

VGS = 4.5 V, VDS = 5 V

Forward Transconductance VDS = 5 V, ID = 3.8 A 9 S

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance Output Capacitance 310 pF

VDS = 15 V, VGS = 0 V, f = 1.0 MHz

Reverse Transfer Capacitance 125 pF

500 pF

SWITCHING CHARACTERISTICS (Note 2) t t t t Q Q Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time VDD = 10 V, ID = 1 A, Turn - On Rise Time 15 28 ns

VGS = 10 V, R

GEN

= 6 Ω

10 18 ns

Turn - Off Delay Time 20 35 ns Turn - Off Fall Time 9 18 ns Total Gate Charge VDS = 10 V, Gate-Source Charge 1.8 nC

ID = 3.8 A, VGS = 4.5 V

18 25 nC

Gate-Drain Charge 4.2 nC

NDH8503N Rev.C

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

otes:

1. R design while R

P

D

Typical R

Scale 1 : 1 on letter size paper.

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

Maximum Continuous Drain-Source Diode Forward Current 0.67 A Drain-Source Diode Forward Voltage

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

(t)

is determined by the user's board design.

CA

θ

T

=

R

θ

T

J−TA

θJA

JA

156oC/W when mounted on a 0.0025 in2 pad of 2oz copper.

J−TA

=

(t)

R

θ

JC

for single device operation using the board layout shown below on 4.5"x5" FR-4 PCB in a still air environment:

2

= I

(t) ×R

DS(ON ) T

D

+R

(t)

θ

CA

J

VGS = 0 V, IS = 0.67 A (Note 2)

0.72 1.2 V

is guaranteed by

JC

θ

NDH8503N Rev.C

Typical Electrical Characteristics

20

V =10V

GS

16

12

8

4

D

I , DRAIN-SOURCE CURRENT (A)

0

0 0.5 1 1.5 2 2.5 3

6.0

5.0

4.5

4.0

3.5

V , DRAIN-SOURCE VOLTAGE (V)

DS

Figure 1. On-Region Characteristics.

1.8

I = 3.8A

D

V = 10V

1.6

GS

1.4

1.2

1

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

3.0

2.5

V = 3.5V

GS

2.25

2

1.75

1.5

1.25

DS(on)

R , NORMALIZED

1

DRAIN-SOURCE ON-RESISTANCE

0.75 0 4 8 12 16 20

4.0

4.5

I , DRAIN CURRENT (A)

D

5.0

6.0

Figure 2. On-Resistance Variation with Gate

Voltage and Drain Current.

2

V = 10V

GS

1.75

1.5

1.25

1

0.75

DS(on)

R , NORMALIZED

0.5

DRAIN-SOURCE ON-RESISTANCE

0.25 0 4 8 12 16 20

T = 125°C

J

25°C

-55°C

I , DRAIN CURRENT (A)

D

7.0 10

Figure 3. On-Resistance Variation with

Temperature.

20

V = 5V

DS

16

12

8

D

I , DRAIN CURRENT (A)

4

0

1 1.5 2 2.5 3 3.5 4 4.5

V , GATE TO SOURCE VOLTAGE (V)

GS

T = -55°C

J

125°C

25°C

Figure 4. On-Resistance Variation with Drain

Current and Temperature.

1.2

1.1

1

0.9

th

0.8

V , NORMALIZED

0.7

GATE-SOURCE THRESHOLD VOLTAGE

0.6

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

Figure 5. Transfer Characteristics. Figure 6. Gate Threshold Variation with

Temperature.

NDH8503N Rev.C

V = V

DS

GS

I = 250µA

D

Typical Electrical Characteristics

1.12

I = 250µA

D

1.08

1.04

1

DSS

BV , NORMALIZED

0.96

DRAIN-SOURCE BREAKDOWN VOLTAGE

0.92

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Breakdown Voltage Variation with

Temperature.

1500

1000

800

500

300

200

CAPACITANCE (pF)

f = 1 MHz

100

V = 0V

GS

50

0.1 0.2 0.5 1 3 5 10 30 V , DRAIN TO SOURCE VOLTAGE (V)

DS

C

iss

oss

rss

15

V =0V

GS

5

1

0.1

0.01

0.001

S

I , REVERSE DRAIN CURRENT (A)

0.0001 0 0.2 0.4 0.6 0.8 1 1.2

V , BODY DIODE FORWARD VOLTAGE (V)

T = 125°C

J

25°C

-55°C

SD

Figure 8. Body Diode Forward Voltage Variation

with Current and Temperature.

10

I = 3.8A

D

8

6

4

2

GS

V , GATE-SOURCE VOLTAGE (V)

0

0 5 10 15 20

Q , GATE CHARGE (nC)

g

V = 10V

DS

15V

20V

Figure 9. Capacitance Characteristics.

V

DD

V

IN

D

V

GS

R

GEN

G

S

Figure 11. Switching Test Circuit.

Figure 10. Gate Charge Characteristics.

t t

on off

t

d(on)

R

L

V

OUT

V

OUT

r

90%

10%

t

d(off)

90%

10%

DUT

90%

V

IN

50%

10%

PULSE WIDTH

Figure 12. Switching Waveforms.

NDH8503N Rev.C

tt

f

INVERTED

Typical Electrical and Thermal Characteristics

20

V = 5V

DS

16

T = -55°C

J

25°C

12

8

4

FS

g , TRANSCONDUCTANCE (SIEMENS)

0

0 4 8 12 16 20

I , DRAIN CURRENT (A)

D

125°C

Figure 13. Transconductance Variation with Drain

Current and Temperature.

1

D = 0.5

0.2

0.1

0.01

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

0.001

0.0001 0.001 0.01 0.1 1 10 100 300

0.1

0.05

0.02

0.01 Single Pulse

20 10

RDS(ON) LIMIT

5

1

0.3

0.1

D

I , DRAIN CURRENT (A)

0.03

0.01

V = 10V

GS

SINGLE PULSE

R = See Note 1

JA

θ

T = 25°C

A

0.1 0.2 0.5 1 2 5 10 30 50 V , DRAIN-SOURCE VOLTAGE (V)

DS

Figure 14. Maximum Safe Operating Area.

R (t) = r(t) * R

JA

θ

R = See Note 1

JA

θ

P(pk)

t

1

t

2

T - T = P * R (t)

J

A

Duty Cycle, D = t / t

t , TIME (sec)

1

10s

DC

θ

1s

JA

1 2

10ms

100ms

JA

θ

100us

1ms

Figure 15. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1. Transient thermal response will change depending on the circuit board design.

NDH8503N Rev.C

Datasheet NDH8503N Datasheet (Fairchild Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual