NDH832P
P-Channel Enhancement Mode Field Effect Transistor
General DescriptionFeatures
June 1996
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
-4.2A, -20V. R
R
High density cell design for extremely low R
Enhanced SuperSOTTM-8 small outline surface mount
package with high power and current handling capability.
= 0.06Ω @ VGS = -4.5V
DS(ON)
= 0.08Ω @ VGS = -2.7V.
DS(ON)
DS(ON).
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
TJ = 125oC
VGS = -2.7 V, ID = -3.7 A
VGS = -4.5 V, VDS = -5 V
VGS = -2.7 V, VDS = -5 V
VDS = -10 V, ID = -4.2 A
0.0450.06
0.0630.12
0.0640.08
-15A
-5
9S
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance530pF
VDS = -10 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance180 pF
1000pF
SWITCHING CHARACTERISTICS(Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay TimeVDD = -5 V, ID = -1 A,
V
= -4.5 V, R
Turn - On Rise Time5370ns
GEN
GEN
= 6 Ω
1320ns
Turn - Off Delay Time6080ns
Turn - Off Fall Time3340ns
Total Gate ChargeVDS = -10 V,
Gate-Source Charge1.2nC
ID = -4.2 A, VGS = -4.5 V
1830nC
Gate-Drain Charge6nC
NDH832P Rev. B2
Page 3
Electrical Characteristics(T
= 25°C unless otherwise noted)
A
SymbolParameterConditionsMinTypMaxUnits
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
design while R
P
Typical R
Scale 1 : 1 on letter size paper
Maximum Continuous Drain-Source Diode Forward Current-1.5A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
D
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 70oC/W when mounted on a 1 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.026 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.005 in2 pad of 2oz copper.
T
J−TA
=
(t)
R
θJA
θ
JC
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: