These logic level N-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process has been especially tailored to minimize on-state
resistance, provide superior switching performance, and
withstand high energy pulses in the avalanche and
commutation modes. These devices are particularly suited for
low voltage applications such as automotive, DC/DC
converters, PWM motor controls, and other battery powered
circuits where fast switching, low in-line power loss, and
resistance to transients are needed.
75 A, 50 V. R
R
= 0.010 Ω @ VGS= 5 V
DS(ON)
= 0.0075 Ω @ VGS= 10 V.
DS(ON)
Low drive requirements allowing operation directly from logic
drivers. V
GS(TH)
< 2.0V.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON)
.
TO-220 and TO-263 (D2PAK) package for both through hole
and surface mount applications.
Maximum Continuos Drain-Source Diode Forward Current75A
Maximum Pulsed Drain-Source Diode Forward Current180A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
VGS = 0 V, IS = 37.5 A (Note)
VGS = 0 V, IF = 37.5 A
0.91.3V
40150ns
dIF/dt = 100 A/µs
NDP7052L Rev.B1
Page 3
Typical Electrical Characteristics
R , NORMALIZED
R , ON-RESISTANCE (OHM)
100
V = 10V
80
60
40
20
D
I , DRAIN-SOURCE CURRENT (A)
0
00.511.522.53
6.0
GS
5.0
3.5
3.0
2.5
V , DRAIN-SOURCE VOLTAGE (V)
DS
1.8
V = 3.0V
1.6
GS
1.4
1.2
1
DS(on)
DRAIN-SOURCE ON-RESISTANCE
0.8
0.6
020406080100
3.5
4.0
4.5
I , DRAIN CURRENT (A)
D
5.0
6.0
10
Figure 1. On-Region Characteristics.
2
I = 37.5A
D
1.75
V = 5V
GS
1.5
1.25
1
DS(ON)
R , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
0.75
0.5
-50-250255075100125150175
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. On-Resistance Variation
with Temperature.
60
V = 5V
DS
50
40
30
20
D
I , DRAIN CURRENT (A)
10
0
11.522.533.5
V , GATE TO SOURCE VOLTAGE (V)
GS
T = -55°C
J
125°C
25°C
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage.
0.08
25°C
0.06
0.04
0.02
DS(on)
0
22.533.544.55
125°C
V , GATE TO SOURCE VOLTAGE (V)
GS
Figure 4. On Resistance Variation with
Gate-To- Source Voltage.
60
V = 0V
GS
20
1
0.1
0.01
S
0.001
I , REVERSE DRAIN CURRENT (A)
0.0001
00.20.40.60.811.2
T = 125°C
J
25°C
-55°C
V , BODY DIODE FORWARD VOLTAGE (V)
SD
ID=37.5A
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage
Variation with Source Current and Temperature.
NDP7052L Rev.B1
Page 4
Typical Electrical Characteristics (continued)
10
I = 75A
D
8
6
4
2
GS
V , GATE-SOURCE VOLTAGE (V)
0
020406080100120140160
Q , GATE CHARGE (nC)
g
V = 12V
DS
24V
Figure 7. Gate Charge Characteristics.
400
200
DS(ON)
R Limit
100
50
20
10
V = 10V
GS
5
SINGLE PULSE
D
I , DRAIN CURRENT (A)
2
1
0.5
0.51351020 3080
o
R = 1 C/W
JC
θ
T = 25 °C
C
V , DRAIN-SOURCE VOLTAGE (V))
DS
100µs
1ms
10ms
100ms
DC
48V
8000
C
4000
2000
1500
1000
CAPACITANCE (pF)
f = 1 MHz
500
V = 0V
GS
300
123510203050
V, DRAIN TO SOURCE VOLTAGE (V)
DS
iss
C
oss
C
rss
Figure 8.Capacitance Characteristics.
2000
1500
1000
POWER (W)
500
0
0.10.31310301003001,000
SINGLE PULSE TIME (SEC)
SINGLE PULSE
R =1° C/W
JC
θ
T = 25°C
C
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
1
0.5
0.3
0.2
0.1
0.05
0.03
0.02
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
0.01
0.010.050.10.51510501005001000
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
t ,TIME (ms)
1
R (t) = r(t) * R
θ
JC
R = 1.0 °C/W
θ
JC
P(pk)
t
1
t
2
T- T = P * R (t)
CJ
Duty Cycle, D = t /t
Figure 11. Transient Thermal Response Curve.
θ
JC
JC
θ
1 2
NDP7052L Rev.B1
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