INTEGRATED CIRCUITS
74F646, 74F646A
Octal transceiver/register, non-inverting
(3-State)
74F648, 74F648A
Octal transceiver/register, inverting
(3-State)
Product specification
IC15 Data Handbook
1990 Sep 25
Philips Semiconductors Product specification
74F646/A/74F648/AT ransceivers/registers
FEA TURES
•Combines 74F245 and two 74F374 type functions in one chip
•High impedance base inputs for reduced loading (70µA in high
and low states)
•Independent registers for A and B buses
•Multiplexed real-time and stored data
•Choice of non-inverting and inverting data paths
•Controlled ramp outputs for 74F646A/74F648A
•3-state outputs
•300 mil wide 24-pin slim dip package
TYPE
74F646/74F648 115MHz 140mA
74F646A/74F648A 185MHz 105mA
DESCRIPTION
The 74F646/74F646A and 74F648/74F648A transceivers/registers
consist of bus transceiver circuits with 3–state outputs, D–type
flip–flops, and control circuitry arranged for multiplexed transmission
of data directly from the input bus or the internal registers. Data on
the A or B bus will be clocked into the registers as the appropriate
clock pin goes high. Output enable (OE
to control the transceiver function. In the transceiver mode, data
present at the high impedance port may be stored in either the A or
B register or both.
The select (SAB, SBA) pins determine whether data is stored or
transferred through the device in real–time. The DIR determines
which bus will receive data when the OE
isolation mode (OE
register and/or data from bus B may be stored in the A register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B may be driven at a time.
TYPICAL f
max
= high), data from bus A may be stored in the B
TYPICAL SUPPLY CURRENT ( TOTAL)
) and DIR pins are provided
is active low. In the
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE PKG DWG #
VCC = 5V ±10%, T
24–pin plastic slim DIP
(300mil)
24–pin plastic SOL N74F646D, N74F646AD, N74F648D, N74F648AD SOT137-1
N74F646N, N74F646AN, N74F648N, N74F648AN SOT222-1
= 0°C to +70°C
amb
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
A0 – A7, B0 – B7 A and B inputs 3.5/0.1 16 70µA/70µA
CPAB A–to–B clock input 1.0/0.033 20µA/20µA
CPBA B–to–A clock input 1.0/0.033 20µA/20µA
SAB A–to–B select input 1.0/0.033 20µA/20µA
SBA B–to–A select input 1.0/0.033 20µA/20µA
DIR Data flow directional control enable input 1.0/0.033 20µA/20µA
OE Output enable input 1.0/0.033 20µA/20µA
A0 – A7, B0 – B7 A, B outputs for N74F646A/N74F648A 750/80 15mA/48mA
A0 – A7, B0 – B7 A, B outputs for N74F646/N74F648 750/106.7 15mA/64mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
1990 Sep 25 853-1 124 00515
2
74F (U.L.) HIGH/
LOW
LOAD VALUE HIGH/
LOW
Philips Semiconductors Product specification
74F646/A/74F648/ATransceivers/registers
PIN CONFIGURATION
1
CPAB
2
SAB
3
DIR
4
A0
5
A1
6
A2
7
A3
8
A4
9
A5
10
A6
11
A7
GND
LOGIC SYMBOL
4567891011
A0 A1 A2 A3 A4 A5 A6 A7
CPAB
1
SAB
2
DIR
3
CPBA
23
SBA
22
OE
21
B0 B1 B2 B3 B4 B5 B6 B7
74F646/646A
74F646/646A
24
V
CC
23
CPBA
22
SBA
21
OE
20
B0
19
B1
18
B2
17
B3
16
B4
15
B5
14
B6
1312
B7
SF00386
IEC/IEEE SYMBOL
21
3
23
22
1
2
4
5
6
7
8
9
10
11
LOGIC DIAGRAM
21
OE
3
DIR
23
CPBA
22
SBA
1
CPAB
2
SAB
74F646/646A
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
1
1
6D
1
/
74F646/646A
5
4D
1
5
7
1
2
7
20
19
18
17
16
15
14
13
SF00388
V
= Pin 24
CC
GND = Pin 12
1990 Sep 25
20 19 18 17 16 15 14 13
SF00387
3
4
A0
VCC = Pin 24
GND = Pin 12
I of 8 channels
1D
C1
to 7 other channels
1D
C1
20
B0
SF00393
Philips Semiconductors Product specification
74F646/A/74F648/ATransceivers/registers
PIN CONFIGURATION
1
CPAB
2
SAB
3
DIR
4
A0
5
A1
6
A2
7
A3
8
A4
9
A5
10
A6
11
A7
GND
LOGIC SYMBOL
4567891011
74F648/648A
74F648/648A
24
V
23
CPBA
22
SBA
21
OE
20
B0
19
B1
18
B2
17
B3
16
B4
15
B5
14
B6
1312
B7
SF00389
CC
IEC/IEEE SYMBOL
21
3
23
22
1
2
4
5
6
7
8
9
10
11
LOGIC DIAGRAM
74F648/648A
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
1
1
7
6D
1
7
5
4D
1
5
1
2
20
19
18
17
16
15
14
13
SF00391
VCC = Pin 24
GND = Pin 12
A0 A1 A2 A3 A4 A5 A6 A7
CPAB
1
SAB
2
DIR
3
CPBA
23
SBA
22
OE
21
B0 B1 B2 B3 B4 B5 B6 B7
20 19 18 17 16 15 14 13
SF00390
OE
DIR
CPBA
SBA
CPAB
SAB
A0
1D
C1
74F648/648A
to 7 other channels
1D
C1
20
B0
SF00400
21
3
23
22
1
2
I of 8 channels
4
1990 Sep 25
4
Philips Semiconductors Product specification
74F646/A/74F648/ATransceivers/registers
FUNCTION TABLE
INPUTS DATA I/O OPERATING MODE
OE DIR CPAB CPBA SAB SBA An Bn 74F646/74F646A 74F648/74F648A
X X ↑ X X X Input Unspecified* Store A, B unspecified* Store A, B unspecified*
X X X ↑ X X Unspecified* Input Store B, A unspecified* Store B, A unspecified*
H X ↑ ↑ X X Input Input Store A and B data Store A and B data
H X H or L H or L X X Input Input Isolation, hold storage Isolation, hold storage
L L X X X L Output Input Real time B data to A bus Real time B data to A bus
L L X H or L X H Output Input Stored B data to A bus Stored B data to A bus
L H X X L X Input Output Real time A data to B bus Real time A data to B bus
L H H or L X H X Input Output Stored A data to B bus Stored A data to B bus
NOTES:
1. H = High–voltage level
2. L = Low–voltage level
3. X = Don’t care
4. ↑ = Low–to–high clock transition
5. * = The data output function may be enabled or disabled by various signals at the OE
always enabled, i.e., data at the bus pins will be stored on every low–to–high transition of the clock.
and DIR inputs. Data input functions are
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in high output state –0.5 to V
Current applied to output in low output state 74F646A, 74F648A 72 mA
Operating free air temperature range
Storage temperature range –65 to +150
PARAMETER RATING UNIT
CC
74F646, 74F648 128 mA
0 to +70
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS UNIT
MIN NOM MAX
V
V
V
I
I
I
T
CC
IH
IL
Ik
OH
OL
amb
Supply voltage 4.5 5.0 5.5 V
High–level input voltage 2.0 V
Low–level input voltage 0.8 V
Input clamp current –18 mA
High–level output current –15 mA
Low–level output current 74F646A, 74F648A 48 mA
74F646, 74F648 64 mA
Operating free air temperature range 0 +70
V
°C
°C
°C
1990 Sep 25
5
Philips Semiconductors Product specification
74F646/A/74F648/ATransceivers/registers
The following examples demonstrate the four fundamental
bus–management functions that can be performed with the
74F646/646A and 74F648/648A. The select pins determine whether
BUS MANAGEMENT FUNCTIONS
REAL TIME BUS TRANSFER
BUS A
OE DIR CPABCPBA SAB SBA
LL X X X L
BUS B TO BUS A
BUS B
REAL TIME BUS TRANSFER
BUS A TO BUS B
BUS A BUS A
DIR CPABCPBA SAB SBA
OE
LH X X L X
data is stored or transferred through the device in real time. The
output enable pins determine the direction of the data flow.
STORAGE FROM
A, B, OR A AND B
OE DIR CPABCPBA SAB SBA
XX ↑ XXX
XX X ↑ XX
HX ↑↑XX
TRANSFER STORED DATA
TO A AND/OR B
BUS A BUS BBUS BBUS B
OE DIR CPABCPBA SAB SBA
L L X H or L X H
L H H or L X H X
SF00392
1990 Sep 25
6
Philips Semiconductors Product specification
74F646/A/74F648/ATransceivers/registers
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
V
OH
V
OL
V
IK
I
I
High-level output voltage
Low-level output voltage All
Input clamp voltage VCC = MIN, II = I
Input current at others VCC = 0.0V, VI = 7.0V 100 µA
maximum input voltage A0–A7, B0–B7 VCC = MAX, VI = 5.5V 1 mA
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
O
I
CC
High–level input current OE, DIR, CPAB, VCC = MAX, VI = 2.7V 20 µA
Low–level input current CPBA, SAB, SBA VCC = MAX, VI = 0.5V –20 µA
Off–state output current,
+ I
IH
high–level voltage applied
Off–state output current,
+ I
IL
low–level voltage applied
Short–circuit output current
Output current
Supply current (total) I
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
Unless otherwise specified, V
2. All typical values are at VCC = 5V, T
3. Not more than one output should be shorted at a time. For testing I
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
is tested under conditions that produce current approximately one half of the true short–circuit output current (IOS).
4. I
O
PARAMETER TEST LIMITS UNIT
IOH =
1
±10%V
±5%V
±10%V
MIN TYP2MAX
2.4 V
CC
2.7 3.4 V
CC
2.0 V
CC
CC
CC
0.38 0.55 V
0.42 0.55 V
–0.73 -1.2 V
CONDITIONS
VCC = MIN, IOH = –3mA
VIL = MAX,
VIH = MIN
VCC = MIN,
VIL = MAX,
–15mA
IOL = 48mA ±10%V
74F646/74F648 only VIH = MIN IOL = 64mA ±5%V
IK
A0 – A7, B0 –B7
VCC = MAX, V
= 2.7V 70
O
VCC = MAX, VO = 0.5V –70
3
74F646, 74F648 VCC = MAX -100 -225 mA
4
= VCC for all test conditions.
X
tests should be performed last.
OS
74F646A, 74F648A VCC = MAX, V0 = 2.25V -60 -150 mA
amb
= 25°C.
74F646, I
74F648 I
74F646A, I
74F648A I
CCH
CCLVCC
CCZ
CCH
CCLVCC
I
CCZ
OS
= MAX 160 210 mA
= MAX 110 155 mA
, the use of high-speed test apparatus and/or sample-and-hold
125 165 mA
135 160 mA
100 145 mA
105 155 mA
µA
µA
1990 Sep 25
7
Philips Semiconductors Product specification
74F646/A/74F648/ATransceivers/registers
AC ELECTRICAL CHARACTERISTICS FOR 74F646
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST CONDITION VCC = +5.0V
CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
Maximum clock frequency Waveform 1 100 115 90 MHz
Propagation delay
CPAB or CPBA to An or Bn
Propagation delay
An to Bn or Bn to An
Propagation delay
SAB or SBA to An or Bn
Output enable time
OE to An or Bn
Output enable time
DIR to An or Bn
Output disable time
OE to An or Bn
Output disable time
DIR to An or Bn
Waveform 1
Waveform 2
Waveform 2, 3
Waveform 5
Waveform 6
Waveform 5
Waveform 6
Waveform 5
Waveform 6
Waveform 5
Waveform 6
5.5
5.5
4.0
4.0
5.0
5.0
5.0
6.5
4.5
6.0
6.5
6.5
5.5
5.5
7.5
8.0
6.0
6.5
7.0
6.5
7.0
8.5
6.5
8.5
9.0
9.0
8.5
8.5
10.0
10.0
9.0
8.0
8.5
8.5
10.0
11.0
9.0
11.0
11.5
11.5
11.0
11.0
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
5.0
5.0
4.0
4.0
4.5
4.5
4.5
6.0
4.0
5.5
6.0
6.0
4.5
5.0
11.5
11.0
10.0
10.0
10.5
9.5
11.0
12.5
10.0
12.5
12.5
13.5
13.0
12.5
UNIT
ns
ns
ns
ns
ns
ns
ns
AC SETUP REQUIREMENTS FOR 74F646
T
= +25°C T
amb
SYMBOL PARAMETER TEST CONDITION VCC = +5.0V
CL = 50pF, RL = 500Ω CL= 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
t
(H)
su
t
(L)
su
t
(H)
h
t
(L)
h
t
(H)
w
t
(L)
w
Setup time, high or low
An or Bn to CPAB or CPBA
Hold time, high or low
An or Bn to CPAB or CPBA
Pulse width, high or low
CPAB or CPBA
Waveform 4
Waveform 4
Waveform 1
4.5
4.5
0
0
4.0
6.0
LIMITS
amb
VCC = +5.0V ± 10%
5.0
5.0
4.0
6.0
= 0°C to +70°C
0
0
UNIT
ns
ns
ns
1990 Sep 25
8
Philips Semiconductors Product specification
74F646/A/74F648/ATransceivers/registers
AC ELECTRICAL CHARACTERISTICS FOR 74F648
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST CONDITION VCC = +5.0V
CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
Maximum clock frequency Waveform 1 100 115 90 MHz
Propagation delay
CPAB or CPBA to An or Bn
Propagation delay
An to Bn or Bn to An
Propagation delay
SAB or SBA to An or Bn
Output enable time
OE to An or Bn
Output enable time
DIR to An or Bn
Output disable time
OE to An or Bn
Output disable time
DIR to An or Bn
Waveform 1
Waveform 3
Waveform 2,3
Waveform 5
Waveform 6
Waveform 5
Waveform 6
Waveform 5
Waveform 6
Waveform 5
Waveform 6
5.0
5.0
3.0
4.0
4.5
4.5
4.5
6.0
4.5
6.0
6.0
6.0
5.0
5.0
7.0
7.5
6.0
6.0
7.0
6.5
7.0
8.5
7.0
8.5
9.0
8.5
9.0
9.0
9.5
9.5
8.5
8.5
8.5
8.5
10.0
11.0
10.0
11.0
11.5
12.0
12.5
12.5
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
4.5
4.5
2.5
3.5
4.5
4.5
4.5
5.5
4.0
5.5
6.0
6.0
4.5
5.0
11.0
11.0
9.5
9.5
10.5
9.5
11.0
12.5
11.0
12.5
12.5
13.5
14.0
14.0
UNIT
ns
ns
ns
ns
ns
ns
ns
AC SETUP REQUIREMENTS FOR 74F648
T
= +25°C T
amb
SYMBOL PARAMETER TEST CONDITION VCC = +5.0V
C
= 50pF, RL = 500Ω C
L
MIN TYP MAX MIN MAX
t
(H)
su
t
(L)
su
t
(H)
h
t
(L)
h
t
(H)
w
t
(L)
w
Setup time, high or low
An or Bn to CPAB or CPBA
Hold time, high or low
An or Bn to CPAB or CPBA
Pulse width, high or low
CPAB or CPBA
Waveform 4
Waveform 4
Waveform 1
4.0
4.0
0
0
3.5
6.5
LIMITS
amb
VCC = +5.0V ± 10%
= 50pF, RL = 500Ω
L
5.0
5.0
4.0
7.0
= 0°C to +70°C
0
0
UNIT
ns
ns
ns
1990 Sep 25
9
Philips Semiconductors Product specification
74F646/A/74F648/ATransceivers/registers
AC ELECTRICAL CHARACTERISTICS FOR 74F646A
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST CONDITION VCC = +5.0V
CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
Maximum clock frequency Waveform 1 165 185 150 MHz
Propagation delay
CPAB or CPBA to An or Bn
Propagation delay
An to Bn or Bn to An
Propagation delay
SAB or SBA to An or Bn
Output enable time
OE to An or Bn
Output enable time
DIR to An or Bn
Output disable time
OE to An or Bn
Output disable time
DIR to An or Bn
Waveform 1
Waveform 2
Waveform 2, 3
Waveform 5
Waveform 6
Waveform 5
Waveform 6
Waveform 5
Waveform 6
Waveform 5
Waveform 6
5.5
4.5
4.0
2.0
4.5
3.5
3.0
3.0
3.0
3.5
1.5
2.5
2.0
3.0
7.0
7.0
6.0
5.0
6.5
8.0
5.5
5.5
5.0
6.0
4.0
5.5
4.5
5.0
10.5
9.5
9.0
8.0
9.5
10.0
9.0
10.0
8.0
8.5
6.5
8.0
7.5
8.0
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
4.5
4.0
3.5
2.0
4.0
3.0
2.5
2.5
3.0
3.0
1.0
2.0
1.5
2.0
11.0
10.0
10.0
8.0
10.0
11.5
10.0
10.5
8.5
9.5
8.0
9.5
8.5
8.5
UNIT
ns
ns
ns
ns
ns
ns
ns
AC SETUP REQUIREMENTS FOR 74F646A
T
= +25°C T
amb
SYMBOL PARAMETER TEST CONDITION VCC = +5.0V
CL = 50pF, RL = 500Ω C
MIN TYP MAX MIN MAX
t
(H)
su
t
(L)
su
t
(H)
h
t
(L)
h
t
(H)
w
t
(L)
w
Setup time, high or low
An or Bn to CPAB or CPBA
Hold time, high or low
An or Bn to CPAB or CPBA
Pulse width, high or low
CPAB or CPBA
Waveform 4
Waveform 4
Waveform 1
3.5
4.0
0
0
3.5
3.5
LIMITS
amb
VCC = +5.0V ± 10%
= 50pF, RL = 500Ω
L
4.0
4.5
4.5
4.0
= 0°C to +70°C
0
0
UNIT
ns
ns
ns
1990 Sep 25
10
Philips Semiconductors Product specification
74F646/A/74F648/ATransceivers/registers
AC ELECTRICAL CHARACTERISTICS FOR 74F648A
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST CONDITION VCC = +5.0V
CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
Maximum clock frequency Waveform 1 160 185 135 ns
Propagation delay
CPAB or CPBA to An or Bn
Propagation delay
An to Bn or Bn to An
Propagation delay
SAB or SBA to An or Bn
Output enable time
OE to An or Bn
Output enable time
DIR to An or Bn
Output disable time
OE to An or Bn
Output disable time
DIR to An or Bn
Waveform 1
Waveform 3
Waveform 2, 3
Waveform 5
Waveform 6
Waveform 5
Waveform 6
Waveform 5
Waveform 6
Waveform 5
Waveform 6
5.0
5.5
2.5
4.0
4.0
4.5
3.5
4.5
3.5
4.0
2.5
4.0
2.5
2.5
7.0
7.5
4.5
6.0
7.0
7.0
6.5
6.5
5.5
6.5
4.0
6.5
5.0
5.0
9.5
10.0
7.5
8.5
9.5
9.5
10.0
10.0
8.5
9.5
6.5
9.0
8.5
8.0
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
4.5
4.5
2.0
4.0
3.5
4.5
3.5
4.0
3.0
4.0
2.0
3.5
2.0
3.5
10.5
10.5
8.5
9.5
11.5
10.0
11.0
11.5
9.0
10.0
8.0
10.0
9.0
9.0
UNIT
ns
ns
ns
ns
ns
ns
ns
AC SETUP REQUIREMENTS FOR 74F648A
T
= +25°C T
amb
SYMBOL PARAMETER TEST CONDITION VCC = +5.0V
CL = 50pF, RL = 500Ω C
MIN TYP MAX MIN MAX
t
(H)
su
t
(L)
su
t
(H)
h
t
(L)
h
t
(H)
w
t
(L)
w
Setup time, high or low
An or Bn to CPAB or CPBA
Hold time, high or low
An or Bn to CPAB or CPBA
Pulse width, high or low
CPAB or CPBA
Waveform 4
Waveform 4
Waveform 1
4.0
4.0
0
0
3.5
3.5
AC WAVEFORMS
1/f
CPBA
or
CPAB
An or Bn
V
M
t
PHL
tw(H)
max
V
M
tw(L)
V
M
V
M
t
PLH
V
M
SF00394
Waveform 1. Propagation delay for clock input to output clock
pulse width, and maximum clock frequency
An or Bn
Bn or An
Waveform 2. Propagation delay for An to Bn or Bn to An and
LIMITS
= 0°C to +70°C
amb
VCC = +5.0V ± 10%
= 50pF, RL = 500Ω
L
4.5
4.5
0
0
4.0
3.5
V
M
t
PHL
V
M
V
M
SAB or SBA to An or Bn
t
PLH
V
M
UNIT
ns
ns
ns
SBA or SAB
An or Bn
SF00395
1990 Sep 25
11
Philips Semiconductors Product specification
74F646/A/74F648/ATransceivers/registers
AC WAVEFORMS (Continued)
t
PHL
V
M
SBA or SAB
An or Bn
SF00396
An or Bn
Bn or An
V
t
PLH
M
V
M
V
M
Waveform 3. Propagation delay for An to Bn or Bn to An and
SAB or SBA to An or Bn
An or Bn
CPBA
CPAB
or
V
M
t
(H) th(H)
su
V
M
V
M
V
V
M
tsu(L) th(L)
V
M
M
SF00397
Waveform 4. Data setup time and hold times
OE
DIR
An or Bn
Waveform 5. 3-state output enable time to high level and
OE
DIR
An or Bn
Waveform 6. 3-state output enable time to low level and output
V
t
PZH
M
V
V
M
t
PHZ
M
output disable time from high level
V
t
PZL
M
V
V
M
t
PLZ
M
disable time from low level
VOH -0.3V
0V
SF00398
3.5V
VOL +0.3V
SF00399
NOTES:
1. For all waveforms, V
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
= 1.5V.
M
TEST CIRCUIT AND WAVEFORM
V
CC
R
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
L
C
R
L
L
Test Circuit for Open Collector Outputs
SWITCH POSITION
TEST SWITCH
t
t
PLZ
PZL
closed
closed
All other open
DEFINITIONS:
= Load resistor;
R
L
see AC electrical characteristics for value.
C
= Load capacitance includes jig and probe capacitance;
L
see AC electrical characteristics for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
of
7.0V
NEGATIVE
PULSE
POSITIVE
PULSE
family
74F
90%
10%
amplitude
V
M
10%
t
THL (tf
t
TLH (tr
90%
V
M
Input Pulse Definition
INPUT PULSE REQUIREMENTS
V
3.0V
1.5V
t
)
)
t
rep. rate
M
1MHz 500ns
w
V
M
10%
)
t
TLH (tr
t
)
THL (tf
90%
V
M
w
t
t
TLHtTHL
w
90%
10%
AMP (V)
0V
AMP (V)
0V
2.5ns 2.5ns
SF00128
1990 Sep 25
12
Philips Semiconductors Product specification
Transceivers/registers
DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1
74F646/A/74F648/A
1990 Sep 25
13
Philips Semiconductors Product specification
Transceivers/registers
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
74F646/A/74F648/A
1990 Sep 25
14
Philips Semiconductors Product specification
Transceivers/registers
74F646/A/74F648/A
NOTES
1990 Sep 25
15
Philips Semiconductors Product specification
Transceivers/registers
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
74F646/A/74F648/A
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05151
yyyy mmm dd
16
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