Page 1
74F195A
4-bit parallel-access shift register
Product specification
IC15 Data Handbook
1996 Mar 12
INTEGRATED CIRCUITS
Page 2
Philips Semiconductors Product specification
74F195A4-bit parallel-access shift register
2
1996 Mar 12 853-0024 16555
FEA TURES
•Shift right and parallel load capability
•J – K (D) inputs to first stage
•Complement output from last stage
•Asynchronous Master Reset
•Diode inputs
DESCRIPTION
The 74F195A is a 4-Bit Parallel Access Shift Register and its
functional characteristics are indicated in the Logic Diagram and
Function Table. This device is useful in a variety of shifting, counting
and storage applications. It performs serial, parallel, serial to
parallel, or parallel to serial data transfers at very high speeds.
The 74F195A operates in two primary modes: shift right (Q0→Q1)
and parallel load, which are controlled by the state of the Parallel
Enable (PE
) input. Serial data enters the first flip-flop (Q0) via the J
and K
inputs when the PE input is High, and is shifted one bit in the
direction Q0→Q1→Q2→Q3 following each Low-to-High clock
transition.
The J and K
inputs provide the flexibility of the J-K type input for
special applications, and by tying the two together the simple D-type
input is made for general applications.
The device appears as four common clocked D flip-flops when the
PE
input is Low. After the Low-to-High clock transition, data on the
parallel inputs (D0–D3) is transferred to the respective Q0–Q3
outputs. Shift left operation (Q3–Q2) can be achieved by tying the
Qn outputs to the Dn-1 inputs and holding the PE
input Low.
All parallel and serial data transfers are synchronous, occurring after
each Low-to-High clock transition. The 74F195A utilizes
edge-triggering, therefore there is no restriction on the activity of the
J, K
, Dn, and PE inputs for logic operation, other than the set-up and
hold time requirements.
A Low on the asynchronous Master Reset (MR
) input sets all Q
outputs Low, independent of any other input condition.
PIN CONFIGURATION
16
15
14
13
12
11
107
6
5
4
3
2
1
V
CC
Q3
CP
Q3
Q2
Q0
Q1
MR
J
D3
D0
D1
D2
98GND PE
SF00757
K
TYPE TYPICAL f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F195A 180MHz 40mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
T
amb
= 0°C to +70°C
PKG. DWG. #
16-pin plastic DIP N74F195AN SOT 38-4
16-pin plastic SO N74F195AD SOT 109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE HIGH/LOW
p
74F195 1.0/0.033 20µA/20µA
D0–D3
Data inputs
74F195A 1.0/1.0 20µA/0.6mA
p
p
74F195 1.0/0.033 20µA/20µA
J, K
J-K or D type serial inputs
74F195A 1.0/1.0 20µA/0.6mA
p
74F195 1.0/0.033 20µA/20µA
CP
Clock Pulse input (active rising edge)
74F195A 1.0/1.0 20µA/0.6mA
p
74F195 2.0/0.066 40µA/40µA
MR
Master Reset input (active Low)
74F195A 1.0/1.0 20µA/0.6mA
Q0–Q3,
Q3
Data outputs 50/33 1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
Page 3
Philips Semiconductors Product specification
74F195A4-bit parallel-access shift register
1996 Mar 12
3
LOGIC SYMBOL
Q0 Q1
Q2 Q3
15 14
13 12
V
CC
= Pin 16
GND = Pin 8
9
2
10
3
PE
J
CP
K
D1 D2
56
SF00758
D3D0
4
7
1MR
11Q3
IEC/IEEE SYMBOL
SF00759
7
3
4
5
6
2
10
9
M1
SRG4
C2/1
1, 2J
1, 2K
1, 2D
15
13
1
R
14
1, 2D
12
11
LOGIC DIAGRAM
CP
10
PE
9
J
2
S
CP
R
Q0
15
SF00760
VCC = Pin 16
GND = Pin 8
R
D
Q
Q
3
K
MR
D0
D1
D2
D3
S
CP
R
Q1
14
R
D
Q
S
CP
R
Q2
13
R
D
Q
S
CP
R
Q3
12
R
D
Q
Q
Q3
11
1
4
5
6
7
Page 4
Philips Semiconductors Product specification
74F195A4-bit parallel-access shift register
1996 Mar 12
4
FUNCTION TABLE
INPUTS OUTPUTS
MR CP PE J K Dn Q0 Q1 Q2 Q3 Q3
OPERATING MODES
L X X X X X L L L L H Reset (clear)
H ↑ h h h X H q0 q1 q2 q2 Shift, set First stage
H ↑ h l l X L q0 q1 q2 q2 Shift, reset First stage
H ↑ h h l X q0 q0 q1 q2 q2 Shift, toggle First stage
H ↑ h l h X q0 q0 q1 q2 q2 Shift, retain First stage
H = High voltage level
h = High voltage level one setup time prior to Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL PARAMETER RATING UNIT
V
CC
Supply voltage –0.5 to +7.0 V
V
IN
Input voltage –0.5 to +7.0 V
I
IN
Input current –30 to +5 mA
V
OUT
Voltage applied to output in High output state –0.5 to +V
CC
V
I
OUT
Current applied to output in Low output state 40 mA
T
amb
Operating free-air temperature range 0 to +70 °C
T
stg
Storage temperature –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5.0 5.5 V
V
IH
High-level input voltage 2.0 V
V
IL
Low-level input voltage 0.8 V
I
IK
Input clamp current –18 mA
I
OH
High-level output current –1 mA
I
OL
Low-level output current 20 mA
T
amb
Operating free-air temperature range 0 70 °C
Page 5
Philips Semiconductors Product specification
74F195A4-bit parallel-access shift register
1996 Mar 12
5
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL PARAMETER TEST CONDITIONS
NO TAG
MIN
TYP
NO TAG
MAX
UNIT
p
VCC = MIN, VIL = MAX
±10%V
CC
2.5 V
VOHHigh-level output voltage
CC
,
IL
VIH = MIN, IOH = MAX
±5%V
CC
2.7 3.4 V
p
VCC = MIN, VIL = MAX
±10%V
CC
0.35 0.50
VOLLow-level output voltage
CC
,
IL
VIH = MIN, IOL = MAX
±5%V
CC
0.35 0.50
V
V
IK
Input clamp voltage VCC = MIN, II = I
IK
–0.73 –1.2 V
I
I
Input current at maximum input voltage VCC = MAX, VI = 7.0V 74F195A 100 µA
I
IH
High-level input current VCC = MAX, VI = 2.7V all others 20 µA
I
IL
Low-level input current VCC = MAX, VI = 0.5V 74F195A –600 mA
I
OS
Short-circuit output current
3
VCC = MAX –60 –150 mA
I
CC
Supply current (total) VCC = MAX 74F195A 40 58 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER
TEST
CONDITION
VCC = +5V
T
amb
= +25°C
C
L
= 50pF, RL = 500Ω
VCC = +5V ± 10%
T
amb
= 0°C to +70°C
C
L
= 50pF, RL = 500Ω
UNIT
MIN TYP MAX MIN MAX
Maximum clock
Load mode
Waveform
165 180 150
f
MAX
frequency
Shift mode
NO TAG
180 190 170
MH
z
t
PLH
t
PHL
Propagation delay
CP to Qn
Waveform
NO TAG
3.0
2.5
5.0
4.0
9.5
7.0
2.5
2.0
10.0
7.5
ns
t
PLH
t
PHL
Propagation delay
CP to Q3
Waveform
NO TAG
2.0
2.0
5.5
4.0
9.5
6.5
2.5
2.0
9.5
7.0
ns
t
PHL
Propagation delay
MR to Qn
Waveform 2 2.0 4.0 7.0 2.0 7.0 ns
t
PLH
Propagation delay
MR to Q3
Waveform 2 2.5 4.5 8.0 2.0 10.0 ns
Page 6
Philips Semiconductors Product specification
74F195A4-bit parallel-access shift register
1996 Mar 12
6
AC SETUP REQUIREMENTS
LIMITS
SYMBOL PARAMETER
TEST
CONDITION
VCC = +5V
T
amb
= +25°C
C
L
= 50pF, RL = 500Ω
VCC = +5V ± 10%
T
amb
= 0°C to +70°C
C
L
= 50pF, RL = 500Ω
UNIT
MIN TYP MAX MIN MAX
tS(H)
tS(L)
Setup time, High or Low
J, K and Dn to CP
Waveform 3
2.5
2.5
2.5
2.5
ns
th(H)
th(L)
Hold time, High or Low
J, K and Dn to CP
Waveform 3
0.0
1.0
0.0
1.0
ns
tS(H)
tS(L)
Setup time, High or Low
PE to CP
Waveform 4
2.0
2.5
2.0
2.5
ns
th(H)
th(L)
Hold time, High or Low
PE to CP
Waveform 4
0.0
0.0
0.0
0.0
ns
tW(H)
CP Pulse width
High
Waveform
NO TAG
4.5 4.5 ns
tW(L)
MR Pulse width
Low
Waveform 2 4.5 4.5 ns
t
REC
Recovery time
MR to CP
Waveform 2 2.5 3.0 ns
AC WAVEFORMS
For all waveforms, VM = 1.5V .
The shaded areas indicate when the input is permitted to change for predictable output performance.
t
PHL
t
PLH
CP
V
M
V
M
V
M
tw(H)
1/f
max
V
M
V
M
t
PLH
Q3
V
M
V
M
Qn
t
PHL
SF00761
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
th(H)ts(H)
CP
SF00763
V
M
V
M
V
M
V
M
V
M
V
M
th(L)ts(L)
J, K
,
Dn
Waveform 2. Data Setup and Hold Times
CP
V
M
V
M
V
M
V
M
t
PHL
t
rec
MR
Qn
t
w
(L)
V
M
Q3
t
PLH
SF00762
Waveform 3. Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Clock Recovery T ime
CP
V
MVM
V
M
V
M
V
M
V
M
PE
Qn
t
s
(H)
SF00764
t
h
ts(L)
RESPONSE Qn=Qn–1 Qn=Dn
SERIAL-SHIFT RIGHT PARALLEL LOAD
t
h
Waveform 4. Setup and Hold Times, Parallel Enable to Clock
Page 7
Philips Semiconductors Product specification
74F195A4-bit parallel-access shift register
1996 Mar 12
7
TEST CIRCUIT AND WAVEFORMS
t
w
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
NEGATIVE
PULSE
POSITIVE
PULSE
t
w
AMP (V)
0V
0V
t
THL (tf
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
TLHtTHL
1MHz 500ns
2.5ns 2.5ns
Input Pulse Definition
V
CC
family
74F
D.U.T.
PULSE
GENERATOR
R
L
C
L
R
T
V
IN
V
OUT
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
R
T
= T ermination resistance should be equal to Z
OUT
of
pulse generators.
t
THL (tf
)
t
TLH (tr
)
t
TLH (tr
)
AMP (V)
amplitude
3.0V
1.5V
V
M
SF00006
Page 8
Philips Semiconductors Product specification
74F195A
4-bit parallel-access shift register
1996 Mar 12
8
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
Page 9
Philips Semiconductors Product specification
74F195A
4-bit parallel-access shift register
1996 Mar 12
9
NOTES
Page 10
Philips Semiconductors Product specification
74F195A
4-bit parallel-access shift register
yyyy mmm dd
10
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05096
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
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