Datasheet N74F194D, N74F194N Datasheet (Philips)

INTEGRATED CIRCUITS

74F194

4-bit bidirectional universal shift register

Product specification
IC15 Data Handbook




1989 Apr 04

Philips Semiconductors Product specification

74F1944-bit bidirectional universal shift register

FEA TURES

•Shift right and shift left capability

•Synchronous parallel and serial data transfer

•Easily expanded for both serial and parallel operation

•Asynchronous Master Reset

•Hold (do nothing) mode

DESCRIPTION

The functional characteristics of the 74F194 4-Bit Bidirectional Shift
Register are indicated in the Logic Diagram and Function Table. The
register is fully synchronous, with all operations taking place in less
than 9ns (typical) for 74F, making the device especially useful for
implementing very high speed CPUs, or for memory buffer registers.

The 74F194 design has special logic features which increase the
range of application. The synchronous operation of the device is
determined by two Mode Select inputs, S0 and S1. As shown in the
Mode Select-Function Table, data can be entered and shifted from
left to right (shift right, Q0→Q1, etc.), or right to left (shift left,
Q3→Q2, etc.), or parallel data can be entered, loading all 4 bits of
the register simultaneously. When both S0 and S1 are Low, existing
data is retained in a hold (do nothing) mode. The first and last
stages provide D-type Serial Data inputs (D
multistage shift right or shift left data transfers without interfering
with parallel load operation. Mode Select and data inputs on the
74F194 are edge-triggered, responding only to the Low-to-High
transition of the Clock (CP). Therefore, the only timing restriction is
that the Mode Select and selected data inputs must be stable one
setup time prior to the Low-to-High transition of the clock pulse.
Signals on the Mode Select, Parallel Data (D0–D3) and Serial Data
(D

, DSL) can change when the clock is in either state, provided

SR

only the recommended setup and hold times, with respect to the
clock rising edge, are observed. The four Parallel Data inputs
(D0–D3) are D-type inputs. Data appearing on (D0–D3) inputs when
S0 and S1 are High is transferred to the Q0–Q3 outputs
respectively, following the next Low-to-High transition of the clock.
When Low, the asynchronous Master Reset (MR
input conditions and forces the Q outputs Low.

, DSL) to allow

SR

) overrides all other

PIN CONFIGURATION

MR

1

D

2

SR

D0

3

D1

4

D2

5

D3

6

D

SL

TYPE TYPICAL f

MAX

74F194 150MHz 33mA

16

V

CC

Q0

15

Q1

14

Q2

13

Q3

12

CP

11

S1

107

98GND S0

SF00167

TYPICAL

SUPPLY CURRENT

(TOTAL)

ORDERING INFORMATION

COMMERCIAL RANGE

DESCRIPTION

16-pin plastic DIP N74F194N SOT38-4

16-pin plastic SO N74F194D SOT109-1

VCC = 5V ±10%,

T

= 0°C to +70°C

amb

PKG DWG #

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW

D0–D3 Parallel data inputs 1.0/1.0 20µA/0.6mA

D

SR

D

SL

S0, S1 Mode Select inputs 1.0/1.0 20µA/0.6mA

CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
MR Asynchronous master Reset input (Active Low) 1.0/1.0 20µA/0.6mA

Q0–Q3 Data outputs 50/33 1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

April 4, 1989 853–0354 96224

Serial data input (Shift Right) 1.0/1.0 20µA/0.6mA
Serial data input (Shift Left) 1.0/1.0 20µA/0.6mA

2

Philips Semiconductors Product specification

74F1944-bit bidirectional universal shift register

LOGIC SYMBOL

9
10
11

1

V

= Pin 24

CC

GND = Pin 12

LOGIC DIAGRAM

10

S1

9

S0

7

D

SL

6

D3

S0
S1
CP

MR

D

2

SR

34

D1 D2

Q0 Q1

15 14

56

D3D0

Q2 Q3

13 12

7

D

SL

SF00168

IEC/IEEE SYMBOL

1

9
10
11

2

3

4

5

6

7

R
0

M

1

C4
1 → /2 ←

1, 4D
3, 4D
3, 4D
3, 4D
3, 4D
2, 4D

SRG8

0
3

S

CP

R

15

14
13

12

SF00169

Q3

R

D

12

Q3

D

MR

VCC = Pin 24
GND = Pin 12

CP

13

14

15

SF00170

Q2

Q1

Q0

S

Q2

5

D2

4

D1

3

D0

2

SR

1

11

CP

R

S

CP

R

S

CP

R

R

D

Q1

R

D

Q0

R

D

April 4, 1989

3

Philips Semiconductors Product specification

OPERATING MODES

Shift left

Shift right

SYMBOL

PARAMETER

UNIT

74F1944-bit bidirectional universal shift register

FUNCTION TABLE

INPUTS OUTPUTS

CP MR S1 S0 D

X L X X X X X L L L L Reset (clear)
X H l l X X X q0 q1 q2 q3 Hold (do nothing)

↑ H h l X l X q1 q2 q3 L
↑ H h l X h X q1 q2 q3 H
↑ H l h l X X L q0 q1 q2
↑ H l h h X X H q0 q1 q2
↑ H h h X X dn d0 d1 d2 d3 Parallel load

H = High voltage level
h = High voltage level one setup time prior to Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition.

SR

D

SL

Dn Q0 Q1 Q2 Q3

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL PARAMETER RATING UNIT

V
V
I

IN

V
I

OUT

T
T

CC
IN

OUT

amb
stg

Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in High output state –0.5 to V

CC

Current applied to output in Low output state 40 mA
Operating free-air temperature range 0 to +70 °C
Storage temperature range –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

LIMITS

MIN NOM MAX

V
V
V
I
I
I
T

CC
IH

IL
IK
OH
OL

amb

Supply voltage 4.5 5.0 5.5 V
High-level input voltage 2.0 V
Low-level input voltage 0.8 V
Input clamp current –18 mA
High-level output current –1 mA
Low-level output current 20 mA
Operating free-air temperature range 0 +70 °C

V

April 4, 1989

4

Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITIONS

1

UNIT

VOHHigh-level output voltage

3

V

VOLLow-level output voltage

V

74F1944-bit bidirectional universal shift register

DC ELECTRICAL CHARACTERISTICS

LIMITS

MIN TYP

p

p

V

IK

I

I

I

IH

I

IL

I

OS

I

CC

Input clamp voltage VCC = MIN, II = I
Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA
High-level input current VCC = MAX, VI = 2.7V 20 µA
Low-level input current VCC = MAX, VI = 0.5V –0.6 mA
Short-circuit output current
Supply current (total)

4

5

VCC = MIN, VIL = MAX ±10%V
VIH = MIN, IOH = MAX ±5%V

CC

VCC = MIN, VIL = MAX ±10%V
VIH = MIN, IOL = MAX ±5%V

IK

CC

VCC = MAX –60 –150 mA
VCC = MAX 33 46 mA

CC

CC

2.5

2.7 3.4

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Output High state will change to Low stat if an external voltage of less than 0.0V is applied.

= 5V, T

CC

4. Not more than one output should be shorted at a time. For testing I
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

amb

= 25°C.

, the use of high-speed test apparatus and/or sample-and-hold

OS

of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I

5. With all outputs open, D
then 4.5V applied to CP.

inputs grounded and a 4.5V applied to S0, S1, MR and the serial inputs, ICC is tested with a momentary ground,

i

tests should be performed last.

OS

2

MAX

0.30 0.50

0.30 0.50

–0.73 –1.2 V

AC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER

TEST

CONDITION

VCC = +5.0V

T

= +25°C

amb

= 50pF, RL = 500Ω

C

L

VCC = +5.0V ± 10%

T

= 0°C to +70°C

amb

= 50pF, RL = 500Ω

C

L

MIN TYP MAX MIN MAX

f

MAX

t

PLH

t

PHL

t

PHL

Maximum clock frequency Waveform 1 105 150 90 MHz

Propagation delay
CP to Qn

Propagation delay
MR to Qn

Waveform 1

Waveform 2 4.5 8.6 12.0 4.5 14.0 ns

3.5

3.5

5.2

5.5

7.0

7.0

3.5

3.5

8.0

8.0

AC SETUP REQUIREMENTS

LIMITS

SYMBOL PARAMETER

TEST

CONDITION

VCC = +5.0V

T

= +25°C

amb

= 50pF, RL = 500Ω

C

L

MIN TYP MAX MIN MAX

tS(H)
tS(L)

th(H)
t

(L)

h

tS(H)
tS(L)

th(H)
th(L)

Setup time, High or Low
Dn, DSL, DSR to CP

Hold time, High or Low
Dn, D

, DSR to CP

SL

Setup time, High or Low
Sn to CP

Hold time, High or Low
Sn to CP

Waveform 3

Waveform 3

Waveform 3

Waveform 3

4.0

4.0
0

0

8.0

8.0
0

0

tW(H) CP Pulse width, High Waveform 1 5.0 5.5 ns
tW(L) MR Pulse width, Low Waveform 2 5.0 5.0 ns
t

REC

Recovery time, MR to CP Waveform 2 7.0 8.0 ns

VCC = +5.0V ± 10%

T

= 0°C to +70°C

amb

= 50pF, RL = 500Ω

C

L

4.0

4.0

1.0

1.0

9.0

8.0
0

0

UNIT

ns

UNIT

ns

ns

ns

ns

April 4, 1989

5

Philips Semiconductors Product specification

74F1944-bit bidirectional universal shift register

AC WAVEFORMS

For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.

1/f

MAX

CP

Qn

V

M

t

PHL

tw(H)

V

M

V

M

V

M

t

PLH

V

M

SF00171

Waveform 1. Propagation Delay, Clock Input to Output,

Clock Pulse Width, and Maximum Clock Frequency

Dn, D

,

SR

D

S0, S1

CP

V

V

M

SL

M

th(H)ts(H)

V

M

V

V

M

M

th(L)ts(L)

V

M

SF00172

Waveform 3. Setup and Hold Times

TIMING DIAGRAM

Typical Clear, Load, Shift-Right, Shift-Left and Inhibit Sequence

MR

CP

Qn

V

M

tw(L)

t

PHL

V

M

V

M

t

REC

V

M

SF00158

Waveform 2. Master Reset Pulse Width, Master Reset to

Output Delay, and Master Reset to Clock Recovery T ime

SERIAL

DATA

INPUTS

PARALLEL

DATA

INPUTS

OUTPUTS

CP

S0
S1

MR

D

SR

D

SL

D0
D1
D2
D3

Q0
Q1
Q2
Q3

CLEAR LOAD

H
L

H
L

SHIFT RIGHT

SHIFT LEFT

INHIBIT

CLEAR

SF00173

April 4, 1989

6

Philips Semiconductors Product specification

74F1944-bit bidirectional universal shift register

TEST CIRCUIT AND WAVEFORMS

V

CC

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

R

C

L

L

Test Circuit for Totem-Pole Outputs

DEFINITIONS:

= Load resistor;

R

L

see AC ELECTRICAL CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC ELECTRICAL CHARACTERISTICS for value.

R

= T ermination resistance should be equal to Z

T

pulse generators.

OUT

of

NEGATIVE
PULSE

POSITIVE
PULSE

family

74F

90%

10%

amplitude

t

w

V

M

10%

)

V

90%

M

t

THL (tf

t

TLH (tr

)

t

TLH (tr

t

THL (tf

t

w

Input Pulse Definition

INPUT PULSE REQUIREMENTS

V

rep. rate

M

3.0V

1.5V

1MHz 500ns

10%

)

)

90%

t

w

V

M

V

M

90%

10%

t

TLHtTHL

2.5ns 2.5ns

AMP (V)

0V

AMP (V)

0V

SF00006

April 4, 1989

7

Philips Semiconductors Product specification

4-bit bidirectional universal shift register

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

74F194

1989 Apr 04

8

Philips Semiconductors Product specification

4-bit bidirectional universal shift register

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74F194

1989 Apr 04

9

Philips Semiconductors Product specification

4-bit bidirectional universal shift register

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

74F194

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 10-98
Document order number: 9397-750-05095




yyyy mmm dd

10