Datasheet MX98715AEC-E Datasheet (MXIC)

1. INTRODUCTION

PRELIMINARY

MX98715AEC-E

APPLICATION NOTE

The purpose of this application note is to describe the
implementation of a PCI bus master 100 Base-TX F ast
Ethernet node using MXIC’ highly integrated single chip
Fast Ethernet NIC controller MX98715AEC-E. In de­tails, this document presents product overview , program­ming guide, hardware design and layout recommenda­tions that can help you to quickly and smoothly imple­ment a Fast Ethernet adapter card.

As you can find in the MX98715AEC-E driver diskette,

2. PRODUCT OVERVIEW

The MX98715AEC-E implements the 10/100Mbps MAC
layer and Physical layer on a single chip in accordance
with the IEEE 802.3 standard.

The MX98715AEC-E highly integrates with direct PCI
bus interface, including PCI bus master with DMA chan­nel capability, direct EEPROM as well as Boot ROM
interface, and large on chip transmit/receiv e FIFOs. Also ,
the MX98715AEC-E is equipped with intelligent

MXIC already provided a complete set of high quality
drivers for easier and more efficient way to interface with
MX98715AEC-E on the most popular Network Operat­ing Systems. Nevertheless, there are still some special
applications or environment not covered in the
MX98715AEC-E driver diskette. Driver developers, how­ever, could still refer to the section of driver program­ming guide to accomplish the required driver. It is rec­ommended that you are familiar with the MX98715AEC­E data sheet before reading this guide.

IEEE802.3u-compliant Nway auto-negotiation capability
allowing a single RJ-45 connector to link with the other
IEEE802.3u-compliant device without re-configuration.
T o optimiz e operating bandwidth, network data integrity
and throughput, the proprietary Adaptive Network
Throughput Control (ANTC) function is implemented. For
detailed product specification information, please refer
to the MX98715AEC-E data sheet.

3. HARDWARE DESIGN CONSIDERATIONS

3.1 SYSTEM APPLICA TION BLOCK DIAGRAM

A system block diagram for the MX98715AEC-E based
Fast Ethernet adapter card is shown as f ollowing:

PCI Bus

Osc or Crystal

25MHz

EEPROM

MX98715AEC-E

Fig. 1

Boot ROM

LED

Magnetic

RJ45

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MX98715AEC-E

3.2 PCI CONNECTION

The MX98715AEC-E provides direct PCI bus interface
to PCI connector. Board designers should especially
take care of the four pins of TDI,TDO,PRSNT1# &
PRSNT2# that are only related to PCI bus connector.
Boards that do not implement JTAG Boundary Scan
should tight TDI and TDO together to prevent the scan
chain from been broken.

Both pins PRSNT1# and PRSNT2# should be connected
to ground indicating that the board is physically present­ing in a PCI slot and providing information about the
total power requirements ( less than 7.5W ) of the board.

3.3 OSCILLA TOR OR CR YST AL

The MX98715AEC-E is designed to operate with a 25MHz
oscillator or crystal module. The clock specification of
this oscillator should meet 25MHz +/- 50PPM.

3.4 BOOT R OM

The MX98715AEC-E support a direct boot ROM inter­face allowing diskless workstations to remotely down­load operating system from network server. F or proper
operation, the access time of adapt EPROM should not
excess 240ns.

ing indicates the configuration setting table for LED dis­play programming.

CSR9 <28:29> LED0 LED1
0 0 Activity Goodlink
11 Link speed Link Activity

3.7 NETWORK INTERF ACE TO MA GNETIC
COMPONENT

For isolating and impedance matching purpose, an iso­lating transformer with 1:1 transmit and 1:1 receive turns
ratio is required for transmit and receive twisted pair in­terface. In Appendix B, several transformers that we had
verified successfully with MX98715AEC-E are listed for
quick reference purpose.

3.8 OPTIMIZED EQUALIZER COMPONENTS

M XI C ’ Fast Ethernet solution utilizes adaptive equal­izer to compensate the attenuation and phase distortion
induced by different lengths of cab le. To optimize trans­mit and receive signal quality, pins RTX and RTX2EQ
should be connected to external resistors 560 ohm (±1%)
and 1.4K ohm (±1%) and then to g round respectively.

3.9 Remote-Power -On and ACPI application

3.5 SERIAL EEPROM

The MX98715AEC-E provides pins EECS,BPA0 (EECK),
BPA1 (EEDI) and BPD0 (EEDO) for directly accessing
the serial EEPROM. BPA0-1 and BPD0 serve as SK
(EECK), DI (EEDI) and DO (EEDO) respectively. The
contents of the EEPROM includes the ID information of
the MX98715AEC-E (V endorID , DeviceID , Sub-vendorID ,
Sub-deviceID and MAC ID), and the configuration pa­rameters for software driver. The EEPROM contents
should be programmed according to MXIC's definition
as mentioned in Appendix A. Detailed software program­ming example is described in section 4.5.

3.6 PROGRAMMABLE LED SUPPORT

The MX98715AEC-E provides two pins LED0 and LED1
to control display LEDs. Displayed messages are pro­grammable through setting CSR9 bit-28 & bit-29 to serve
as Activity /Linkspeed and Goodlink/Linkactivity LED
respectively . The maximum sinking current of these out­put pins is 16mA. Current limiting resistor (560 ohm)
should be added to ensure proper operation. The f ollow-

MX98715AEC-E fully supports Remote-Power-ON and
ACPI spec that meet PC98 requirement for power­sensitive applications. It accepts the following wake-up
events in the power-down mode.

* Reception of a Magic Pack et.
* Reception of a Network wake-up frame.
* Detection of change in the network link state.

To put MX98715A into the sleep mode and enable the
wake-up events detection are done as following:

1. Write 1 to PPMCSR [8] to enable power management
feature.

2. Write the value to PPMCSR [1:0] to determine which
power state to enter .

If D1, D2 or D3

state is set, the PC is still turned on

hot

and is commonly called entering the Remote W ak e-up
mode. Otherwise if the main power on a PC is totally

shut off, we call that it is in the D3

state or Remote

cold

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Po wer-On mode. T o sustain the oper ation of the Lancard,
a 5V standby power is required. Once the PC is turned
on, MX98715AEC-E loads the magic ID from EEPROM
and set it up automatically. No register is needed to be

programmed. After then, simply turn of PC to enter D3

cold

state. In either Remote W ake-up mode or Remote P ower­On mode. The transceiver and the RX b lock are still alive
to monitor the network activity . If one of the three wak e­up events occured, the following status is changed:

1. PPMCSR [15] (PME status) is set to 1.

2. CRS5 [28] (WKUPI) is set to 1.

3. PCI interrupt pin INTA# is asserted low.

4. LANWAKE pin is asserted high.

4. DRIVER PROGRAMMING GUIDE

This chapter will provide you the necessary information
for programming driver for the MX98715AEC-E based
node. Initialization module is introduced first that de­scribes how MX98715AEC-E is initialized before any
other operations can commence, then followed by ac­tual implementation examples for both transmit and re­ceive operations.

MX98715AEC-E

for (i=0; i<NumTXBuffers; i++) {
/* initialize the own bit to host tdes0 */
tx_resource[i]->ownership=0x00;
tx_resource[i]->tstatus=0x0000;
tx_resource[i]->tdes0_unused=0x00;

/* fill buffer_1_address tdes2 */
get_ea((void far *)(tx_resource[i]->tx_buffer_data),
&physicaladdress);
tx_resource[i]->buff_1_addr=physicaladdress;

/* fill buffer_2_address tdes3 */
if (i==NumTXBuffers-1) j=0;
else j=i+1;
get_ea((void far *)(tx_resource[j], &physicaladdress);
tx_resource[i]->buff_2_addr=physicaladdress;
}
}

initializeTheReceiveRing()
{
unsigned int i,j;
unsigned long physicaladdress;
for (i=0; i<NumRXBuffers; i++) {
/* memory allocation for rx descriptor_buffer (allign 4) */
rx_resource[i]=
(struct RX_RESOURCE *)((((unsigned int)rx_temp[i])+4)&
0xfffc);
}

for (i=0; i<NumRXBuffers; i++) {
/* set the own bit to chip rdes0 */
rx_resource[i]->frame_length=RDES0_OWN_BIT;
rx_resource[i]->rstatus=0x0000;

4.1 INITIALIZA TION

initializeTheTransmitRing()
{
unsigned int i,j;
unsigned long physicaladdress;
for (i=0; i<NumTXBuffers; i++) {
/* memory allocation for tx descriptor_buffer (allign 4) */
tx_resource[i]=
(struct TX_RESOURCE *)((((unsigned int)tx_temp[i])+4)&
0xfffc);
}

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/* fill rdes1 */
rx_resource[i]->command=RDES1_BUFF­RX_BUFFER_SIZE+rxpkt_size[i];

/* fill buffer_1_address rdes2 */
get_ea((void far *)(rx_resource[i]->rx_buffer_data),
&physicaladdress);
rx_resource[i]->buff_1_addr=physicaladdress;
/* fill buffer_2_address rdes3 */
if (i==NumRXBuffers-1) j=0;
else j=i+1;

3

MX98715AEC-E

get_ea((void far *)(rx_resource[j], &physicaladdress);
rx_resource[i]->buff_2_addr=physicaladdress;
}
}

initialize()
{
unsigned long physicaladdress;

NIC_read_reg(&csr6);
NIC_write_reg(&csr6,csr6.value&(~(CSR6_SR|CSR6_ST)));
delay(10);
InitializeTheTransmitRing (6);
InitializeTheReceiveRing (6);
NIC_write_reg(&csr0,CSR0_L_SWR);
delay(50);

NIC_write_reg(&csr0,csr0shadow);
get_ea((void far *)rx_resource[0],&physicaladdress);
NIC_write_reg(&csr3,physicaladdress);
get_ea((void far *)tx_resource[0],&physicaladdress);
NIC_write_reg(&csr4,physicaladdress);
NIC_read_reg(&csr16);
NIC_write_reg(&csr7,csr7shadow);
NIC_write_reg(&csr16,csr16shadow);
//Clear status register
NIC_write_reg(&csr5,(unsigned long)0xffffffff);
NIC_write_reg(&csr6,csr6shadow);
NIC_read_reg(&csr6);
setup_frame(TDES1_SETUP_LAST,perfect);
}

4.2 TRANSMISSION MODULE

bmtx()
{
unsigned char editmode, j;
struct TX_RESOURCE *tx_pointer;

initialize();
fill_pattern(6); //fill pattern
NIC_write_reg(&csr6,csr6.value&(~CSR6_ST)); //stop
NIC_read_reg(&csr6);
NIC_write_reg(&csr6,csr6.value|CSR6_SF); //store and
forward
NIC_read_reg(&csr0)
NIC_write_reg(&csr0,csr0.value|0x020000); //TAP=01
tx_pointer=tx_resource[0];
j=0;

editmode=1;

while (editmode) {
if ((tx_pointer->ownership & 0x80)==0) {
j++;
j%=tx_pkt_num;
if (tx_pointer->command & TDES1_LS_BIT)
tx_error_detect(tx_pointer->tstatus);
tx_pointer->ownership |= 0x80;
tx_pointer=tx_resource[j];
}
if (kbhit()) {
keycode_get();
if (M_code!=0) {
switch (M_code) {
case 0x1b: // ESC: quit
editmode=0;
break;
case 0x20:
NIC_read_reg(&csr6);
NIC_write_reg(&csr6,csr6.value^CSR6_ST);
break
default: break;
}
}
}
}
}

4.3 RECEPTION MODULE

bmrx()
{
unsigned char editmode,i,j;
unsigned long physicaladdress;
struct RX_RESOURCE *rcv_pointer;

initialize();
rcv_pointer=rx_resource[0];
j=0;
editmode=1;

while (editmode) {
// if data received
if ((rcv_pointer->frame_length & 0x8000)==0) {
j++;
j%=6;
if (rcv_pointer->rstatus & RDES0_LS)
rx_error_detect(rcv_pointer->rstatus);
rcv_pointer->frame_length |= 0x8000;

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rcv_pointer=rx_resource[j];
}
if (kbhit()) {
keycode_get();
if (M_code!=0) {
switch (M_code) {
case 0x1b: // ESC: quit
editmode=0;
break;
default: break;
}
}
}
}
}

MX98715AEC-E

CSR20.22 default value = 1 for IC revision H, for all
older IC revision, the default value =0.

CSR20.16 should be set to the same value as CSR20.22.
For PC99 certification, Rev.H IC is requred, therefore

both CSR20.22 and CSR20.16 should be set to 1 by
drivers.

4.5 EEPROM ACCESSING

The following is a reference code for accessing the con­tents of EEPROM that stores ID information and node
configuration for the MX98715AEC-E.

4.4 SPECIAL CODING of MX98715AEC-E

4.4.1 SPEED SELECTION

Speed selection for MX98715AEC-E is controlled by in­ternal Nway registers.

The Internal NWay registers are remov ed and protocol
selection is controlled by Operation Mode Register
(CSR6) and 10Base-T Control Register (CSR14)

NWay Active 100F 100H 10F 10 H
CSR6_PS 0 1 1 0 0
CSR6_PCS X 1 1 X X
CSR6_FD 1 1 0 1 0
CSR14_ANE 1 0 0 0 0

4.4.2 REGISTERS SETTING FOR DEVELOPING
Y OUR OWN DRIVER

The contents of CSR16 for MXIC 10/100Base NIC con­trollers should be set differently as follow:

MX98715AEC-E = 0x0b3cXXXX

Meanwhile, you could directly access the Nway auto­negotiation status from CSR20. Detailed format infor­mation please refer to MX98715AEC-E data sheet.

/*************************************
* Read all content from EEPROM
**************************************/
eeprom_read()
{
unsigned int i, address, eeval;
char bit;
for (address=0; address<64; address++{
NIC_write_reg(&csr9,(unsigned long)0x04800);
eeprom_serial_in(0);
eeprom_serial_in(1); //command
eeprom_serial_in(1);
eeprom_serial_in(0);
for(i=0; i<6; i++){ //address serial in
bit = ((address>>(5-i)) & 0x01) ? 1:0;
eeprom_serial_in(bit);
}
eeval=0;
for(i=0; i<16; i++){ //dat serial out
NIC_write_reg(&csr9,(unsigned long)0x04803);
NIC_read_reg(&csr9);
eeval += (((unsigned long)0x008 & csr9.value)>>3)<<(15­i);
NIC_write_reg(&csr9,(unsigned long)0x04801);
}
NIC_write_reg(&csr9,(unsigned long)0x04800);
c46[address*2] = eeval & 0x0ff;
c46[address*2+1] = (eeval >>8) & 0x0ff;
}
}

If EEPROM offset 77h bit5=1 (autocomp), then
CSR20.14=CSR20.9=1. To enable long cable compen­sation circuit to improve quality & yield when long cable
is used.

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MX98715AEC-E

/*************************************
* Write a word to EEPROM
**************************************/
eeprom_write(unsigned int address, unsigned int data)
{
unsigned int i;
char bit;
eeprom_wen();
NIC_write_reg(&csr9,(unsigned long)0x04800);
eeprom_serial_in(0);
eeprom_serial_in(1); //command
eeprom_serial_in(0);
eeprom_serial_in(1);

for(i=0; i<6; i++){ //address serial in
bit = ((address>>(5-i)) & 0x01) ? 1:0;
eeprom_serial_in(bit);
}
for(i=0; i<16; i++){ //data serial in
bit = ((data>>(15-i)) & 0x01) ? 1:0;
eeprom_serial_in(bit);
}
NIC_write_reg(&csr9,(unsigned long)0x04800);
NIC_write_reg(&csr9,(unsigned long)0x04801);
i=0;
do{
i++;
NIC_read_reg(&csr9);
} while ((!(csr9.value & 0x08)) && (i<10000));
NIC_write_reg(&csr9,(unsigned long)0x04800);
if (i==10000) prstring (“Writing EEPROM error !!”);
eeprom_wds();
}

eeprom_wds()
{
NIC_write_reg(&csr9,(unsigned long)0x04800);
eeprom_serial_in(0);
eeprom_serial_in(1);
eeprom_serial_in(0);
eeprom_serial_in(0);
eeprom_serial_in(0);
eeprom_serial_in(0);
eeprom_serial_in(0);
eeprom_serial_in(0);
eeprom_serial_in(0);
eeprom_serial_in(0);
NIC_write_reg(&csr9,(unsigned long)0x04800);
}

/*************************************
* Serial inject a bit to EEPROM
**************************************/
eeprom_serial_in(unsigned int bit2)
{
NIC_write_reg(&csr9,(unsigned long)0x04800+4*bit2);
NIC_write_reg(&csr9,(unsigned long)0x04803+4*bit2);
NIC_write_reg(&csr9,(unsigned long)0x04801+4*bit2);
}

4.6 AUTO-COMPENSATION ON TRANSCEIVER

The driver must set bits CSR20<9> and CSR20<14> high to enable
auto-compensation function. Be careful not to clear these two bits
while accessing CRS20 at any time.

eeprom_wen()
{
NIC_write_reg(&csr9,(unsigned long)0x04800);
eeprom_serial_in(0);
eeprom_serial_in(1);
eeprom_serial_in(0);
eeprom_serial_in(0);
eeprom_serial_in(1);
eeprom_serial_in(1);
eeprom_serial_in(0);
eeprom_serial_in(0);
eeprom_serial_in(0);
eeprom_serial_in(0);
NIC_write_reg(&csr9,(unsigned long)0x04800);
}

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MX98715AEC-E

5. PCB layout recommendation

Introduction:
Due to the high frequency and the increasing degree of integration, system board designs are becoming complex. The
purpose of this section is to give system designer more information. Such as pow er stability , placement, signal trace
routing and de-coupling capacitor.

5.1 Power / Gr ound consideration

It is recommended to separate power plane into 3 domains (Power for digital , analog and receive section). Seg­mented power supplies reduces noise from one section to another .
It is also recommended to separate ground plane into 3 domains ( Digital Ground, Analog Ground and Receive
Ground). The reason f or separating is to prev ent digital noise from coupling onto the analog or receive ground.
All power/ground lines should be as wide as possible to allow noise de-coupling and efficient low resistive paths for
supply current.

3.3V

bead

V digital

V analog

GND GNDR

40mil

Bridge

V receive

GND GNDA

Depending upon the environment, any or all of these filters may be simplified.o

GNDR

(Receive ground)

GNDS

CardBus

GNDA

(Chassis

Interface

(Analog ground)

ground)

GND
(digital ground)

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MX98715AEC-E

Oscillat

5.2 Board Layout / Trace Routing

¨ 90 degree corners should be avoided, smooth cornering is preferred.

¨ Keep the lengths of clock lines short and minimize the numbers of VIAs.

¨ All pair lines ( i.e. TX+/- , RX+/-) are of the equal length and run in parallel

then possible noise is common and can be ignored on different inputs.

Magnetic

Tx+
Tx-

Tx+
Tx-

¨ A good practice is that never run transmit and receive pair too close.

Crosstalk may become a problem.

Tx+
Tx-

Rx+
Rx-

Magnetic

Tx+
Tx-

Rx+
Rx-

¨ The ground shield of clock line may reduce extra noise.

Magnetic

Magnetic

Tx+
Tx-

Rx+
Rx-

Ground Shield

or

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MX98715AEC-E

¨

All differential pair ( Tx +/ - , Rx +/-) to the magnetic should have matched
impedance. See schematics for details.

V

50

Tx+
Tx-

V

Rx+
Rx-

100 Ohm

¨

A chassis ground is used to isolate the cable side and ground.

Magnetic

50

Magnetic

Chassis

System Ground

5.3 Component placement

General:

External components are placed as close as possible

Magnetic

Osc/Crystal

IC

Ground

RJ-45

BootRom

Eeprom

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MX98715AEC-E

¨

De-coupling capacitor
De-coupling cap should be placed close to power pin. It stabilize current to

the device and de-coupling noise from the power plane to ground.

PIN

0.1 U

¨

Analog Region Receive Region Digital Region

81. VDD 90. VDD Others

82. GND 89. GND

84. VDD 93. V DD

88. VDD 94. GND

87. GND 95. GND

86.GND

96. VDD

99. GND

103. VDD

104. GND

105. GND

106. VDD

107. GND

108. VDD

109. GND

IC

Transformer

RX­RX+

TX­TX+

Receive Region

Bead

Bead

109
110

95

96

88

89

Analog Region

OSC or crystal

25MHz

81 80

Digital Region

MX98715AEC-E

128

1

Fig. 2

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MX98715AEC-E

APPENDIX A: EEPROM FORMAT

BYTE OFFSET (HEX) DESCRIPTIONS
00-13 Reserved
1 4 MAC ID Byte0 ( is automatically loaded into IC )
1 5 MAC ID Byte1 ( is automatically loaded into IC )
1 6 MAC ID byte2 ( is automatically loaded into IC )
1 7 MAC ID byte3 ( is automatically loaded into IC )
1 8 MAC ID byte4 ( is automatically loaded into IC )
1 9 MAC ID byte5 ( is automatically loaded into IC )
1 a Magic Pac k et ID Byte0 ( is automatically loaded into IC )
1 b Magic Pac k et ID Byte1 ( is automatically loaded into IC )
1c Magic Packet ID Byte2 ( is automatically loaded into IC )
1 d Magic Pac k et ID Byte3 ( is automatically loaded into IC )
1e-39 Reserved
3 a Magic Pac k et ID Byte4 ( is automatically loaded into IC )
3 b Magic Pac k et ID Byte5 ( is automatically loaded into IC )
3c-59 Reserved
5 a LSB of Sub-Device ID ( is automatically loaded into IC )
5 b MSB of Sub-Device ID ( is automatically loaded into IC )
5c LSB of Sub-Vendor ID ( is automatically loaded into IC )
5 d MSB of Sub-Vendor ID ( is automatically loaded into IC )
5e-6f Reserved
7 0 Network ID index: to indicates the starting address of Network ID in length of continu-

ous 6 bytes. The content of this field could be in the range of 00-04h, or 10-14h, or

21-24h, or 31-34h. IC always automatically load ID from 14h after reset or power up.
71-75 Reserved, and should be set to 0
76 LED option: The conent of this field is automatically loaded into CSR9 register for LED option.

Bit0:CSR9<28>=LED0SEL

Bit1:CSR9<29>=LED1SEL

Bit2:CSR9<30>=LEDSEL2

Bit3:CSR9<31>=LEDSEL3

Bit4:CSR9<24>=LEDSEL4

Bit5:CSR9<25>:WKFCAT0

Bit6:CSR9<26>:WKFCAT1

Bit7:Must be zero

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MX98715AEC-E

LED programing option table

01
LED0SEL ACT SPEED
LED1SEL LINK LINK/ACT
LED2SEL SPEED COL (NO T USED)
LED3SEL R X FULL/HALF (NOT USED)
LED4SEL* CO L PMEB (NOT USED)

7 7 Miscellaneous options is automatically loaded into CSR21 register & IC. :

Bit0:CSR21<2>MPHITDIS=Set to disable magic packet detection,
Bit1:CSR21<3>LNKCHGDIS=Set to disable link change detection.
Bit2:LW AKEPOR (NOT USED), DON'T CARE.
Bit3:CSR21<4> WKFCATEN, wake up frame concatenation option enable .
Bit4:PCI PM1.1=Default 0 for PM1.0 support, Set for pm1.1 support, PCI configuration
Register PPMC bit 18-16 will be affected.
Bit5:AUT OCOMP: Default is 1,set to enable transceiv er auto-compensation function.
It overrides bits CSR20<9> and CSR20<14>.
Bit<7:6>:Must be zero.

78-79 Reserved, and should be set to 0
7 a LSB of Device ID
7 b MSB of Device ID
7c LSB of V endor ID
7 d MSB of Vendor ID
7e-7f Reserved, and should be set to 0

* Note :Byte 77 Bit 5 (Autocomp) must always set to 1.

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MX98715AEC-E

APPENDIX B: SPECIAL COMPONENTS

1.MAGNETIC

A.BASIC ELECTRICAL SPECIFICA TION

T urn Ratio T ransmit 1:1

Receive 1:1

OC L 350uH min measured between 0 and 70°C with a 0.1V rms, 100KHz

signal at a DC. bias between 0 and 8mA.
L L 0.4uH Max at >1MHz
Cw w 18pF Max
DC R 0.9W Max per winding
Isolation Resistance not less than 1GW @ 2000V rms
Isolation Voltage 2000V rms Min @ 60Hz for 1 min
Rise/Fall Time 3ns Min 4ns Max
Insertion Loss (100 KHz to 100 MHz) -1.1 dB Max
CMDR & DCMR (100 KHz to 80 MHz) 38 dB Min
Cross Talk (100KHz to 80 MHz) -38 dB Max

B. T ransformer REFERENCE VENDORS

V endor Part No
V alor ST6118 (PT4171S)
PE PE68515
BelFuse S558-5999-15
Delta LF8200
T aimic HSIP-002

2.CRYSTAL

BASIC ELECTRICAL SPECIFICA TION

A.

CL=((C1*C2)/(C1+C2))+CIC+ C, Rd 100 ohm,R 1M ohm
CL=Crystal's external load capacitor

Specified by crystal's specification
CIC=MX98715AEC-E internal capacitor, 7pF
C=PCB's stray capacitance
Assume C1=C2=C
CL=1/2C

+ 7pf + 3pf

Ext

if CL=20pf, than C

P/N:PM0678 REV. 0.4, JUN. 21, 2000

, C=3pf,

Ext

Ext=C1=C2

C1

=20pf.

13

IC

R

Rd

C2

MX98715AEC-E

B. CR YST AL REFERENCE VEDORS

SPK 25MHz±50PPM
NDK
JEN JAAN ENTERPRISE

3. SPECIAL REQUIREMENT ON RESIST ORS & BEAD

Resistors for RTX=560 ohm ± 1%
Resistor for RTX2EQ=1.4K ± 1%
Resistor for RD A=10K ± 5%(F or 10 Base-T Vpp swing)
Ferrite Bead maximum current capacity for analog Vdd > 300mA
Ferrite Bead maximum current capacity for Receiv e Region Vdd > 100mA

P/N:PM0678 REV. 0.4, JUN. 21, 2000

14

MX98715AEC-E

Bill Of Materials ( Refer to schematic dated Nov 6, 1999)

Item Quantity Reference Part
1 20 C1,C4,C7,C8,C9,C10,C11, 0.1u

C12,C14,C15,C16,C17,C18,

C22,C23,C28,C30,C33,C35,

C37
2 3 C2,C24,C27 22u
3 1 C3 470p
4 1 C5 47p
5 1 C13 2.2u
6 2 C20,C19 30p
7 1 C 29 0.01u/1KV
8 1 C31 82p
9 1 C38 47u
10 2 D1,D2 LED
11 1 D3 1N5817
12 1 J1 CON3
13 3 L1,L3,L4 F.B. ( L1 must sustain maximum current up to 200mA )
1 4 1 L6 25uH (L4 must sustain maximum current up to 300mA)
15 1 OSC1 25MHz
16 1 P1 PCI5V_A
17 1 Q2 PNP
18 1 RJ1 RJ-45
19 3 R1,R2,R9 560
20 2 R3,R26 100
21 1 R4 10K
22 3 R6,R10,R11 49.9 ( R10,R11 must sustain up to 0.25W )
23 4 R7,R13,R14,R15 75
24 1 R 8 1.4K
25 2 R17,R28 51K
26 1 R 1 8 0 ohm
27 1 R18 22
28 1 R19 27K
29 1 R21 68K
30 1 R27 0
31 1 U2 27512
32 1 U3 93C46
33 1 U4 ST6118
34 1 U5 AIC1631-5
35 1 U6 FDC6324L
36 1 U7 NDC631N
37 1 U8 MX98715AC

P/N:PM0678 REV. 0.4, JUN. 21, 2000

15

MX98715AEC-E

Appendix C: IEEE802.3 CONFORMANCE TEST

1. Testing Conditions
(1) DUT diagram (using MX98715AEC-E standard 2-layer PCB demo board)

5V

TXOP

MX98715AEC-E

TXON

50

5V

50

33pF

Tran sforme r

1:1

33pF

(2) Testing equipment and setting

T ektronix TDS744A Digitizing Oscilloscope
trigger Slope +
rise time: 10% ~ 90%
fall time: 90% ~ 10%
probe input capacitance: 1pF
probe input impedance: 200K ohm

2. UTP Differential Output Test (950mV V out 1050mV)

(1) Vout (+) = 500.0mV
(2) Vout (-) = -500.0mV
(3) Result: Pass

3. UTP Active Output Interface T emplate T est

(1) UTP active output interface template
(see below scanned figure)

100

+

V

out

_

P/N:PM0678 REV. 0.4, JUN. 21, 2000

16

3 UTP Active Output Interface Templace Test

(1) 10 BT Transmit tenplate checker

TXOP

+

_

TXON

TP -

Model

MX98715AEC-E

100

+

V0

_

(2) UTP active output interface template

10 BT Transmit Templatc

P/N:PM0678 REV. 0.4, JUN. 21, 2000

17

(3) 10BT Transmit waveform

MX98715AEC-E

Result: Pass

P/N:PM0678 REV. 0.4, JUN. 21, 2000

18

4. Vout T ransmit Wa veform Overshoot (shall not exceed 5%)

(1) V out (+) pattern
(see below scanned figure)

MX98715AEC-E

100BT Transmit overshoot non-scramble pattern=000000000000001- - - - -

P/N:PM0678 REV. 0.4, JUN. 21, 2000

19

(2) V out (-) pattern
(see below scanned figure)

MX98715AEC-E

100BT Transmit overshoot non-scramble pattern=000000000000001- - - - -

(3) Result: Pass

P/N:PM0678 REV. 0.4, JUN. 21, 2000

20

MX98715AEC-E

5. Transmit Signal Amplitude Symmetry (0.98 +Vout(+) / -Vout(-) 1.02)

(1) Vout(+) = 500mV
(2) V out(-) = -500mV

(3) Results: P ass

6. Vout T ransmit Rise/Fall Times (3.0nsec < T rise/fall < 5.0nsec)

100BT Transmit rise/fall time. non-scramb le pattern=000000000000001 - - - - -

(3) Results: Pass

7. Vout T ransmit Duty Cycle Distortion (The deviation of the 50% crossing times fr om a best fit to a time grid
of 16ns shall not exceed .25ns) (DSO: Lecro y9384, Vcc: 5.0V olts)

(1) Amplitude Results
(see below scanned figure)

P/N:PM0678 REV. 0.4, JUN. 21, 2000

21

(2) First half cycle
(see below scanned figure)

MX98715AEC-E

100BT Transmit Duty Cycle Distortion. non-scramble pattern=010101 - - - - -

(3) Second half cycle
(see below scanned figure)

100BT Transmit Duty Cycle Distortion. non-scramble pattern=010101 - - - - -

P/N:PM0678 REV. 0.4, JUN. 21, 2000

22

(4) Third half cycle
(see below scanned figure)

MX98715AEC-E

100BT Transmit Duty Cycle Distortion. non-scramble pattern=010101 - - - - -

(5) Fourth half cycle
(see below scanned figure)

100BT Transmit Duty Cycle Distortion. non-scramble pattern=010101 - - - - -

(6) Test Result : Pass

P/N:PM0678 REV. 0.4, JUN. 21, 2000

23

8. Transmit peak to peak votlage (1.9V Vpp 2.1V)

MX98715AEC-E

100BT Transmit Vpp non-scramble pattern=000000000000001 - - - - -

9. Transmit jitter ( jitter 1.4ns)

100BT Transmit jitter random pattern

P/N:PM0678 REV. 0.4, JUN. 21, 2000

24

MX98715AEC-E

P/N:PM0678 REV. 0.4, JUN. 21, 2000

25

MX98715AEC-E

P/N:PM0678 REV. 0.4, JUN. 21, 2000

26

MX98715AEC-E

REVISION HISTORY

REVISION DESCRIPTION PAGE DATE

0.1 Modify the power switch application circuits (option 1&2) P12,13,14 NOV/09/1999

0.2 Modify Appendix A and add 14~19 byte offset(HEX) P9, 10 DEC/13/1999

0.3 Modify contents: Registers setting for developing your own driver P5 MA Y/04/2000

0.4 Add appendix C P14~22 JUN/15/2000

Modify 5. PCB Layout Recommendations P7~10 JUN/21/2000

P/N:PM0678 REV. 0.4, JUN. 21, 2000

27

TOP SIDE MARKING

MX98715AEC-E

MX98715AEC-E

C9930
TA777001
37DEX

TAIWAN

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:[phone]
FAX:[phone]

line 1 : MX98715A is MXIC parts No.

"E" : PQFP
"C" : commercial grade

"-E" : bonding option
line 2 : Assembly Date Code.
line 3 : Wafer Lot No.
line 4 : "37D" : revision code,

"E" : bonding option

"X" : no used
line 5 : State

EUROPE OFFICE:

TEL:[phone]
FAX:[phone]

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CHICAGO OFFICE:

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http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

28