Datasheet MX97103FC Datasheet (MXIC)

FEATURE

PRELIMINARY

MX97103

ISDN S/T-PCI TRANSCEIVER

• Single chip solution for ISDN PC card with PCI inter­face

• Supports full duplex 2B+D ISDN S/T transceiver ac­cording to ITU I.430

• Integrate S-interface, D & B channel protocol control­lers, and PCI controller

• 32-bit PCI bus interface

GENERAL DESCRIPTION

MX97103 is a single chip solution for ISDN-S connec­tion on PCI bus. It integrates S-transceiver, D and B
channel protocol controllers, and PCI interface.

It can be divided into the following major functional bloc ks
: analog front end, la yer 1 function, GCI interface . LAPD
controller, B channel HDLC controllers, EEPR OM inter­face and PCI interface. The important function of each
major block will be described below.

According to ITU 1.430 spec. the S/T interface is a 4­wire interface. Among them, 2 wires are used f or trans­mitting, and the other two are for receiving. The wiring
configurations include short passive bus, e xtended pas­sive bus and point-to-point connection. For short pas­sive bus , the operation distance is from 100m to 200m,
and the TEs(max 8)can be connected at random points
along the full length of the cable. F or e xtended passive
bus, TEs connect to the cable at the far end from the NT.
The total length would be at least 500m and a differen­tial distance between TE connection points is of 25 to
50m. For point-to-point connection, the cable length can
be 1km.

• Each B channel has 2x64 byte FIFO for each direction

• D channel has 2x32 byte FIFO for each direction

• EEPROM interface for loading vendor-specific data

• One programmable LED

• Comply to ACPI Rev 1.0

• 0.5u CMOS

• 100-pin PQFP package

The layer 1 b lock comprises of PDLL, DA C, RT and MFC
functions. DPLL's function is to establish S/T frame syn­chronization. DAC resolves the contention issue for
differnet TE accessing D channel at the same time . R T
deals with the receiving S/T data extraction and put out
the transmitted data at the corrent time slot. MFC is the
multiframing S and Q channel control block.

GCI is the digital bus for the IC. It can accomodate 8
GCI-compatible devices . This bloc k conv erts the frame
between GCI and S/T interface.

LAPD block relieves the microprocessor of the duty to
generate HDLC frame on the D channel. It can gener­ate flag, CRC, address and control field automatically.
And it can generate S-frame for HDLC protocol. It con­tains 2 FIFO of 2x32 byte each to facilitate the D pac ket
transmission and reception.

Two B channel HDLC controllers can handle tasks like
flag and CRC generation, zero insertion and deletion.
For each direction a 2x64 byte FIFO is pro vided to buffer
the data.

The analog front end deals with the signals transmitted
to and received from the wiring cable. It accepts the
digital data from layer 1 block and converts them into
appropriate signals to be sent out to the wire, and it also
receive the attenuated and distorted signal from the wire
and recover them to be processed b y la yer 1 block.

P/N:PM0564 REV. 1.0, FEB. 23, 1999

The EEPROM interface is used to load specific v endor
information after system hardware reset. V endor ID and
device ID can be load to distinguish different products.
If EEPROM is not used, default v alues will be set.

The PCI interface enables the chip attached to PCI bus
directly without any glue logic. The bus speed can be
from 25MHz to 33MHz.

1

PIN CONFIGURATION

AD15

VSS

CBE1#

PAR

VDD

PERR#

STOP#

VSS

DEVSEL#

TRDY#

IRDY#

FRAME#

CBE2#

VSS

AD16

AD17

VSS

AD18

AD19

VDD

AD20

AD21

VSS

AD22

AD23

VSS

IDSEL

CBE3#

AD24

AD25

MX97103

AD14

VSS
AD13
AD12

VDD
AD11
AD10

VSS

AD9

AD8

VSS

CBE0#

AD7

AD6

VSS

AD5

AD4

VDD

AD3

AD2

BLOCK DIAGRAM

8079787776757473727170696867666564636261605958575655545352

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

1234567891011121314151617181920212223242526272829

AD1

AD0

VSS

VDD

EEDI

EEDO

EECK

EECS

PME

MX97103

VSS

TEST3

TEST2

LED1

TEST1

TEST4

VDD

DD

DU

FSC

DCL

VSS

SDS1

BCL

VSS

SDS2

XTAL2

XTAL1

SR2

AVSS(C)

51

30

SR1

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

VDD
AD26
AD17
VSS
AD28
AD29
VSS
AD30
AD31
VDD
CLK
VSS
RST#
INTA#
AVDD(C)
SX2
SX1
AVDDX
AVDD(P)
AVSS(P+X)

P/N:PM0564

S/T Interface

7.68MHZ

Transmitter

Multiframe

control

Receiver

OSC

Activation/

Deactivation

DPLL

GCI interface

DU DD

GCI

DCL FSC1

2

LAP-D&B-HDLC

B-channel

Switching FIFOS

PCI

Interface

PCI bus

EEPROM

Interface

REV. 1.0, FEB. 23, 1999

MX97103

PIN DESCRIPTION

PAD# PIN NAME TYPE DESCRIPTION
42, 43, 45, 46, 48, 49, AD[31:0] I/O PCI address/data bus.
51, 52, 56, 57, 59, 60,
62, 63, 65, 66, 80, 81,
83, 84, 86, 87, 89, 90,
93, 94, 96, 97, 99, 100,
2, 3
53, 68, 78, 92 CBE[3:0]# I PCI command/byte enable, command during address

phase, byte enable during data phase.

69 FRAME# I PCI FRAME# signal, asserted to indicate the start of a bus

transaction.
71 TRDY# O PCI Target ready, asserted by target agent.
70 IRDY# I PCI master ready, data transferred on the rising edge of

CLK when IRDY# and TRDY# both asserted.
72 DEVSEL# O PCI slave device select, specific for configuration cycle.
54 IDSEL I PCI Initialization device select, specific for configuration

cycle.
40 CLK I PCI clock, 33MHz
38 RST# I PCI bus reset
37 INTA# O/D PCI bus interrupt request
75 PERR# I/O PCI bus data error
77 PAR I/O PCI bus parity bit, even parity for AD and CBE
74 STOP# O PCI stop signal
23 BCL O GCI bit clock, 768KHz
22 SDS1 O GCI serial data strobe 1, programmable strobe signal
24 SDS2 O GCI serial data strobe 2, programmable strobe signal
19 FSC O(I) GCI frame sync
20 DCL O(I) GCI data clock, 1.536MHz
18 DU I/O GCI data upward to ST interface
17 DD I/O GCI data downward from ST interface
34 SX1 O S-bus transmitter output(positive)
35 SX2 O S-bus transmitter output(negative)
29 SR2 I S-bus receiver input
30 SR1 I S-bus receiver ref erence
27 XTAL1 I Connection f or 7.68MHz crystal/oscillator input
26 XTAL2 O Crystal output
9 LED2 O Auxillisry LED output 0
15 LED1 O Auxilliary LED output 1

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REV. 1.0, FEB. 23, 1999

3

PAD# PIN NAME TYPE DESCRIPTION
8 EECS O EEPROM chip select
7 EECK O EEPROM interf ace cloc k
6 EEDI O Output data to EEPROM
5 EEDO I Input data from EEPROM
10, 12, 13, 14 TEST[4:1] test pins
36, 33, 32 A VDD Analog po wer
31, 28 A VSS Analog ground
4, 16, 41, 50, 61, VDD Digital power
76, 85, 98
1, 11, 21, 25, 39, VSS Digital ground
44, 47, 55, 58, 64,
67, 73, 79, 82, 88,
91, 95

ABSOLUTE MAXIMUM RATINGS

MX97103

Supply Voltage(VDD) 4.75V to 5.25V
DC Input Voltage(Vin) -0.5V to VDD+0.5V
DC Output Voltage(Vout) -0.5V to VDD+0.5V
Storage T emperature Range(Tstg) -55°C to 150°C
Pow er Dissipation(PD) 500mW
Lead T emp.(TL)(Soldering, 10sec) 260°C
ESD Rating(Rzap=1.5k, Czap=100pf) 2000V
Clamp Diode Current ±20mA

P/N:PM0564

REV. 1.0, FEB. 23, 1999

4

MX97103

DC CHARACTERISTICS

PCI BUS D.C SPECS

PCI System signals
CLK, RST#
PCI Shared signals
AD[31:0](t/s), CBE[3:0]#(t/s), FRAME#(s/t/s), TRDY#(s/t/s), IDSEL(in), IRDY#(s/t/s), ST OP#(s/t/s),
DEVSEL#(s/t/s), PAR(t/s), PERR#(s/t/s), INT A#(o/d), SERR#(s/t/s)

Temperature from 0 to 70°C; VDD=5V±5%, VSS=0V, AVSS=0V

SYMBOL P ARAMETER CONDITIONS MIN. V ALUE MAX. VALUE NOTES
VIL L-input v oltage 0.8V
VIH H-input voltage 2.0V 5.4V
VOL L-output voltage IOL1=3mA 0.45V 1

IOL2=6mA
VOH H-output voltage IOH=-2mA 2.4V
IIL L-input current VIN=0.5V -70uA
IIH H-input current VIN=2.7V 70uA
CI/O Input/output capacitance at 1MHz 10pF
CCLK CLK input capacitance at 1MHz 17pF
CL Load capacitance 50pF

NOTE:

1. IOL2 applies to signals with external pull-ups: FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#

GCI BUS & EEPROM INTERFACE D.C. SPECS

GCI signals:
BCL, DCL, DD , DU, FSC.SDS1, SDS2
EEPROM signals:
EECS, EECK, EEDI, EEDO

SYMBOL P ARAMETER CONDITIONS MIN. V ALUE MAX. VALUE NOTES
VIL L-input v oltage 0.8V
VIH H-input voltage 2.0V 5.4V
VOL L-output voltage IOL1=2mA 0.45V 1

IOL2=7mA
VOH H-output voltage IOH=-400uA 2.4V

NOTE:

1. IOL2 is for DD only.

P/N:PM0564

REV. 1.0, FEB. 23, 1999

5

MX97103

S-BUS D.C. SPECS

SX1, SX2, SR1, SR2

SYMBOL P ARAMETER CONDITIONS MIN. V ALUE MAX. V ALUE NOTES
VX Absolute value of output RL=50 ohm 2.03V 2.31V SX1, SX2

pulse amplitude RL=400 ohm 2.10V 2.39V
(VSX2-VSX1)

IX Transmitter output RL=5.6 ohm 7.5mA 13.4mA

current

RX T r ansmitter output (1) Inactive or during (1)10K ohm

impedance binary 1, (2) during (2) 0 ohm

binary 0 RL=50 ohm
VSR1 Receive output voltage IO<5uA 2.35V 2.6V SR1, SR2
VTR Receiver threshold Dependent on peak 225mV 375mV SR1, SR2

voltage (VSR2-VSR1) level

NOTE:

1. Due to the transformer, the load resistance seen by the circuit is four times RL.

CRYSTAL SPEC

27pF

XTAL1

CL

CL

XTAL2

27pF

Crystal mode

P ARAMETER SYMBOL LIMIT V ALUES UNIT
Frequency

f

Frequency calibration tolerance max. 100 ppm
Load capacitance CL max. 35 pF
Oscillator mode fundamental

External

oscillator

signal

NC

Driving from external source

XTAL1

XTAL2

7.680 MHz

XTAL1 CLOCK CHARACTERISTICS

P ARAMETER LIMIT V ALUES

MIN. MAX.

Duty cycle 1:2 2:1

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REV. 1.0, FEB. 23, 1999

6

AC CHARA CTERISTICS

MX97103

Temperature from 0 to 70°C, VDD=5V±5%
Inputs are driven to 2.4V for a logical "1" and to 0.4V f or
a logical "0". Timing meansurements are made at 2.0V
for a logical "1" and 0.8v for a logical "0". The AC-testing
output is loaded with a 150pF capacitor.

TIMING WAVEFORM

SERIAL INTERF A CE TIMING

DCL

tBCD

BCL

FSC

SDS1/2

DD/DU(O)

DD/DU(I)

tIOD

tIIHtIIS

0.45

2.4

2.0
TEST POINTS

0.8

Input/Output waveform for AC tests

tSSD

tFSD

2.0

0.8

DUT

C=150pF

GCI TIMING

PARAMETER SYMBOL MIN. MAX.
GCI output data delay tIOD 20ns 100ns
GCI input data setup tIIS 20ns
GCI input data hold tIIH 20ns
FSC strobe delay tFSD -20ns 20ns
SDS strobe delay tSDD 120ns
Bit clock delay tBCD -20ns 20ns

P/N:PM0564

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REV. 1.0, FEB. 23, 1999

PCI SHARED SIGNALS A.C. TIMING WAVEFORM

MX97103

CLK

OUTPUT

INPUT

1.5V

t1

1.5V

t5

Valid

t3

Valid

t2

t4

t6

PARAMETER SYMBOL MIN. MAX. NOTES
CLK signal valid delay t1 11ns CL=50pF
CLK to signal invalid delay t2 2ns
Hi-Z to active delay from CLK t3 2ns
Active to Hi-Z delay from CLK t4 28ns
Input signal valid setup time before CLK t5 7ns
Input signal hold time from CLK t6 0ns

PCI SIDEBAND SIGNALS A.C. TIMING WAVEFORM

CLK

OUTPUT

INPUT

1.5V

t1

1.5V

t5

Valid

t3

Valid

t2

t4

t6

PARAMETER SYMBOL MIN. MAX. NOTES
CLK to sideband signal valid delay t1 12ns CL=50pF
CLK to signal invalid delay t2 2ns
Hi-Z to active delay from CLK t3 2ns
Active to Hi-Z delay from CLK t4 28ns
Sideband signal valid setup time before CLK t5 12ns
Input signal hold time from CLK t6 0ns

P/N:PM0564

8

REV. 1.0, FEB. 23, 1999

APPLICATION

ISDN ACCESS ARCHITECTURE

MX97103

ISDN User Area

PCI bus

GCI CONNECTION

TE(1)

TE(8)

TE(1)

TE(1)

TE(8)

S

LT-S LT -T

LT-S

LT-S

Direct Subscriber Access

= MX97103

ISDN

central office

T

NT1

PBX(NT2)

where - TE is an ISDN terminal

- LT-S is a subscriber line termination

- LT-T is a trunk line termination

- LT is a trunk line termination in the central office

GCI

U

telephone

EEPROM

LT

line

LTNT1

P/N:PM0564

Data

Encryption

DSP-COFI

Speech

Processing

9

MX97103

S interface

PCI BUS

REV. 1.0, FEB. 23, 1999

VDD

VDD

C4

18pf

OSC

XTAL1

XTAL2

C3

18pf

7.68MHz

EEDO

EEDI
EECK
EECS

VDD

MX97103

3.3KR7

DO
DI

EEPROM

SK

(6 bit)

CS

10uF

DCL
FSC

DD

VSS

AVSS

MX97103

INTAN
RSTN
FRAMEN

CLK STOPN PAR PERRN TARDYN IDSELN IRDYN IDSEL CBEN[3:0] AD[31:0]

DU

SX1

SX2

SR1

SR2

R10

3.3K

R1
33

R3
33

R4

1.8K

47pF

R6

1.8K

47pF

VDD

D11

D12

R9

3.3K

D1

D5

DCLK
FS
DR
DX

D2

D6

D13

CODEC

D3

D4

D7

D9

D8

D10

D14

2:1

+5V

+5V

DC point

R5

8.2K

R8

8.2K

2:1

DC point

Over-

voltage

Pro-

tection

circuits

RJ45

P/N:PM0564

PCI BUS

REV. 1.0, FEB. 23, 1999

10

MX97103

TEST CIRCUIT

To test digital function separately, DTMC[TMODE] can be set to enab le the stim ulus inputs from test1~4 pins.

PIN DTMC SP2 S P1 SP0 I/O SIGNAL DESCRIPTION
TEST1 1 X X X I XRAMI1 test RAMI1 input signal
TEST2 1 X X X I XRAMI2 test RAMI2 input signal
TEST3 1 X X X I XZC test ZC input signal
TEST4 1 X X X I XI0N test I0N input signal
TEST1 0 0 0 0 O ARAMI1 RAMI1 from analog module
TEST2 0 0 0 0 O ARAMI2 RAMI2 from analog module
TEST3 0 0 0 0 O AZC ZC from analog module
TEST4 0 0 0 0 O SAMP SAMP from analog module
TEST1 0 0 0 1 O S[0] activation/deactivation state code
TEST2 0 0 0 1 O S[1]
TEST3 0 0 0 1 O S[2]
TEST4 0 0 0 1 O S[3]
TEST1 0 0 1 0 O MBAS1 TIC bus arbitration state code
TEST2 0 0 1 0 O MBAS2
TEST3 0 0 1 0 O CLS D channel collision
TEST4 0 0 1 0 O AI0N I0N from analog module
TEST1 0 0 1 1 O RFN layer sync.

For normal operation, DTMC should be set to 0. Test1~4 pins can be programmed to output internal signals for
monitoring purpose.

P/N:PM0564

REV. 1.0, FEB. 23, 1999

11

PACKAGE INFORMATION

100-PIN PLASTIC QUAD FLAT PACKA GE (PQFP)

ITEM MILLIMETERS INCHES

A 24.80±.40 .967±.016
B 20.00±.13 .787±.005
C 14.00±.13 .551±.005
D 18.80±.40 .740±.016
E 12.35 [REF] .486 [REF]
F .83 [REF] .033 [REF]
G .58 [REF] .023 [REF]
H .30 [Typ .] .012 [Typ.]
I .65 [Typ.] .026 [T yp.]
J 2.40 [Typ .] .094 [T yp.]
K 1.20 [T yp. ] .047 [Typ .]
L .15 [Typ.] .006 [T yp.]
M .10 max. .004 max.
N 2.75±.15 .018±.006
O .10 min. .004 min.
P 3.30 max. .103 max.

NOTE: Each lead centerline is located within .25 mm[.01
inch] of its true position [TP] at maximum material con­dition.

F

N

MX97103

A

B

80

81

100

130

M

51

50

E

CD

31

IHG

J

L

K

P

O

ORDERING INFORMATION

PART NO. PACKAGE
MX97103FC 100-PIN PQFP

P/N:PM0564

REV. 1.0, FEB. 23, 1999

12

MX97103

MACRONIX INTERNATIONAL CO., LTD.

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MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

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