Page 1
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
2-Wire 8912-Bit Serial CMOS EEPROM
This datasheet contains new product information. Analog Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
MTV24C08/24LC08 Revision.1.0 11/03/1999
1/15
FEATURES
• State- of- the- Art Architecture
- Non-volatile data storage
- Standard Voltage and Low Voltage Operation
5.0(Vcc = 4.5V to 5.5V) for MTV24C08
3.0(Vcc = 2.7V to 5.5V) for 24LC08
• 2 wire I2C serial interface
- Provides bidirectional data transfer protocol
• 16-byte page write mode
- Minimizes total write time per word
• Self-timed write-cycle(including auto-erase)
• Durable and Reliable
- 10 years data retention after 1000K write/erase cycles
- Minimum of 1,000,000 write/erase cycles per word
- Unlimited read cycles
- ESD protection
• Low standby current
GENERAL DESCRIPTION
The MTV24C08/24LC08 is a low cost, non-volatile, 4096-bit serial EEPROM with enhanced security device
and conforms to all specifications in I2C 2 wire protocol. The whole memory can be disabled (Write
Protected) by connecting the WP pin to Vcc. This section of memory then becomes unalterable unless WP
is switched to Vss. It is enhanced with security function. Every word of the memory has a programmable
security bit to permit whether it can be altered or not. The MTV24C08/24LC08's communication protocol
uses CLOCK(SCL) and DATA I/O(SDA) lines to synchronously clock data between the master (for example
a microcomputer)and the slave EEPROM devices(s) .In addition, the bus structure allows for a maximum of
16K of EEPROM memory. This supports the family in 2K, 4K, 8K, 16K devices, allowing the user to
configure the memory as the application requires with any combination of EEPROMs (not to exceed 16K).
MTV EEPROMs are designed and tested for application requiring high endurance, high reliability, and low
power consumption.
Page 2
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
MTV24C08/24LC08 Revision.1.0 11/03/1999
2/15
BLOCK DIAGRAM
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE
ADDRESS
REGISTER
&
COMPARATOR
WORD
ADDRESS
COUNTER
H.V.
GENERATION
TIMING
&
CONTROL
XDEC
EEPROM
ARRAY
DATA
BIT
64X16X8
YDEC
DATA
REGISTER
DOUT
ACK
WP
SDA
SCL
A0
A1
A2
VCC
VSS
Din
R/W ~ , device address bit A0
4
Dout
128
64
6
incload
ck
start cycle
128
Page 3
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
MTV24C08/24LC08 Revision.1.0 11/03/1999
3/15
PIN DESCRIPTIONS
SERIAL CLOCK (SCL)
The SCL input is used to clock all data into and out of the device.
SERIAL DATA (SDA)
SDA is a bidirection pin used to transfer data or security bit into and out of the device.
It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
Thus, the SDA bus requires a pull-up resistor to Vcc (typical 4.7K£[ for 100KHZ, 1K£[ for 400KHZ)
DEVICE ADDRESS INPUTS (A0, A1, A2)
Device address pin A2 are connected to Vcc or Vss to configure the EEPROM address.
The following table (Table A) shows the active pins across the 24C/LCXX device family.
TABLE A
Device A0 A1 A2
24C02/24LC02 ADR ADR ADR
24C04/24LC04 XP ADR ADR
MTV24C08/24LC08 XP XP ADR
24C016/24LC016 XP XP XP
ADR indicates the device address pin.
XP indicates that device address pin don’ t care but refers to an internal PAGE BLOCK memory segment.
WRITE PROTECTION (WP)
If WP is connected to Vcc, PROGRAM operation onto the whole memory will not be executed. READ
operations are possible. If WP is connected to Vss, normal memory operation is enabled, READ/WRITE
over the entire memory is possible.
1.0 FUNCTIONAL DESCRIPTION
1.1 APPLICATIONS
MTV’ s electrically erasable programmable read only memories (EEPROMs) offer valuable security features
including write protect function , two write modes ,three read modes, and a wide variety of memory size.
Typical applications for the I2C bus and 24C/LCXX memories are included in SANs(small-area-networks),
stereos, televisions, automobiles and other scaled-down systems that don't require tremendous speeds but
instead cost efficiency and design simplicity.
1.2 ENDURANCE AND DATA RETENTION
The MTV24C08/24LC08 is designed for applications requiring up to 1,000,000 programming cycles (BYTE
WRITE and PAGE WRITE). It provides 10 years of secure data retention, without power after the execution
of 1,000,000 programming cycles.
1.3 DEVICE OPERATION
Page 4
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
MTV24C08/24LC08 Revision.1.0 11/03/1999
4/15
The MTV24C08/24LC08 support a bi-directional bus oriented protocol. The protocol defines any device that
sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the
transfer is the master and the device that is controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive operations. Therefore, the MTV24C08/24LC08
is considered a slave in all applications.
Clock And Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. (Shown in Figures 1 and 2)
Start Condition
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition. (Shown in Figure 2)
Stop Condition
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition. (Shown in Figure 2)
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each
byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.
The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition. (Shown in
Figure 3)
Devices Addressing
After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device
code (1010) for the MTV24C08/24LC08, 3-bit device address (A2 A1 A0) and 1-bit value indicating the read
or write mode. All I2C EEPROMs use and internal protocol that defines a PAGE BLOCK size of 8K bits. The
MTV24C08/24LC08 contains four 2K-bits PAGE BLOCK, and the device address bits A0 and A1 are used
for determinating which PAGE BLOCK of memory segment the read/write operation will be proceeded in.
The eighth bit of slave address determines if the master device wants to read or write to the
MTV24C08/24LC08. (Refer to table B).
The MTV24C08/24LC08 monitor the bus for its corresponding slave address all the time. It generates an
acknowledge bit if the slave address was true and it is not in a programming mode.
TABLE B
Operation Control Code Chip Select R/W
Read
Write
1010
1010
A2 A1 A0
A2 A1 A0
1
0
A2 are used to access device address for MTV24C08/24LC08, 8K bits’ size device.
A0 ,A1are used to access page blocks ,size of 8K bits, in the MTV24C08/24LC08
Page 5
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
MTV24C08/24LC08 Revision.1.0 11/03/1999
5/15
WRITE OPERATIONS
Byte Write
Following the start signal from the master, the slave address is placed onto the bus by the
master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the ninth clock cycle.
Therefore the next byte transmitted by the master is the word address and will be written into the address
pointer of the MTV24C08/24LC08. After receiving another acknowledge signal from the MTV24C08/24LC08
the master device will transmit the data word to be written into the addressed memory location. The
MTV24C08/24LC08 acknowledges again and the master generates a stop condition. This initiates the
internal write cycle, and during this period the MTV24C08/24LC08 will not generate acknowledge signals.
(Shown in Figure 4)
Page Write
The write control byte, word address and the first data byte are transmitted to the MTV24C08/24LC08 in the
same way as in a byte write. But instead of generating a stop condition the master transmit up to 16 data
bytes to the MTV24C08/24LC08 which are temporarily stored in the on-chip page buffer and will be written
into the memory after the master has transmitted a stop condition. After the receipt of each byte, the two
lower order address pointer bits are internally incremented by one. The higher order six bits of the word
address remains constant. If the master should transmit more than 16 bytes prior to generating the stop
condition, the address counter will roll over and the previously received data will be overwritten. As with the
byte write operation, once the stop condition is received an internal write cycle will begin. (Shown in Figure
5).
Acknowledge Polling
Since the device will not acknowledge during a write cycle , this can be used to determine when the cycle is
complete (this feature can be used to maximize bus throughout). Once the stop condition for a write
command has been issued from the master, the device initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master sending a start condition followed by the control byte
for a write command (R/W = 0). If the device is still busy with the write cycle , then no ACK will returned. If
the cycle is complete then the device will return the ACK and the master can then proceed with the next
read or write commands.
Write Protection
Programming will not take place if the WP pin of the MTV24C08/24LC08 is connected to Vcc. The
MTV24C08/24LC08 will accept slave and byte addresses; but if the memory accessed is write protected by
the WP pin, the MTV24C08/24LC08 will not generate an acknowledge after the first byte of data has been
received, and thus the programming cycle will not be started when the stop condition is asserted.
READ OPERATIONS
Read operations are initiated in the same way as write operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types of read operations: current address read, random
read, and sequential read.
Page 6
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
MTV24C08/24LC08 Revision.1.0 11/03/1999
6/15
Current Address Read
The MTV24C08/24LC08 contains an address counter that maintains the address of the last accessed word,
internally incremented by one. Therefore if the previous access (either a read or write operation ) was to
address n, the next current address read operation would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the MTV24C08/24LC08 issues an acknowledge and transmits the
eight bit data word . The master will not acknowledge the transfer but does generate a stop condition and
the MTV24C08/24LC08 discontinues transmission. (Shown in Figure 6)
Random Read
Random read operations allow the master to access any memory location in a random manner. To perform
this type of read operation, first the word address must be set. This is done by sending the word address to
the MTV24C08/24LC08 as part of a write operation. After the word address is sent, the master generates a
start condition following the acknowledge. This terminates the write operation, but not before the internal
address pointer is set. Then the master issues the control byte again but with R/W bit set to a one. The
MTV24C08/24LC08 will then issue an acknowledge and transmit the eight bit data word. The master will not
acknowledge the transfer but does generate a stop condition and the MTV24C08/24LC08 discontinues
transmission. (Shown in Figure 7)
Sequential Read
Sequential reads are initiated by either a current address read or a random read. After the master receives a
data word, it responds with an acknowledge. As long as the E2PROM receives an acknowledge, it will
continue to increment the data words. When the memory address limit is reached, the data word address
will “roll over” and the sequential read will continue. The sequential read operation is terminated when the
master does not respond with a zero but does generate a following stop condition.
2.0 CONNECTION DIAGRAM
Page 7
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
MTV24C08/24LC08 Revision.1.0 11/03/1999
7/15
Pin Name
A0, A1 N.C.
A2 Device Address inputs
Vss Ground
SDA Data I/O
SCL Clock input
WP Write Protect
Vcc + 5 V or + 3 V
3.0 ABSOLUTE MAXIMUM RATINGS
Storage Temperature................................-65°C to + 125°C
Voltage with Respect to Ground.................-0.3 to + 6.5 V
NOTE: These are STRESS rating only. Appropriate conditions for operating these devices given elsewhere
may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
4.0 OPERATING CONDITIONS
Temperature under bias: MTV24C08/24LC08.......0°C to + 70°C
MTV24C08/24LC08-I.....-40°C to + 85°C
VCC
WP
SCL
SDA
A0
A1
A2
VSS
1
2
3
4 5
6
7
8
24C08
or
24LC08
TSSOP
VCC
WP
SCL
SDA
A0
A1
A2
VSS
VCC
WP
SCL
SDA
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
1
2
3
4 5
6
7
8
Dual-In-Line
package
SO package
(M8)
24C08
or
24LC08
24C08
or
24LC08
Page 8
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
MTV24C08/24LC08 Revision.1.0 11/03/1999
8/15
5.0 ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
(Vcc =5V +/- 10% ,MTV24C08/24LC08¡FVcc =3V +/- 10% ,24LC08)
MTV24C08/
24LC08
24LC08
Units
Symbol Parameter Conditions
Min Max Min Max
ICC1
Operating Current
(Program)
SCL = 100KHZ
CMOS Input Levels
— 10 — 8 mA
ICC2
Operating Current
(Read)
SCL = 100KHZ
CMOS Input Levels
— 2 — 2 mA
ISB
Standby Current SCL = SDA = 0 V
— 10 — 10
µA
IIL
Input Leakage VIN = 0 V to VCC
-1 +1 -1 +1
µA
IOL
Output Leakage VOUT = 0 V to Vcc
-1 +1 -1 +1
µA
VIL
Input Low Voltage
-0.1 0.8 -0.1
0.15 V
CC
V
VIH
Input High Voltage
2
VCC +0.2 0.8V
CC
VCC+0.2
V
VOL1
Output Low Voltage IOL = 2.1mA TTL
— 0.4 — 0.4 V
VOH1
Output High Voltage IOH = -400uA TTL
2.4 — 2.4 — V
VOL2
Output Low Voltage IOL = 10uA CMOS
— 0.2 — 0.2 V
VOH2
Output High Voltage IOH = -10uA CMOS
VCC-0.2 — VCC-0.2
— V
VLK
VCC Lockout Voltage
Programming Command
Can Be Executed
Default — Default — V
6.0 SWITCHING CHACTERISTICS (Under Operating Conditions )
AC ELECTRICAL CHARACTERISTICS
(Vcc =5V +/- 10% , MTV24C08¡FVcc =3V +/- 10% ,24LC08)
(Vcc =5V +/- 10% , MTV24C08 Fast Mode)
MTV24C08/
24LC08
MTV24C08
(Fast Mode)Parameter Symbol
Min Max Min Max
Units
Clock frequency Fscl 0 100 — 400 kHz
Clock high time Thigh 4000 — 600 — ns
Clock low time Tlow 4700 — 1200 — ns
SDA and SCL rise time Tr — 1000 — 300 ns
SDA and SCL fall time Tf — 300 — 300 ns
START condition hold time Thd:Sta 4000 — 600 — ns
START condition setup time Tsu:Sta 4700 — 600 — ns
Data input hold time Thd:Dat 0 — 0 — ns
Data input setup time Tsu:Dat 250 — 100 — ns
STOP condition setup time Tsu:Sto 4000 — 600 — ns
Output valid from clock Taa 300 3500 100 900 ns
Bus free time Tbuf 4700 — 1200 — ns
Data out hold time Tdh 300 — 50 — ns
Input filter spike suppression
(SDA and SCL pins)
Tsp — 100 — 50 ns
Write cycle time Twr — 10 — 10 ms
Page 9
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
MTV24C08/24LC08 Revision.1.0 11/03/1999
9/15
CAPACITANCE TA= 25°C , f=250KHZ
Symbol Parameter Max Units
CO
UT
Output capacitance 5 pF
CIN Input capacitance 5 pF
A. C. Conditions of Test
Input Pulse Levels Vcc x 0.1 to Vcc x 0.9
Input Rise and Fall times 10 ns
Input and Output Timming level Vcc x 0.5
Output Load 1 TTL Gate and CL = 100pf
7.0TIMING DIAGRAM
BUS TIMING
SCL
Figure 1. Data Validity
SDA
IN
SDA
OUT
SDA
SCL
Tf
Thd:Sta
Thd:Dat
Tsu:Dat
Tbuf
Tdh
Taa
Tlow
Thigh
Tlow
Tr
Tsu:StaTsu:Sta
DATA STABLE
DATA
CHANGE
Page 10
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
MTV24C08/24LC08 Revision.1.0 11/03/1999
10/15
Figure 2. Definition of Start and Stop
SDA
BITSTOPSTART BIT
SCL
81 9
ACKNOWLEDGE
START
Figure 3. Acknowledge Response from Receiver
SCL FROM MASTER
DATA OUTPUT FROM
TRANSMITTER
DATA OUTPUT FROM
RECEIVER
DATA n
BYTE
ADDRESS
SLAVE
ADDRESS
S
T
A
R
T
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
SLAVE
SDA LINE
BUS ACTIVITY
MASTER
Figure 4. Byte Write for Data
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
DATA n+15DATA n
BYTE
ADDRESS n
SLAVE
ADDRESS
S
T
A
R
T
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
SLAVE
Figure 5. Page Write for Data
S P
S
S
T
O
P
P
Page 11
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
MTV24C08/24LC08 Revision.1.0 11/03/1999
11/15
DATA
P
S
T
O
P
SLAVE
ADDRESS
S
T
A
R
T
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
SLAVE
A
C
K
Figure 6. Current Address Read for Data
s
P
S
T
O
P
S
S
T
A
R
T
S
S
T
A
R
T
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
SLAVE
SLAVE
ADDRESS
A
C
K
BYTE
ADDRESS n
A
C
K
SLAVE
ADDRESS
A
C
K
DATA n
Figure 7. Random Read for Data
S
S
T
A
R
T
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
SLAVE
SLAVE
ADDRESS
A
C
K
DATA n
A
C
K
DATA n+1
A
C
K
DATA n+x
A
C
K
P
S
T
O
P
Figure 8. Sequential Read for Data
Page 12
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
MTV24C08/24LC08 Revision.1.0 11/03/1999
12/15
9.0 PACKAGE DIAGRAMS
Plastic Dual-in-line Package (PDIP)
DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES
SYMBOLS
MIN NOM MAX MIN NOM MAX
A
¡Ð ¡Ð
5.33
¡Ð ¡Ð
0.210
A1 0.38
¡Ð ¡Ð
0.015
¡Ð ¡Ð
A2 3.25 3.30 3.45 0.128 0.130 0.136
B 0.36 0.46 0.56 0.014 0.018 0.022
B1 1.14 1.27 1.52 0.045 0.050 0.060
B2 0.18 0.99 1.17 0.032 0.039 0.046
C 0.20 0.25 0.33 0.008 0.010 0.013
D 9.12 9.30 9.53 0.359 0.366 0.375
E 7.62
¡Ð
8.26 0.300
¡Ð
0.325
E1 6.20 6.35 6.60 0.244 0.250 0.260
e
¡Ð
2.54
¡Ð ¡Ð
0.100
¡Ð
L 3.18
¡Ð ¡Ð
0.125
¡Ð ¡Ð
eB 8.38
¡Ð
9.40 0.330
¡Ð
0.370
S 0.71 0.84 0.97 0.028 0.033 0.038
7
15
(4X)
(4X)
E1
D
PIN #1 INDENT O0.025 DEEP 0.006-0.008
E-PIN O0.118 NOTE 9
AL
A2A1
B2
B1
B
e
S
E
C
eB
Page 13
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
MTV24C08/24LC08 Revision.1.0 11/03/1999
13/15
JEDEC Small Outline Package(SO-8)
DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES
SYMBOLS
MIN NOM MAX MIN NOM MAX
A 1.47 1.60 1.73 0.058 0.063 0.068
A1 0.10
¡Ð
0.25 0.004
¡Ð
0.010
A2
¡Ð
1.45
¡Ð ¡Ð
0.057
¡Ð
B 0.33 0.41 0.51 0.013 0.016 0.020
C 0.19 0.20 0.25 0.0075 0.008 0.0098
D 4.80 4.85 4.95 0.189 0.191 0.195
E 3.81 3.91 3.99 0.150 0.154 0.157
e
¡Ð
1.27
¡Ð ¡Ð
0.050
¡Ð
H 5.79 5.99 6.20 0.228 0.236 0.244
L 0.38 0.71 1.27 0.015 0.028 0.050
y
¡Ð ¡Ð
0.10
¡Ð ¡Ð
0.004
£c
0
O
¡Ð
8
O
0
O
¡Ð
8
O
A
0.015x45
VIEW "A"
L
H
E
A2
A1
B
e
y
7
(4X)
D
C
7
(4X)
VIEW "A"
Page 14
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
MTV24C08/24LC08 Revision.1.0 11/03/1999
14/15
8L TSSOP PACKAGE OUTLING DRAWING
DIMENSIONS IN MILLIMETERS
SYMBOLS
MIN NOM MAX
A 1.05 1.10 1.20
A1 0.05 0.10 0.15
A2
¡Ð
1.00 1.05
b 0.20 0.25 0.28
C
¡Ð
0.127
¡Ð
D 2.90 3.05 3.10
E 6.20 6.40 6.60
E1 4.30 4.40 4.50
e
¡Ð
0.65
¡Ð
L 0.50 0.60 0.70
L1 0.90 1.00 1.10
y
¡Ð ¡Ð
0.10
£c
0
O
4
O
8
O
A
E
E1
b
y
e
C
DETAIL A
DETAIL A
L 1
L
E1 L1
A2
A1
D
PIN 1 INDICATOR O0.70
SURFACE POLISHED
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