Datasheet MTV212MS32, MTV212MV32, MTV212MN32 Datasheet (MYSON)

MYSON

8051 core, 12MHz operating frequency.
512-byte RAM; 32K-byte program Flash-ROM support In System
Maximum 14 channels of 5V open-drain PWM DAC.

Watchdog timer with pro

VESA DDC interface, 3-channel A/D converter and a 32K-byte internal program Flash-ROM.

WR

WR

MTV212M32

TECHNOLOGY

(Rev 1.1)

8051 Embedded Monitor Controller

Flash Type with ISP

FEATURES

•

•

•

• Maximum 32 bi-directional I/O pins.

• SYNC processor for composite separation/insertion, H/V polarity/frequency check, polarity adjustment

and programmable clamp pulse output.

• Built-in self-test pattern generator with four free-running timings.

• Built-in low power reset circuit.

• Compliant with VESA DDC1/2B/2Bi/2B+ standard.

• Dual slave IIC addresses.

• Single master IIC interface for internal device communication.

• 4-channel 6-bit ADC.

•

• 40-pin DIP, 42-pin SDIP or 44-pin PLCC package.

grammable interval.

GENERAL DESCRIPTIONS

Programming(ISP).

The MTV212M32 micro-controller is an 8051 CPU core embedded device specially tailored to Monitor
applications. It includes an 8051 CPU core, 512-byte SRAM, SYNC processor, 14 built-in PWM DACs,

BL OCK DIAGRAM

STOUT
HBLANK
VBLANK
HSYNC
VSYNC
HCLAMP
HALFV
HALFH

P1.0-7
P2.0-2,P2.4-7

P3.2-0

P3.4-5
RST
X1
X2

8051

P0.0­7
RD

ALE

P0.0­7
RD

ALE

AD0-2

XFR

ADC

H/VSYNC
CONTROL

14 CHANNEL

PWM DAC

ISCL

DDC & IIC

INTERFACE

ISDA
HSCL
HSDA

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

Revision 1.1 - 1 - 2000/07/04

MYSON

MTV212M32

TECHNOLOGY

(Rev 1.1)

DEVICE SUMMARY

The MTV212M32 is one of the MTV212 family device. For other family devices information, please see the
table below:

Part Numb er USB ROM RAM Pack ag e

MTV212A16 No 16K 256 PDIP40, SDIP42, PLCC44
MTV212A24 No 24K 512 PDIP40, SDIP42, PLCC44
MTV212M32/A32 No 32K 512 PDIP40, SDIP42, PLCC44
MTV212A32U Yes 32K 768 PDIP40, SDIP42, PLCC44
MTV212A48U Yes 48K 768 PDIP40, SDIP42, PLCC44
MTV212A64U Yes 64K 1024 PDIP40, SDIP42, PLCC44

The usage of Auxiliary RAM (AUXRAM) is limited for targeted Flash ROM, the allowable XBANK (35h) bank
selection is defined as the table below:

Part Numb er RAM Xbnk2 Xbnk1 Xbnk 0

MTV212A16 256 - - ­ MTV212A24 512 0 0 0
0 0 1
MTV212M32/A32 512 0 0 0
0 0 1
MTV212A32U 768 0 0 0

0 0 1
0 1 0
0 1 1

MTV212A48U 768 0 0 0

0 0 1
0 1 0
0 1 1

MTV212A64U 1024 0 0 0

0 0 1
0 1 0
0 1 1
1 0 0
1 0 1

Revision 1.1 - 2 - 2000/07/04

MYSON

DA2/P5.2

DA1/P5.1

DA0/P5.0

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P2.2/AD2

P3.2/INT0

DA2/P5.2

DA1/P5.1

DA0/P5.0

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P2.2/AD2

P3.2/INT0

P1.624P1.7

P2.1/AD1

P1.5

P2.0/AD0

HSDA/P3.1/Txd
P1.1

P3.2/INT0

P1.2

P1.3

P1.4

23222120282726

25

NC

6543214443424140

NC

NC

DA0/P5.0

DA1/P5.1

DA2/P5.2
VSYNC

HSYNC

DA3/P5.3

DA4/P5.4

DA5/P5.5

19

18

VSS

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P2.2/AD2

P2.3/AD3

MTV212M32

TECHNOLOGY

(Rev 1.1)

PIN CONNECTION

Note: As long as the pin sequence is not changed, the 42 pin SDIP’s pin-out is negotiable according to
customer’s demand.

401

VSYNC

39

HSYNC

38

DA3/P5.3

37

DA4/P5.4

36

DA5/P5.5

35

DA8/HALFH

34

DA9/HALFV

33

HBLANK/P4.1

32

VBLANK/P4.0

31

DA7/HCLAMP

30

DA6/P5.6

29

P2.7/DA13

28

P2.6/DA12

27

P2.5/DA11

26

P2.4/DA10

25

HSCL/P3.0/Rxd

24

HSDA/P3.1/Txd

23

P2.0/AD0

22

P2.1/AD1

21

P1.7

RST

VDD

X2
X1

P1.0
P1.1

P1.2
P1.3
P1.4
P1.5
P1.6

2
3
4
5
6
7
8

MTV212M32

9

40 Pin

10
11
12
13
14
15
16
17
18
19
20

PDIP

NC
NC
NC

RST

VDD

X2
X1

P1.0
P1.1

P1.2
P1.3
P1.4

1
2
3
4
5
6
7
8

MTV212M32

9

42 Pin

10
11
12
13
14
15
16
17
18
19
20

SDIP

VSYNC

42

HSYNC

41
40

DA3/P5.3

39

DA4/P5.4

38

DA5/P5.5

37

DA8/HALFH

36

DA9/HALFV

35

HBLANK/P4.1

34

VBLANK/P4.0

33

DA7/HCLAMP

32

DA6/P5.6

31

P2.6/DA12

30

P2.5/DA11

29

P2.4/DA10

28

HSCL/P3.0/Rxd

27

HSDA/P3.1/Txd

26

P2.0/AD0

25

P2.1/AD1

24

P1.7

23

P1.6

2221

P1.5

RST

VDD

X2
X1

P1.0

7
8
9
10
11
12
13
14
15
16
17

MTV212M32

44 Pin

PLCC

39

DA8/HALFH

38

DA9/HALFV

37

HBLANK/P4.1

36

VBLANK/P4.0

35

DA7/HCLAMP

34

DA6/P5.6

33

P2.7/DA13

32

P2.6/DA12

31

P2.5/DA11

30

P2.4/DA10

29

HSCL/P3.0/Rxd

Revision 1.1 - 3 - 2000/07/04

MYSON

PWM DAC output (5V open drain) / General purpose I/O (5V open drain).
PWM DAC output (5V open drain) / General purpose I/O (5V open drain).
PWM DAC output (5V open drain) / General purpose I/O (5V open drain).

PWM DAC output (CMOS) /

PWM DAC output (5V open drain) /
PWM DAC output (5V open drain) /

MTV212M32

TECHNOLOGY

PIN DESCRIPTION

Name Type Description
DA2/P5.2
DA1/P5.1
DA0/P5.0
RST
VDD
P2.3/AD3
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P2.2/AD2
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.1/AD1
P2.0/AD0
HSDA/P3.1/Txd
HSCL/P3.0/Rxd
P2.4/DA10
P2.5/DA11
P2.6/DA12
P2.7/DA13
DA6/P5.6
DA7/HCLAMP
VBL ANK /P4.0
HBLA NK /P4.1
DA9/HALFV
DA8/HALFH
DA5/P5.5
DA4/P5.4
DA3/P5.3
HSYNC
VSYNC

I/O
I/O
I/O

Active high reset.

I

Positive Power Supply.

-

General purpose I/O (CMOS output or 8051 standard) / ADC Input.

I/O

Ground.

-

Oscillator output.

O

Oscillator input.

I

Master IIC data (5V open drain) / General purpose I/O (8051 standard) / T0

I/O

Master IIC clock (5V open drain) / General purpose I/O (8051 standard) / T1

I/O

Self-test video output (CMOS) / General purpose Output (CMOS).

O

General purpose I/O (CMOS output or 8051 standard) / ADC Input.

I/O

General purpose I/O (CMOS output or 8051 standard).

I/O

General purpose I/O (CMOS output or 8051 standard).

I/O

General purpose Input / INT0.

I

General purpose I/O (CMOS output or 8051 standard).

I/O

General purpose I/O (CMOS output or 8051 standard).

I/O

General purpose I/O (CMOS output or 8051 standard).

I/O

General purpose I/O (CMOS output or 8051 standard).

I/O

General purpose I/O (CMOS output or 8051 standard).

I/O

General purpose I/O (CMOS output or 8051 standard).

I/O

General purpose I/O (CMOS output or 8051 standard) / ADC Input.

I/O

General purpose I/O (CMOS output or 8051 standard) / ADC Input.

I/O

Slave IIC data (5V open drain) / General purpose I/O (8051 standard) / Txd

I/O

Slave IIC clock (5V open drain) / General purpose I/O (8051 standard) / Rxd

I/O

General purpose I/O (CMOS output or 8051 standard) / PWM DAC output (CMOS).

I/O

General purpose I/O (CMOS output or 8051 standard) / PWM DAC output (CMOS).

I/O

General purpose I/O (CMOS output or 8051 standard) / PWM DAC output (CMOS).

I/O

General purpose I/O (CMOS output or 8051 standard) / PWM DAC output (CMOS).

I/O

PWM DAC output (CMOS) / General purpose I/O (CMOS output or open drain I/O).

I/O

O

Vertical blank (CMOS) / General purpose Output (CMOS).

O

Horizontal blank (CMOS) / General purpose Output (CMOS).

O
O
O

PWM DAC output (CMOS) / General purpose I/O (CMOS output or open drain I/O).

I/O

PWM DAC output (CMOS) / General purpose I/O (CMOS output or open drain I/O).

I/O

PWM DAC output (CMOS) / General purpose I/O (CMOS output or open drain I/O).

I/O

Horizontal SYNC or Composite SYNC Input.

I

Vertical SYNC input.

I

Hsync clamp pulse output (CMOS).

(Rev 1.1)

vsync half freq. output (5V open drain).
hsync half freq. output (5V open drain).

Revision 1.1 - 4 - 2000/07/04

MYSON

MTV212M32

TECHNOLOGY

(Rev 1.1)

PIN CONFIGURATION

A “CMOS output pin” means it can sink and drive at least 4mA current. It’s not recommended to use such pin
as input fuction.
A “5V open drain pin” means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used
as input or output function and need an external pull up resistor.
A “8051 standard pin” is a pseudo open drain pin. It can sink at least 4mA current when output low level, and
drive at least 4mA current for 160nS when output transit from low to high, then keep drive 1 00uA to maintain
the pin at high level. It can be used as input or output function. It need an external pull up resistor when drive
heavy load device.

Output

Data

2 OSC
period

delay

4mA 10uA

4mA

Input
Data

120uA

8051 Stand ard Pin

Pin

Input
Data

Output

Data

Output

Data

4mA

CMOS Outp u t Pin

Pin

4mA

No Current

5V Open Drain Pin

Pin

4mA

Revision 1.1 - 5 - 2000/07/04

MYSON

FUNCTIONAL DESCRIPTIONS

2. Memory Allo catio n

2.4 Auxiliary RAM (AUXRAM)
divided into two banks, selected by XBANK register. Program can initialize

MTV212M32

TECHNOLOGY

1. 8051 CPU Core

(Rev 1.1)

MTV212M32 includes all 8051 functions with the following exceptions:

1.1 The external RAM access is restricted to XFRs/AUXRAM within the MTV212M32.

1.2 Port0, port3.3, port3.6 and port3.7 are not general-purpose I/O ports. They are dedicated to monitor
special application.

1.3 INT1 input pin is not provided, it is connected to special interrupt sources.

1.4 Port2 are shared with special function pins.

In addition, there are 2 timers, 5 interrupt sources and serial interface compatible with the standard 8051.

Note: All registers listed in this document reside in external RAM area (XFR). For internal RAM memory map
please refer to 8051 spec.

2.1 Internal Special Function Registers (SFR)

The SFR is a group of registers that are the same as standard 8051.

2.2 Internal RAM

There are total 256 bytes internal RAM in MTV212M32, same as standard 8052.

2.3 External Special Function Registers (XFR)

The XFR is a group of registers allocated in the 8051 external RAM area 00h - 7Fh. Most of the registers are
used for monitor control or PWM DAC. Program can initialize Ri value and use "MOVX" instruction to access
these registers.

There are total 256 bytes auxiliary RAM allocated in the 8051 external RAM area 80h - FFh. The AUXRAM is
instruction to access the AUXRAM.

FFh

Internal RAM

addressing only

80h
7Fh

Internal RAM

Accessible by

indirect

(Using

MOV A,@Ri

instruction)

SFR

Accessible by

direct addressing

FFh

80h
7Fh

Ri value and use "MOVX"

AUXRAM

Accessible by

indirect external

RAM addressing

(XBANK=0)(Using

MOVX A,@Ri

instruction)

Accessible by

indirect external

RAM addressing

(XBANK=1)(Using

MOVX A,@Ri

XFR

AUXRAM

instruction)

Accessible by

direct and indirect

addressing

00h

Accessible by

indirect external

RAM addressing

(Using

MOVX A,@Ri

instruction

00h

Revision 1.1 - 6 - 2000/07/04

MYSON

PWMF

MTV212M32

TECHNOLOGY

3. Chip Configu ratio n

The Chip Configuration registers define the chip pins function, as well as the functional blocks' connection,
configuration and frequency.

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PADMOD
PADMOD
PADMOD
PADMOD
PADMOD
PADMOD

OPTION
OPTION

XBANK

PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset)

DA13E = 1 → pin “P2.7/DA13” is DA13.
DA12E = 1 → pin “P2.6/DA12” is DA12.
DA11E = 1 → pin “P2.5/DA11” is DA11.
DA10E = 1 → pin “P2.4/DA10” is DA10.

AD3E = 1 → pin “P2.3/AD3” is AD3.
AD2E = 1 → pin “P2.2/AD2” is AD2.
AD1E = 1 → pin “P2.1/AD1” is AD1.
AD0E = 1 → pin “P2.0/AD0” is AD0.
P56E = 1 → pin “DA6/P5.6” is P5.6.
P55E = 1 → pin “DA5/P5.5” is P5.5.

P54E = 1 → pin “DA4/P5.4” is P5.4.
P53E = 1 → pin “DA3/P5.3” is P5.3.
P52E = 1 → pin “DA2/P5.2” is P5.2.
P51E = 1 → pin “DA1/P5.1” is P5.1.
P50E = 1 → pin “DA0/P5.0” is P5.0.
HIICE = 1 →pin “HSCL/P3.0/Rxd” is HSCL; pin “HSDA/P3.1/Txd” is HSDA.

IIICE = 1 → pin “ISDA/P3.4/T0” is ISDA; pin “ISCL/P3.5/T1” is ISCL.
HLFVE = 1 → pin “DA9/HALFV” is VSYNC half frequency output.

30h (w) DA13E DA12E DA11E DA10E AD3E AD2E AD1E AD0E
31h (w) P56E P55E P54E P53E P52E P51E P50E
32h (w) HIICE IIICE HLFVE HLFHE HCLPE P42E P41E P40E
3Ah (w) COP17 COP16 COP15 COP14 COP13 COP12 COP11 COP10
3Bh (w) COP27 COP26 COP25 COP24 COP23 COP22 COP21 COP20

3Ch (w) COP56 COP55 COP54 COP53

33h (w)
34h (w) SlvAbs1 SlvAbs0

35h (r/w) Xbnk2 Xbnk1 Xbnk0

= 0 → pin “P2.7/DA13” is P2.7.
= 0 → pin “P2.6/DA12” is P2.6.
= 0 → pin “P2.5/DA11” is P2.5.

= 0 → pin “P2.4/DA10” is P2.4.
= 0 → pin “P2.3/AD3” is P2.3.
= 0 → pin “P2.2/AD2” is P2.2.
= 0 → pin “P2.1/AD1” is P2.1.
= 0 → pin “P2.0/AD0” is P2.0.
= 0 → pin “DA6/P5.6” is DA6.

= 0 → pin “DA5/P5.5” is DA5.
= 0 → pin “DA4/P5.4” is DA4.
= 0 → pin “DA3/P5.3” is DA3.
= 0 → pin “DA2/P5.2” is DA2.
= 0 → pin “DA1/P5.1” is DA1.
= 0 → pin “DA0/P5.0” is DA0.

= 0 → pin “HSCL/P3.0/Rxd” is P3.0/Rxd; pin “HSDA/P3.1/Txd” is P3.1/Txd.
= 0 → pin “ISDA/P3.4/T0” is P3.4/T0; pin “ISCL/P3.5/T1” is P3.5/T1.

DIV253 FclkE IICpass ENSCL Msel MIICF1 MIICF0

(Rev 1.1)

Revision 1.1 - 7 - 2000/07/04

MYSON

is HSYNC half frequency output.

is HSYNC clamp pulse output.

is open drain I/O or CMOS PWM DAC.

is open drain I/O or CMOS PWM DAC.
is open drain I/O or CMOS PWM DAC.
is open drain I/O or CMOS PWM DAC.

MTV212M32

TECHNOLOGY

= 0 → pin “DA9/HALFV” is DA9.

HLFHE = 1 → pin “DA8/HALFH”

= 0 → pin “DA8/HALFH” is DA8.

HCLPE = 1 → pin “DA7/HCLAMP”

= 0 → pin “DA7/HCLAMP” is DA7.

P42E = 1 → pin “STOUT/P4.2” is P4.2.

= 0 → pin “STOUT/P4.2” is STOUT.

P41E = 1 → pin “HBLANK/P4.1” is P4.1.

= 0 → pin “HBLANK/P4.1” is HBLANK.

P40E = 1 → pin “VBLANK/P4.0” is P4.0.

= 0 → pin “VBLANK/P4.0” is VBLANK.

COP17 = 1 → pin “P1.7” is CMOS Output.

= 0 → pin “P1.7” is 8051 standard I/O.

COP16 = 1 → pin “P1.6” is CMOS Output.

= 0 → pin “P1.6” is 8051 standard I/O.

COP15 = 1 → pin “P1.5” is CMOS Output.

= 0 → pin “P1.5” is 8051 standard I/O.

COP14 = 1 → pin “P1.4” is CMOS Output.

= 0 → pin “P1.4” is 8051 standard I/O.

COP13 = 1 → pin “P1.3” is CMOS Output.

= 0 → pin “P1.3” is 8051 standard I/O.

COP12 = 1 → pin “P1.2” is CMOS Output.

= 0 → pin “P1.2” is 8051 standard I/O.

COP11 = 1 → pin “P1.1” is CMOS Output.

= 0 → pin “P1.1” is 8051 standard I/O.

COP10 = 1 → pin “P1.0” is CMOS Output.

= 0 → pin “P1.0” is 8051 standard I/O.

COP27 = 1 → pin “P2.7/DA13” is CMOS data Output.

= 0 → pin “P2.7/DA13” is 8051 standard I/O or CMOS PWM DAC Output.

COP26 = 1 → pin “P2.6/DA12” is CMOS data Output.

= 0 → pin “P2.6/DA12” is 8051 standard I/O or CMOS PWM DAC Output.

COP25 = 1 → pin “P2.5/DA11” is CMOS data Output.

= 0 → pin “P2.5/DA11” is 8051 standard I/O or CMOS PWM DAC Output.

COP24 = 1 → pin “P2.4/DA10” is CMOS data Output.

= 0 → pin “P2.4/DA10” is 8051 standard I/O or CMOS PWM DAC Output.

COP23 = 1 → pin “P2.3/AD3” is CMOS data Output.

= 0 → pin “P2.3/AD3” is 8051 standard I/O or ADC Input.

COP22 = 1 → pin “P2.2/AD2” is CMOS data Output.

= 0 → pin “P2.2/AD2” is 8051 standard I/O or ADC Input.

COP21 = 1 → pin “P2.1/AD1” is CMOS data Output.

= 0 → pin “P2.1/AD1” is 8051 standard I/O or ADC Input.

COP20 = 1 → pin “P2.0/AD0” is CMOS data Output.

= 0 → pin “P2.0/AD0” is 8051 standard I/O or ADC Input.

COP56 = 1 → pin “DA6/P5.6” is CMOS data Output.

= 0 → pin “DA6/P5.6”

COP55 = 1 → pin “DA5/P5.5” is CMOS data Output.

= 0 → pin “DA5/P5.5”

COP54 = 1 → pin “DA4/P5.4” is CMOS data Output.

= 0 → pin “DA4/P5.4”

COP53 = 1 → pin “DA3/P5.3” is CMOS data Output.

= 0 → pin “DA3/P5.3”

(Rev 1.1)

Revision 1.1 - 8 - 2000/07/04

MYSON

Auxiliary RAM bank switch.

Each PWM DAC converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of

MTV212M32

TECHNOLOGY

OPTION (w) : Chip option configuration (All are "0" in Chip Reset).

PWMF = 1 → select 94KHz PWM frequency.

= 0 → select 47KHz PWM frequency.

DIV253 = 1 → PWM pulse width is 253 step resolution.

= 0 → PWM pulse width is 256 step resolution.
FclkE = 1 → Double CPU clock freq.
IICpass = 1 → HSCL/HSDA pin bypass to ISCL/ISDA pin in DDC2 mode.

= 0 → Separate Master and Slave IIC block.
ENSCL = 1 → Enable slave IIC block to hold HSCL pin low while MTV212M32 can't catch-up
the external master's speed.
Msel = 1 → Master IIC block connect to HSCL/HSDA pins.

= 0 → Master IIC block connect to ISCL/ISDA pins.
MIICF1,MIICF0 = 1,1 → select 400KHz Master IIC frequency.

= 1,0 → select 200KHz Master IIC frequency.
= 0,1 → select 50KHz Master IIC frequency.
= 0,0 → select 100KHz Master IIC frequency.

SlvAbs1,SlvAbs0 : Slave IIC block A's slave address length.

= 1,0 → 5-bits slave address.
= 0,1 → 6-bits slave address.
= 0,0 → 7-bits slave address.

XBANK (r/w) :

Xbnk[2:0] = 0 → Select AUXRAM bank 0.

= 1 → Select AUXRAM bank 1.
= 2 → Select AUXRAM bank 0.
= 3 → Select AUXRAM bank 1.
= 4 → Select AUXRAM bank 0.
= 5 → Select AUXRAM bank 1.

(Rev 1.1)

4. Extra I/O

The extra I/O is a group of I/O pins located in XFR area. Port4 is output mode onl y. Port5 can be used as
both output and input, because Port5's pin is open drain type, user must write Port5's corresponding bit to
"1" in input mode.

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PORT4
PORT5

PORT4 (w) : Port 4 data output value.
PORT5 (r/w) : Port 5 data input/output value.

5. PWM DAC

PWM clk is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253
or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high
output. If DIV253=0, the output will pulse low at least once even if the DAC register's content is FFH. Writing
00H to DAC register generates stable low output.

38h (w) P42 P41 P40

39h (r/w) P56 P55 P54 P53 P52 P51 P50

Revision 1.1 - 9 - 2000/07/04

MYSON

Pulse width of PWM DAC 0
Pulse width of PWM DAC 1
Pulse width of PWM DAC 2
Pulse width of PWM DAC 3
Pulse width of PWM DAC 4
Pulse width of PWM DAC 5
Pulse width of PWM DAC 6
Pulse width of PWM DAC 7
Pulse width of PWM DAC 8

Pulse width of PWM DAC 9
Pulse width of PWM DAC 10
Pulse width of PWM DAC 11
Pulse width of PWM DAC 12
Pulse width of PWM DAC 13

* All of PWM DAC converters are centered with value 80h after power on.

inputs presence check, frequency counting, polarity detection and control, as well as the protection of
function block treat any pulse shorter than one OSC period as noise.

Hself

Hpol

CVpre

Vbpl

VSYNC

Vpre

Vfreq

Vpol

VBLANK

Vself

XOR

HSYNC

CVSYNC

Hpre

Hfreq

Hbpl

XOR

HBLANK

MTV212M32

TECHNOLOGY

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8

DA9
DA10
DA11
DA12
DA13

DA0-13 (r/w) : The output pulse width control for DA0-13.

6. H/V SYNC Processing

20h (r/w)
21h (r/w)
22h (r/w)
23h (r/w)
24h (r/w)
25h (r/w)
26h (r/w)
27h (r/w)
28h (r/w)
29h (r/w)
2Ah (r/w)

2Bh (r/w)
2Ch (r/w)
2Dh (r/w)

(Rev 1.1)

The H/V SYNC processing block performs the functions of composite signal separation /insertion, SYNC
VBLANK output while VSYNC speed up in high DDC communication clock rate. The present and frequency

Digital Filter

Digital Filter

Present

Check

Polarity Check &

Freq. Count

XOR

Present

Check

Polarity Check &

Sync Seperator

Present Check &

Freq. Count

Composite

Pulse Insert

XOR

H/V SYNC Processor Block Diagram

Revision 1.1 - 10 - 2000/07/04

MYSON

6.2 H/V Frequency Counter

VSYNC/CVSYNC is present or continuously updated when VSYNC/CVS YNC is non-present. The 12 bits

CVpre flag interrupt may be disabled when S/W disable the composite function.

MTV212M32

TECHNOLOGY

6.1 Composite SYNC separation/insertion
The MTV212M32 continuously monitors the input HSYNC, if the vertical SYNC pulse can be extracted from
the input, a CVpre flag is set and user can select the extracted "CVSYNC" for the source of polarity check,
frequency count, and VBLANK output. The CVSYNC will have 8us delay compared to the original signal.
The MTV212M32 can also insert pulse to HBLANK output during composite VSYNC’s active time. The insert
pulse’s width is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC. The HBLANK
pulse can be disable or enable by setting “NoHins” control bit.

MTV212M32 can discriminate HSYNC/VSYNC frequency and saves the information in XFRs. The 14 bits
Hcounter counts the time of 64xHSYNC period, then load the result into the HCNTH/HCNTL latch. The
output value will be [(128000000/H-Freq) - 1], updated once per VSYNC/CVSYNC period when

Vcounter counts the time between two VSYNC pulses, then load the result into the VCNTH/VCNTL latch.
The output value will be (62500/V-Freq), updated every VSYNC/CVSYNC perio d. An extra overflow bit
indicates the condition of H/V counter overflow. The VFchg/HFchg interrupt is set when VCNT/HCNT value
changes or overflow. Table 4.2.1 and table 4.2.2 shows the HCNT/VCNT value under the operations of
12MHz.

6.2.1 H-Freq Table

H-Freq(KHZ)

1
2
3
4
5
6
7
8

9
10
11
12

31.5

37.5

43.3

46.9

53.7

60.0

68.7

75.0

80.0

85.9

93.8

106.3

Outpu t Value (14 bit s )

12MHz OSC (hex / dec)

0FDEh / 4062
0D54h / 3412
0B8Bh / 2955
0AA8h / 2728
094Fh / 2383
0854h / 2132
0746h / 1862
06AAh / 1706
063Fh / 1599
05D1h / 1489
0554h / 1364
04B3h / 1203

(Rev 1.1)

6.2.2 V-Freq Table

V-Freq(Hz)

1

2

3

4

5

6

6.3 H/V Present Check
The Hpresent function checks the input HSYNC pulse, Hpre flag is set when HSYNC is over 10KHz or
cleared when HSYNC is under 10Hz. The Vpresent function checks the input VSYNC pulse, the Vpre flag is
set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. The HPRchg interrupt is set when
the Hpre value changes. The VPRchg interrupt is set when the Vpre/CVpre value change. However, the

Revision 1.1 - 11 - 2000/07/04

56
60
70
72
75
85

Outpu t value (12bits)

12MHz OSC (hex / dec)

45Ch / 1116
411h / 1041
37Ch / 892
364h / 868
341h / 833
2DFh / 735

MYSON

6.4 H/V Polarity Detect
The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse
duration is longer than that of low pulse, the negative polarity is asserted; otherwise, positi ve polarity is

6.5 Output HBLANK/VBLANK Control and Polarity Adjust

MTV212M32

TECHNOLOGY

asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when the
Vpol value changes.

The HBLANK is the mux output of HSYNC, composite Hpulse and self-test horizontal pattern. The VBLANK
is the mux output of VSYNC, CVSYNC and self-test vertical pattern. The mux selection and output polarity
are S/W controllable. The VBLANK output is cut off when VSYNC frequency is over 200Hz. The
HBLANK/VBLANK shares the output pin with P4.1/ P4.0.

6.6 Self Test Pattern Generator
This generator can generate 4 display patterns for testing purpose, which are positive cross-hatch, negative
cross-hatch, full white, and full black (showed as following figure). The HBLANK output frequency of the
pattern can be chosen to 95.2KHz, 63.5KHz, 47.6KHz and 31.75KHz. The VBLANK output frequency of the
pattern is 72Hz or 60Hz. It is originally designed to support monitor manufacturer to do burn-in test, or offer
end-user a reference to check the monitor. The generator's output STOUT shares the output pin with P4.2.

Display Region

(Rev 1.1)

Positive cross-hatch Negative cross-hatch

Full white Full black

Revision 1.1 - 12 - 2000/07/04

MYSON

* 8 x 8 blocks of cross hatch pattern in display region.

width and polarity is S/W controllable.

flag is set each time when MTV212M32 detects a VSYNC pulse. The flag is cleared by S/W writing a "0".

MTV212M32

TECHNOLOGY

MTV212M32 Self-Test pattern timing

63.5KHz, 60Hz 47.6KHz, 60Hz 31.7KHz, 60Hz 95.2KHz, 72Hz

time H dots time H dots time H dots time H dots
Hor. Total time (A) 15.75us 1280 21.0us 1024 31.5us 640 10.5us 1600
Hor. Active time (D) 12.05us 979.3 16.07us 783.2 24.05us 488.6 8.03us 1224
Hor. F. P. (E) 0.2us 16.25 0.28us 12 0.45us 9 0.14us 21
SYNC pulse width (B) 1.5us 122 2us 90 3us 61 1.0us 152
Hor. B. P. (C) 2us 162.54 2.67us 110 4us 81.27 1.33us 203

(Rev 1.1)

time V lines time V lines time V lines time V lines
Vert. Total time (O) 16.66ms 1024 16.66ms 768 16.66ms 480 13.89ms 1200
Vert. Active time (R) 15.65ms 962 15.65ms 721.5 15.65ms 451 13.03ms 1126
Vert. F. P. (S) 0.063ms 3.87 0.063ms 2.9 0.063ms 1.82 0.052ms 4.5
SYNC pulse width (P) 0.063ms 3.87 0.063ms 2.9 0.063ms 1.82 0.052ms 4.5
Vert. B. P. (Q) 0.882ms 54.2 0.882ms 40.5 0.882ms 25.4 0.756ms 65

6.7 HSYNC Clamp Pulse Output
The HCLAMP output is active by setting “HCLPE” control bit. The HCLAMP’s leading edge position, pulse

6.8 VSYNC Interrupt
The MTV212M32 check the VSYNC input pulse and generate an interrupt at its leadi ng edge. The VSYNC

6.9 H/V SYNC Processor Register

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

HVSTUS

HCNTH

HCNTL

VCNTH

VCNTL

40h (r) CVpre Hpol Vpol Hpre Vpre Hoff Voff
41h (r) Hovf HF13 HF12 HF11 HF10 HF9 HF8
42h (r) HF7 HF6 HF5 HF4 HF3 HF2 HF1 HF0
43h (r) Vovf VF11 VF10 VF9 VF8
44h (r) VF7 VF6 VF5 VF4 VF3 VF2 VF1 VF0

Revision 1.1 - 13 - 2000/07/04

MYSON

EVsync

The status of polarity, present and static level for HSYNC and VSYNC.

HSYNC input is positive polarity.

VSYNC (CVSYNC) is negative polarity.

Freq counter is overflow, this bit is clear by H/W when condition removed.

Freq counter's low byte.

positive polarity HBLANK output.

positive polarity VBLANK output.

MTV212M32

HVCTR0
HVCTR2
HVCTR3

INTFLG

INTEN

HVSTUS (r) :

CVpre = 1 → The extracted CVSYNC is present.
H

pol

V

pol

H

pre

V

pre

H

off*

V

off*

*H

off

TECHNOLOGY

40h (w) C1 C0 NoHins HBpl VBpl
42h (w) Selft STF1 STF0 Rt1 Rt0 STE
43h (w) CLPEG CLPPO CLPW2 CLPW1 CLPW0

48h (r/w) HPRchg VPRchg HPLchg VPLchg HFchg VFchg Vsync

49h (w) EHPR EVPR EHPL EVPL EHF EVF

= 0 → The extracted CVSYNC is not present.
= 1 →

= 0 → HSYNC input is negative polarity.
= 1 → VSYNC (CVSYNC) is positive polarity.

= 0 →
= 1 → HSYNC input is present.

= 0 → HSYNC input is not present.
= 1 → VSYNC input is present.

= 0 → VSYNC input is not present.
= 1 → HSYNC input's off level is high.

= 0 → HSYNC input's off level is low.
= 1 → VSYNC input's off level is high.

= 0 → VSYNC input's off level is low.

and V

are valid when H

off

pre=0

or V

pre=0.

(Rev 1.1)

HCNTH (r) : H-Freq counter's high bits.

Hovf = 1 → H­HF13 - HF8 : 6 high bits of H-Freq counter.

HCNTL (r) : H-Freq counter's low byte.
VCNTH (r) : V-Freq counter's high bits.

Vovf = 1 → V-Freq counter is overflow, this bit is clear by H/W when condition removed.
VF11 - 8 : 4 high bits of V-Freq counter.

VCNTL (r) : V-
HVCTR0 (w) : H/V SYNC processor control register 0.

HVCTR2 (w) : Self-test pattern generator control.

C1, C0 = 1,1 → Select CVSYNC as the polarity, freq and VBLANK source.

= 1,0 → Select VSYNC as the polarity, freq and VBLANK source.
= 0,0 → Disable composite function.
= 0,1 → H/W auto switch to CVSYNC when CVpre=1 and VSpre=0.

NoHins = 1 → HBLANK has no insert pulse in composite mode.

= 0 → HBLANK has insert pulse in composite mode.

HB

VB

S

STF1,STF0 = 1,1 → 95.2KHz(horizontal)/72Hz(vertical) output selected.

= 1 → negative polarity HBLANK output.

pl

= 0 →
= 1 → negative polarity VBLANK output.

pl

= 0 →

= 1 → enable generator.

elft

= 0 → disable generator.

= 1,0 → 63.5KHz(horizontal)/60Hz(vertical) output selected.

Revision 1.1 - 14 - 2000/07/04

MYSON

Positive polarity clamp pulse output.
Negative polarity clamp pulse output.

: CLPW0 : Pulse width of clamp pulse is

:CLPW0) + 1] x 0.167

enable bit is set, the 8051 core's INT1 source will be driven by a zero level. Soft ware MUST

Clear HSYNC polarity change flag.
Clear VSYNC polarity change flag.

Indicates a HSYNC polarity change.

Enable VSYNC polarity change interrupt.

MTV212M32

TECHNOLOGY

= 0,1 → 47.6KHz(horizontal) /60Hz(vertical) output selected.
= 0,0 → 31.75KHz(horizontal) /60Hz(vertical) output selected.

Rt1,Rt0 = 0,0 → positive cross-hatch pattern output.

= 0,1 → negative cross-hatch pattern output.
= 1,0 → full white pattern output.
= 1,1 → full black pattern output.

STE = 1 → enable STOUT output.

= 0 → disable STOUT output.

HVCTR3 (w) : HSYNC clamp pulse control register.

CLPEG = 1 → Clamp pulse follows HSYNC leading edge.

= 0 → Clamp pulse follows HSYNC trailing edge.

CLPPO = 1 →

= 0 →

CLPW2

INTFLG (w) : Interrupt flag. An interrupt event will set its i ndividual flag, and, if the corresponding interrupt

clear this register while serve the interrupt routine.

HPRchg= 1 → No action.
VPRchg= 1 → No action.
HPLchg= 1 → No action.
VPLchg= 1 → No action.
HFchg = 1 → No action.
VFchg = 1 → No action.

Vsync = 1 → No action.

[(CLPW2

= 0 → Clear HSYNC presence change flag.
= 0 → Clear VSYNC presence change flag.
= 0 →
= 0 →
= 0 → Clear HSYNC frequency change flag.
= 0 → Clear VSYNC frequency change flag.

= 0 → Clear VSYNC interrupt flag.

µs for 12MHz X’tal selection.

(Rev 1.1)

INTFLG (r) : Interrupt flag.

HPRchg= 1 → Indicates a HSYNC presence change.
VPRchg= 1 → Indicates a VSYNC presence change.
HPLchg= 1 →
VPLchg= 1 → Indicates a VSYNC polarity change.
HFchg = 1 → Indicates a HSYNC frequency change or counter overflow.
VFchg = 1 → Indicates a VSYNC frequency change or counter overflow.
Vsync = 1 → Indicates a VSYNC interrupt.

INTEN (w) : Interrupt enable.

EHPR = 1 → Enable HSYNC presence change int errupt.
EVPR = 1 → Enable VSYNC presence change interrupt.
EHPL = 1 → Enable HSYNC polarity change interrupt.
EVPL = 1 →
EHF = 1 → Enable HSYNC frequency change / counter overflow interrupt.
EVF = 1 → Enable VSYNC frequency change / counter overf low interrupt.
EVsync = 1 → Enable VSYNC interrupt.

Revision 1.1 - 15 - 2000/07/04

MYSON

DbufI interrupt is automatically cleared when Software writes a new data byte to DBUF. The

access EEPROM directly.

Under such condition, the HSDA and HSCL are directly bypassed to ISDA and ISCL pins . The other way to

RCABUF/RCBBUF register when a data byte is received. The first byte loaded is word address (slave
the RCABUF/RCBBUF is loaded. If S/W can't read out the RCABUF/RCBBUF in time, the next byte in shift

every time when shift register reads out the data from TX ABUF/TXBBUF.

SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register.

The TXAI/TXBI is cleared by writing TXABUF/TXBBUF. If the control

The master mode IIC block can be connected to the ISDA /ISCL pins or the HSDA/HSCL pins, select by
Msel control bit. Its speed can be selected to 50KHz-400KHz by S/W setting the MIICF1/MIICF0 control bit.

and the display information share the common EEPROM, precaution m ust be taken to avoid bus conflicting
while Msel=0. In DDC1 mode or IICpass=0, the ISCL/ISDA is controlled by MTV212M32 only. In DDC2

MTV212M32

TECHNOLOGY

7. DDC & IIC Int er face

7.1 DDC1 Mode
The MTV212M32 enters DDC1 mode after Reset. In this mode, VSYNC is used as data clock. The HSCL pin
should remain at high. The data output to the HSDA pin is taken from a shift register in MTV212M32. The
shift register fetch data byte from the DDC1 data buffer (DBUF) then send it in 9 bits packet formats which
includes a null bit (=1) as packet separator. The DBUF set the DbufI interrupt flag when the shift register
read out the data byte from DBUF. Software needs to write EDID data to DBUF as soon as the DbufI is set.
The
interrupt can be mask or enable by EDbufI control bit.

7.2 DDC2B Mode
The MTV212M32 switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once
MTV212M32 enters DDC2B mode, S/W can set IICpass control bit to allow HOST

perform DDC2 function is to clear IICpass and config the Slave A IIC block to act as EEPROM behavior. The
Slave A block's slave address can be chosen by S/W as 5-bits, 6-bits or 7-bits. For example, if S/W choose
5-bits slave address as 10100b, the slave IIC block A will respond to slave address 10100xx b and save the 2
LSB "xx" in XFR. This feature enables MTV212M32 to meet PC99 requirement.
The MTV212M32 will return to DDC1 mode if HSCL is kept high for 128 VSYNC clock period. However, it
will lock in DDC2B mode if a valid IIC address (1010xxxb) has been detected on HSCL/HSDA bus. The
DDC2 flag reflects the current DDC status, S/W may clear it by writing a "0" to it.

(Rev 1.1)

DbufI

7.3 Slave Mode IIC function Block
The slave mode IIC block is connected to HSDA and HSCL pins. This block can receive/transmit data using
IIC protocol. There are 2 slave addresses MTV212M32 can respond to. S/W may write the
SLVAADR/SLVBADR register to determine the slave addresses. The SlaveA address can be configured to
5-bits, 6-bits or 7-bits by S/W setting the SlvAbs1 and SlvAbs0 control bits.
In receive mode, the block first detects IIC slave address match condition then issues a SlvAMI/SlvBMI
interrupt. If the matched address is slave A, MTV212M32 will save the matched address's 2 LSB bits to
SlvAlsb1 and SlvAlsb0 register. The data from HSDA is shifted into shift register then written to

address is dropped). This block also generates a RCAI/RCBI (receive buff er full interrupt) every time when
register will not be written to RCABUF/RCBBUF and the slave block return NACK to the master. This feature

guarantees the data integrity of communication. The WadrA/WadrB flag can tell S/W that if the data in
RCABUF/RCBBUF is a word address.
In transmit mode, the block first detects IIC slave address match condition then issues a SlvAMI/SlvBMI
interrupt. In the mean time, the SlvAlsb1/SlvAlsb0 is also updated if the matched address is sla ve A, and the
data pre-stored in the TXABUF/TXBBUF is loaded into shift register, result in TXABUF/T XBBUF empty and
generates a TXAI/TXBI (transmit buffer empty interrupt). S/W should write the TXABUF/TXBBUF a new byte
for next transfer before shift register empty. Fail to do this will cause data corrupt. The TXAI/TXBI occurs

The SlvAMI/
cleared by reading RCABUF/RCBBUF.
bit ENSCL is set, the block will hold HSCL low until the RCAI/RCBI/TXAI/TXBI is cleared.

*Please see the attachments about "Slave IIC Block Timing".

7.4 Master Mode IIC Function Block

The RCAI/RCBI is

The software program can access the external IIC device through this interface. Since th e ED ID/VDIF data

Revision 1.1 - 16 - 2000/07/04

MYSON

IICpass flag is set, the host may access the EEPROM directl y. Soft ware can test the HSCL
condition by reading the
HSCL's rising edge. S/W can launch the master IIC transmit/receive by clearing the P bit. Once P=0,

1. Write MBUF the Slave Address.

1. Write MBUF the Slave Address.

6. After the MTV212M32 receives a new byte, the

WadrB

WadrA

SLVAADR

SLVBADR

In master receive mode, NACK is returned by MTV212M32.

In master receive mode, ACK is returned by MTV212M32.

MTV212M32

TECHNOLOGY

mode and

MTV212M32 will hold HSCL low to isolate the host's access to EEPROM. A summary of master IIC access
is illustrated as follows.

7.4.1. To write IIC Device

2. Set S bit to Start.

3. After the MTV212M32 transmit this byte, a MbufI interrupt will be triggered.

4. Program can write MBUF to transfer next byte or set P bit to stop.
* Please see the attachments about "Master IIC Transmit Timing".

7.4.2. To read IIC Device

2. Set S bit to Start.

3. After the MTV212M32 transmit this byte, a MbufI interrupt will be triggered.

4. Set or reset the MAckO flag according to the IIC protocol.

5. Read out MBUF the useless byte to continue the data transfer.

7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation.

Hbusy flag, which is set in case of HSCL=0, and keeps high for 100uS after the

MbufI interrupt is triggered again.

(Rev 1.1)

* Please see the attachments about "Master IIC Receive Timing".

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

IICCTR
IICSTUS
IICSTUS

INTFLG
INTFLG

INTEN
MBUF

RCABUF

TXABUF

RCBBUF

TXBBUF

DBUF

IICCTR (r/w) : IIC interface contro l register.

DDC2 = 1 → MTV212M32 is in DDC2 mode, write "0" can clear it.
MAckO = 1 →

S, P = ↑, 0 → Start condition when Master IIC is not during transf er.

* A write/read MBUF operation can be recognized only after 10us of the MbufI flag's rising edge.

00h (r/w) DDC2 MAckO P S

01h (r)
02h (r) MAckIn Hifreq Hbusy

03h (r) TXBI RCBI SlvBMI TXAI RCAI SlvAMI DbufI MbufI
03h (w) SlvBMI SlvAMI MbufI
04h (w) ETXBI ERCBI ESlvBMI ETXAI ERCAI ESlvAMI EDbufI EMbufI

05h (r/w) Master IIC receive/transmit data buffer

06h (r) Slave A IIC receive buffer
06h (w) Slave A IIC transmit buffer
07h (w) ENSlvA Slave A IIC address

08h (r) Slave B IIC receive buffer
08h (w) Slave B IIC transmit buffer
09h (w) ENSlvB Slave B IIC address

0Ah (w) DDC1 transmit data buffer

= 0 → MTV212M32 is in DDC1 mode.
= 0 →

= X, ↑ → Stop condition when Master IIC is not during transfer.
= 1, X → Will resume transfer after a read/write MBUF operat ion.
= X, 0 → Force HSCL low and occupy the master IIC bus.

SlvRWB SAckIn SLVS SlvAlsb1 SlvAlsb0

IICSTUS (r) : IIC interface status register.

WadrB = 1 → The data in RCBBUF is word address.
WadrA = 1 → The data in RCABUF is word address.

Revision 1.1 - 17 - 2000/07/04

MYSON

enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear

MTV212M32

TECHNOLOGY

SlvRWB = 1 → Current transfer is slave transmit

= 0 → Current transfer is slave receive

SAckIn = 1 → The external IIC host resp ond NACK.
SLVS = 1 → The slave block has detected a START, cleared when STOP detected.
SlvAlsb1,SlvAlsb0 : The 2 LSB which host send to Slave A block.
MAckIn = 1 → Master IIC bus error, no ACK received from the slave IIC device.

= 0 → ACK received from the slave IIC device.

Hifreq = 1 → MTV212M32 has detected a higher than 200Hz clock on the VSYNC pin.
Hbusy = 1 → Host drives the HSCL pin to low.

INTFLG (w) : Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt

this register while serve the interrupt routine.

SlvBMI = 1 → No action.

= 0 → Clear SlvBMI flag.

SlvAMI = 1 → No action.

= 0 → Clear SlvAMI flag.

MbufI = 1 → No action.

= 0 → Clear Master IIC bus interrupt flag (MbufI).

INTFLG (r) : Interrupt flag.

TXBI = 1 → Indicates the TXBBUF need a new data byte, clear by writing TXBBUF.
RCBI = 1 → Indicates the RCBBUF has received a new data byte, clear by reading RCBBUF.
SlvBMI = 1 → Indicates the slave IIC address B match condition.
TXAI = 1 → Indicates the TXABUF need a new data byte, clear by writing TXABUF.
RCAI = 1 → Indicates the RCABUF has received a new data byte, clear by reading RCABUF.
SlvAMI = 1 → Indicates the slave IIC address A match condition.
DbufI = 1 → Indicates the DDC1 d ata buffer need a new data byte, clear by writing DBUF.
MbufI = 1 → Indicates a byte is sent/received to/from the master IIC bus.

(Rev 1.1)

INTEN (w) : Interrupt enable.

ETXBI = 1 → Enable TXBBUF interrupt.
ERCBI = 1 → Enable RCBBUF interrupt.
ESlvBMI = 1 → Enable slave address B match interrupt.
ETXAI = 1 → Enable TXABUF interrupt.
ERCAI = 1 → Enable RCABUF interrupt.
ESlvAMI = 1 → Enable slave address A match interrupt.
EDbufI = 1 → Enable DDC1 data buffer interrupt.
EMbufI = 1 → Enable Master IIC bus interrupt.

Mbuf (w) : Master IIC data shift register, after START and before STOP condition, write this register will

resume MTV212M32's transmission to the IIC bus.

Mbuf (r) : Master IIC data shift register, after START and before STOP condition, rea d th is register will

resume MTV212M32's receiving from the IIC bus.

RCABUF (r) : Slave IIC block A receive data buffer.
TXABUF (w) : Slave IIC block A transmit data buffer.
SLVAADR (w) :Slave IIC block A's enable and address.

ENslvA = 1 → Enable slave IIC block A.

= 0 → Disable slave IIC block A.

Revision 1.1 - 18 - 2000/07/04

MYSON

When the voltage level of power supply is below 4.0V(+/-0.2V) for a specific time, the LVR will generate a
chip reset signal. After the power supply is above 4.0V(+/-0.2V), LVR maintain in reset state f or 144

WDT(2:0). The timer

9. A/D con v ert er

three 6-bit A/D converters, S/W can select the current convert channel

WCLR

WDT2

WDT1

WDT0

Watchdog Timer control register.

MTV212M32

TECHNOLOGY

bit6-0 : Slave IIC address A to which the slave block should respond.

RCBBUF (r) : Slave IIC block B receive data buffer.
TXBBUF (w) : Slave IIC block B transmit data buffer.
SLVBADR (w) :Slave IIC block B's enable and address.

ENslvB = 1 → Enable slave IIC block B.

= 0 → Disable slave IIC block B.

bit6-0 : Slave IIC address B to which the slave block should respond.

8. Low Pow er Reset (LVR) & Watchdog Tim er

cycle to guarantee the chip exit reset condition with a stable X'tal oscillation.
The WatchDog Timer automatically generates a device reset when it is overflow. The interval of overflow is

0.25 sec x N, where N is a number from 1 to 8, and can be programmed via register
function is disabled after power on reset, user can activate this function by setting WEN, and clear the timer
by set WCLR.

(Rev 1.1)

Xtal

The MTV212M32 is equipped with
by setting the SADC1/SADC0 bit. The refresh rate for the ADC is OSC freq./12288. The ADC compare the
input pin voltage with internal VDD*N/64 voltage (where N = 0 - 63). The ADC output va lue is N when pin
voltage is greater than VDD*N/64 and smaller than VDD*(N+1)/64.

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

ADC
ADC

WDT

WDT (w) :

WEN = 1 → Enable WatchDog Timer.
WCLR = 1 → Clear WatchDog Timer.
WDT2: WDT0 = 0 → overflow interval = 8 x 0.25 sec.

ADC (w) : ADC control.

ENADC = 1 → Enable ADC.
SADC0 = 1 → Select ADC0 pin input.
SADC1 = 1 → Select ADC1 pin input.
SADC2 = 1 → Select ADC2 pin input.
SADC3 = 1 → no action.

10h (w) ENADC SADC3 SADC2 SADC1 SADC0

10h (r) ADC convert Result
18h (w) WEN

= 1 → overflow interval = 1 x 0.25 sec.
= 2 → overflow interval = 2 x 0.25 sec.
= 3 → overflow interval = 3 x 0.25 sec.
= 4 → overflow interval = 4 x 0.25 sec.
= 5 → overflow interval = 5 x 0.25 sec.
= 6 → overflow interval = 6 x 0.25 sec.
= 7 → overflow interval = 7 x 0.25 sec.

Revision 1.1 - 19 - 2000/07/04

MYSON

mode, or by IIC Host in serial mode

5V power supply for Program/Erase/Verify.

Whole Flash erase (Blank): 4mS

Whole 32K byte Flash programming within 3 Sec

request (by key or IIC), S/W can accept the request by the steps below:

Write ISP slave

When ISP is enable, the MTV212M32 will disable Watchdog reset and switch the Flash interface to ISP host

10.1 ISP Command Write

MTV212M32

TECHNOLOGY

ADC (r) : ADC convert result.

10. In System Programm i n g fu n c ti o n (ISP)

The Flash memory can be programmed by a specific WRITER in parallel
while the system is working. The ISP’s feature is outlined as below:

1. Single

2. Block Erase: 128 Byte at 4mS

3.

4. Byte programming Cycle time: 60uS

5. Read access time: 40ns

6. Only two pin IIC bus(shared with DDC2) is needed for ISP in user/factory mode

7. IIC Bus clock rate up to 140KHz

8.

9. CRC check provide 100% coverage for all single/double bit errors

After power on/Reset, The MTV212M32 is running the original ROM code. Once the S/W detect a ISP

1. Clear watchdog to prevent reset during ISP period

2. Disable all interrupt to prevent CPU wake-up

3.

4. Write 93h to ISP enable register (ISPEN) to enable ISP

5. Enter 8051 idle mode

’s IIC address to ISPSLV for communication

(Rev 1.1)

in 15-22.5uS. So S/W MUST enter idle mode immediately after enable ISP. In the 8051 idle mode, PWM
DACs and I/O pins keep running at its old status. There are 4 types of IIC bus transfer protocol in ISP mode.

Command Write

S-tttttt10k-cccccccck-AAAAAAAAk-P

Command Read

S-tttttt11k-ccccccccK-AAAAAAAAK-XaaaaaaaK-RRRRRRRRK-rrrrrrrrK-P

Data Write

S-tttttt00k-xaaaaaaak-ddddddddk- ... –ddddddddk-P

Data Read

S-tttttt00k-xaaaaaaak-(P)-S-tttttt01k-ddddddddK- ... –ddddddddK-P

where

S = start or re-start P = stop
K = ack by host (0 or 1) k = ack by slave
tttttt = ISP slave address cccccccc = command
x = don’t care X = not defined
AAAAAAAA = Flash_address[14:7] aaaaaaa = Flash_address[6:0]
RRRRRRRR = CRC_register[15:8] rrrrrrrr = CRC_register[7:0]
dddddddd = Flash_data

cccccccc = 10100xxx → Program
cccccccc = 00110xxx → Page Erase 128 bytes (Erase)
cccccccc = 01101xxx → Erase entire Flash (Blank)
cccccccc = 11010xxx → Clear CRC_register (Clr_CRC)
cccccccc = 01001xxx → Reset MTV212M32 (Reset_CPU)

The 2nd byte of “Command Write” can define the operating mode of MTV212M32 in its “Data write” stage,

Revision 1.1 - 20 - 2000/07/04

MYSON

byte reflects the current Flash

byte, the MTV212M32 will

Command Write
address will increase every time when ISP slave acknowledges the data b yte. The Blank/Erase command
need one data byte (content is

ack to the following data byte. In the meantime, the low address won

acked data byte. A Data Write may consist of 1,2 or more bytes.

s data byte

10.5 Cyclic Redundancy Check (CRC)

Command Write

MTV212M32

TECHNOLOGY

clear CRC register, or reset MTV212M32. The 3rd byte of Command Write defines the page address (A14-7)
of Flash memory. A Command Write may consist of 1,2 or 3 bytes.

10.2 ISP Command Read
The 2nd byte echoes the current command in ISP slave. The 3rd and 4
address. The 5th and 6th byte reports the CRC result. A Command Read may consist of 2,3,4,5 or 6 bytes.

10.3 ISP Data Write
The 2nd byte defines the Flash’s low address (A6-0). After receiving the 3
execute a Program/Erase/Blank command depends on the preceding “

slave won’t accept any command/data and returns non-ack to any IIC bus activity. The Program command
may have 1-128 data byte. The program cycle time is 60us. If the ISP slave can’t complete the program
cycle in time, it will return non­increase and the CRC won’t count the non-

Data Write (Blank/Erase)

S-tttttt00k-xaaaaaaak-ddddddddk-P ... S-ttttttxxk-

Data Write (Program)

S-tttttt00k-xaaaaaaak-ddddddddk-ddddddddk- ...

“don’t care”). The executing time is 4mS. During the 4mS period, the ISP

|-----Min. 4mS----|

|Min. 60uS|

th

rd

(Rev 1.1)

”. The Flash’s low

’t

10.4 ISP Data Read
The 1st and 2nd byte are the same as “Data write” to define the Flash’s low address. Between 2nd and 3rd byte,
the ISP host may issue Stop-Start or only Re-Start. From the 4th byte, the ISP slave send Flash’
to ISP Host. The low address auto increase every time when data byte transferred.

To shorten the verify time, the ISP slave provide a simple way to check if data error occurs duri ng the
program data transfer. After the ISP Host send a lot of data byte to ISP slave, Host can use Command Read
to check CRC register’s result instead of reading every byte in Flash. The CRC register counts every data
byte which ISP slave acknowledges during “Data Write” period. However, the low address byte and the data
byte of Erase/Blank are not counted. The Clear CRC command will write all “1” to the 16-bit CRC register.
For CRC generation, the 16-bit CRC register is seeded with all “1” pattern (by device reset or Clear CRC
command). The data byte shifted into the CRC register is Msb first. The real implementation is described as
follows:

CRCin = CRC[15]^DATAin;
CRC[15:0] = {CRC[14]^CRCin, CRC[13:2], CRC[1]^CRCin, CRC[0], CRCin};

Where ^ = XOR

example:

data_byte CRC_register_remainder

FFFFH
F6H FF36H
28H 34F2H
C3H 7031H

10.6 Reset Device
After the Flash been program completed and verified OK, the ISP Host can use “
Reset_CPU command to wake up MTV212M32.

” with

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

ISPSLV

Revision 1.1 - 21 - 2000/07/04

0bh (w) ISP Slave address

MYSON

Write 93h to enable ISP Mode

Writer Mode: RESET=1 & DA9=0 & DA8=1

WadrB

WadrA

SLVAADR

SLVBADR

Write 93h to enable ISP Mode

WCLR

WDT2

WDT1

WDT0

Pulse width of PWM DAC 0
Pulse width of PWM DAC 1
Pulse width of PWM DAC 2
Pulse width of PWM DAC 3
Pulse width of PWM DAC 4
Pulse width of PWM DAC 5
Pulse width of PWM DAC 6
Pulse width of PWM DAC 7
Pulse width of PWM DAC 8

Pulse width of PWM DAC 9
Pulse width of PWM DAC 10
Pulse width of PWM DAC 11
Pulse width of PWM DAC 12
Pulse width of PWM DAC 13

PWMF

MTV212M32

(Rev 1.1)

ISPEN

TECHNOLOGY

0ch (w)

Test Mode Conditi o n

In normal application, users should avoid the MTV212M32 entering its test mode or writer mode, outlined as
follow, Adding pull-up resistor to DA8 and DA9 pins is recommended.

Test Mode A: RESET=1 & DA9=1 & DA8=0 & STO=0
Test Mode B: RESET's falling edge & DA9=1 & DA8=0 & STO=1

Memor y Map of XFR

Reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

IICCTR
IICSTUS
IICSTUS

INTFLG
INTFLG

INTEN
MBUF

RCABUF

TXABUF

RCBBUF

TXBBUF

DBUF

ISPSLV

ISPEN

ADC
ADC

WDT

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8

DA9
DA10
DA11
DA12
DA13

PADMOD
PADMOD
PADMOD

OPTION
OPTION

00h (r/w) DDC2 MAckO P S

01h (r)
02h (r) MAckIn Hifreq Hbusy

03h (r) TXBI RCBI SlvBMI TXAI RCAI SlvAMI DbufI MbufI
03h (w) SlvBMI SlvAMI MbufI
04h (w) ETXBI ERCBI ESlvBMI ETXAI ERCAI ESlvAMI EDbufI EMbufI

05h (r/w) Master IIC receive/transmit data buffer

06h (r) Slave A IIC receive buffer
06h (w) Slave A IIC transmit buffer
07h (w) ENSlvA Slave A IIC address

08h (r) Slave B IIC receive buffer
08h (w) Slave B IIC transmit buffer
09h (w) ENSlvB Slave B IIC address

0Ah (w) DDC1 transmit data buffer

0bh (w) ISP Slave address
0ch (w)
10h (w) ENADC SADC3 SADC2 SADC1 SADC0

10h (r) ADC convert Result
18h (w) WEN

20h (r/w)
21h (r/w)
22h (r/w)
23h (r/w)
24h (r/w)
25h (r/w)
26h (r/w)
27h (r/w)
28h (r/w)

29h (r/w)
2Ah (r/w)
2Bh (r/w)
2Ch (r/w)
2Dh (r/w)

30h (w) DA13E DA12E DA11E DA10E AD3E AD2E AD1E AD0E
31h (w) P56E P55E P54E P53E P52E P51E P50E
32h (w) HIICE IIICE HLFVE HLFHE HCLPE P42E P41E P40E
33h (w)
34h (w) SlvAbs1 SlvAbs0

DIV253 FclkE IICpass ENSCL Msel MIICF1 MIICF0

SlvRWB SAckIn SLVS SlvAlsb1 SlvAlsb0

Revision 1.1 - 22 - 2000/07/04

MYSON

EVsync

ELECTRICAL PARA METERS

1. Absolu t e Maximum Rating s

Maximum Supply Voltage

2. Allowable Operating Condit io ns

MTV212M32

XBANK

PORT4

PORT5
PADMOD
PADMOD
PADMOD

HVSTUS

HCNTH

HCNTL

VCNTH

VCNTL

HVCTR0
HVCTR2
HVCTR3

INTFLG

INTEN

TECHNOLOGY

35h (r/w) Xbnk2 Xbnk1 Xbnk0

38h (w) P42 P41 P40

39h (r/w) P56 P55 P54 P53 P52 P51 P50

3Ah (w) COP17 COP16 COP15 COP14 COP13 COP12 COP11 COP10
3Bh (w) COP27 COP26 COP25 COP24 COP23 COP22 COP21 COP20
3Ch (w) COP56 COP55 COP54 COP53

40h (r) CVpre Hpol Vpol Hpre Vpre Hoff Voff
41h (r) Hovf HF13 HF12 HF11 HF10 HF9 HF8
42h (r) HF7 HF6 HF5 HF4 HF3 HF2 HF1 HF0
43h (r) Vovf VF11 VF10 VF9 VF8

44h (r) VF7 VF6 VF5 VF4 VF3 VF2 VF1 VF0
40h (w) C1 C0 NoHins HBpl VBpl
42h (w) Selft STF1 STF0 Rt1 Rt0 STE
43h (w) CLPEG CLPPO CLPW2 CLPW1 CLPW0

48h (r/w) HPRchg VPRchg HPLchg VPLchg HFchg VFchg Vsync

49h (w) EHPR EVPR EHPL EVPL EHF EVF

(Rev 1.1)

at: Ta= 0 to 70 oC, VSS=0V

Name Symbol Range Unit

VDD -0.3 to +6.0 V
Maximum Input Voltage Vin -0.3 to VDD+0.3 V
Maximum Output Voltage Vout -0.3 to VDD+0.3 V
Maximum Operating Temperature Topg 0 to +70 o

Maximum Storage Temperature Tstg -25 to +125 o

at: Ta= 0 to 70 oC, VSS=0V

Name Symbol Min. Max. Unit

Supply Voltage VDD 4.5 5.5 V
Input "H" Voltage Vih1 0.4 x VDD VDD +0.3 V
Input "L" Voltage Vil1 -0.3 0.2 x VDD V
Operating Freq. Fopg - 15 MHz

3. DC Characteri s t i c s

C
C

at: Ta=0 to 70 oC, VDD=5.0V, VSS=0V

Name Symbol Condition Min. Typ. Max. Unit

Output "H" Voltage, open drain pin Voh1 Ioh=0uA 4 V
Output "H" Voltage, 8051 I/O port pin Voh2 Ioh=-50uA 4 V
Output "H" Voltage, CMOS output Voh3 Ioh=-4mA 4 V
Output "L" Voltage Vol Iol=5mA 0.45 V

Revision 1.1 - 23 - 2000/07/04

MYSON

Power Supply Current

4. AC Characterist ic s

PWM DAC Frequency

tVIPW

tVCPW

MTV212M32

TECHNOLOGY

(Rev 1.1)

Active 18 24 mA

Idd

Idle 1.3 4.0 mA

Power-Down 50 80 uA
RST Pull-Down Resistor Rrst VDD=5V 150 250 Kohm
Pin Capacitance Cio 15 pF

at: Ta=0 to 70 oC, VDD=5.0V, VSS=0V

Name Symbol Condition Min. Typ. Max. Unit

Crystal Frequency fXtal 12 MHz

fDA fXtal=12MHz 46.875 94.86 KHz
HS input pulse Width tHIPW fXtal=12MHz 0.3 8 uS
VS input pulse Width

fXtal=12MHz 3 uS
HSYNC to Hblank output jitter tHHBJ 5 nS
H+V to Vblank output delay tVVBD fXtal=12MHz 8 uS
VS pulse width in H+V signal

FXtal=12MHz 20 uS
SDA to SCL setup time tDCSU 200 ns
SDA to SCL hold time tDCH 100 ns
SCL high time tSCLH 500 ns
SCL low time tSCLL 500 ns
START condition setup time tSU:STA 500 ns
START condition hold time tHD:STA 500 ns
STOP condition setup time tSU:STO 500 ns
STOP condition hold time tHD:STO 500 ns

t

SU:STA

t

HD:STA

t

SCKH

t

SCKL

t

DCSU

t

DCH

Data interface timing (I2C)

t

SU:STO

t

HD:STO

Revision 1.1 - 24 - 2000/07/04

MYSON

PACKAGE DIMENSION

MTV212M32

TECHNOLOGY

1. 40-pin PDIP 600 mil

1.981mm
+/-0.254

3.81mm
+/-0.127

3.302mm
+/-0.254

52.197mm +/-0.127

2.540mm0.457mm +/-0.1271.270mm +/-0.254

1.778mm
+/-0.127

0.254mm

(min.)

(Rev 1.1)

15.494mm +/-0.254

13.868mm +/-0.102

5o~7

16.256mm +/-0.508

6o +/-3

0.254mm
+/-0.102

0

o

2. 42 pin SDIP Unit: mm

Symbol

Dimension in mm

Min Nom Max

A 3.937 4.064 4.2
A1 1.78 1.842 1.88
B1 0.914 1.270 1.118

D 36.78 36.83 36.88
E1 13.945 13.970 13.995

F 15.19 15.240 15.29
eB 15.24 16.510 17.78

0° 7.5° 15°

15.494mm +/-

0.254

13.868mm +/-

0.102

5o~7

16.256mm +/-

0.508

0

6o +/-

3

0.254m
m

+/-0.102

o

Revision 1.1 - 25 - 2000/07/04

MYSON

MTV212M32

3. 44 pin PLCC Unit :

0

0.045*45

0.050 TYP.

0.653 +/-0.003

0.690 +/-0.005

TECHNOLOGY

PIN #1 HOLE

0.690 +/-0.005

0.653 +/-0.003

0.026~0.032 TYP.

0.180 MAX.

0.013~0.021 TYP.

70TYP.

0.070 0.070

(Rev 1.1)

0.020 MIN.

0.610 +/-0.02

0.500

0.010

Ordering Inform ation

Standard configurations:

Prefix Part Typ e Package Type ROM Size (K)

N: PDIP

MTV 212M

S: SDIP

V: PLCC

Part Numbers:

Prefix

MTV 212M N 32
MTV 212M S 32
MTV 212M V 32

Part Type Package Type ROM Size (K)

32

Revision 1.1 - 26 - 2000/07/04