Datasheet MTD2955V Datasheet (Motorola)



SEMICONDUCTOR TECHNICAL DATA

  

 



   

Order this document

by MTD2955V/D



   

P–Channel Enhancement–Mode Silicon Gate

TMOS V is a new technology designed to achieve an on–resis­tance area product about one–half that of standard MOSFET s. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

New Features of TMOS V

• On–resistance Area Product about One–half that of Standard

MOSFETs with New Low Voltage, Low R

DS(on)

Technology

• Faster Switching than E–FET Predecessors

Features Common to TMOS V and TMOS E–FETS

• Avalanche Energy Specified

• I

DSS

and V

Specified at Elevated Temperature

DS(on)

• Static Parameters are the Same for both TMOS V and TMOS E–FET

• Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel,

Add T4 Suffix to Part Number

G

TMOS POWER FET

12 AMPERES

60 VOLTS

R

TM

D

S

CASE 369A–13, Style 2

DPAK Surface Mount

DS(on)

= 0.230 OHM

MAXIMUM RATINGS

Drain–to–Source Voltage V
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
Gate–to–Source Voltage — Continuous

Gate–to–Source Voltage — Non–repetitive (tp ≤ 10 ms)

Drain Current — Continuous

Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)

Total Power Dissipation

Derate above 25°C

Total Power Dissipation @ 25°C
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25 Ω)

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves —representing boundaries on device characteristics —are given to facilitate “worst case” design.

E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

(TC = 25°C unless otherwise noted)

Rating

(1)

(1)

Symbol Value Unit

60 Vdc
60 Vdc

± 15
± 25

12

8.0
42

60

0.4

2.1

–55 to 175 °C

216 mJ

2.5

100

71.4
260 °C

Vdc
Vpk

Adc

Apk

Watts

W/°C

Watts

°C/W

V

V

I

E

R
R
R

DSS

DGR

GS

GSM

I

D

I

D

DM
P

D

stg

AS

θJC
θJA
θJA

L

REV 3

Motorola TMOS Power MOSFET Transistor Device Data

 Motorola, Inc. 1997

1

MTD2955V

)

f = 1.0 MHz)

V

G

)

(

DS

,

D

,

(

S

,

GS

,

ELECTRICAL CHARACTERISTICS

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3)

(VGS = 0 Vdc, ID = 0.25 mAdc)
T emperature Coef ficient (Positive)

Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)

Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) I

ON CHARACTERISTICS (1)

Gate Threshold Voltage (Cpk ≥ 2.0) (3)

(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)

Static Drain–to–Source On–Resistance (Cpk ≥ 1.5) (3)

(VGS = 10 Vdc, ID = 6.0 Adc)

Drain–to–Source On–Voltage

(VGS = 10 Vdc, ID = 12 Adc)
(VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150°C)

Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance

Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (1)

Reverse Recovery Time

Reverse Recovery Stored Charge Q

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.

Cpk =

(T

= 25°C unless otherwise noted)

J

Characteristic

(VDS = 25 Vdc, VGS = 0 Vdc,

(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C)

Max limit – Typ

3 x SIGMA

f = 1.0 MHz

(VDD = 30 Vdc, ID = 12 Adc,

(VDS = 48 Vdc, ID = 12 Adc,

(IS = 12 Adc, VGS = 0 Vdc)

(IS = 12 Adc, VGS = 0 Vdc,

= 10 Vdc,

GS

RG = 9.1 Ω)

VGS = 10 Vdc)

dIS/dt = 100 A/µs)

Symbol Min Typ Max Unit

V

(BR)DSS

I

DSS

GSS

V

GS(th)

R

DS(on)

V

DS(on)

FS

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

Q

T

Q

1

Q

2

Q

3

V

SD

t

rr

t

a

t

b

RR

L

D

L

S

60
—

—
—

— — 100 nAdc

2.0
—

— 0.185 0.230

—
—

3.0 5.0 — mhos

— 550 770 pF
— 200 280
— 50 100

— 15 30 ns
— 50 100
— 24 50
— 39 80
— 19 30 nC
— 4.0 —
— 9.0 —
— 7.0 —

—
—

— 115 —
— 90 —
— 25 —
— 0.53 — µC

—
—

— 7.5 —

—
58

—
—

2.8

5.0

—
—

1.8

1.5

3.5

4.5

—
—

10

100

4.0
—

2.9

2.5

3.0
—

—
—

mV/°C

mV/°C

Vdc

µAdc

Vdc

Ohm

Vdc

Vdc

ns

nH

nH

2

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

MTD2955V

25

TJ = 25

°C

20

15

10

, DRAIN CURRENT (AMPS)

D

I

5

0

012345

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

VGS = 10 V

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

0.40
VGS = 10 V

0.35

0.30

0.25

0.20

TJ = 100

25

°C

9 V

678910

°C

8 V

7 V

6 V

5 V

24

VDS ≥ 10 V

21
18
15
12

9

, DRAIN CURRENT (AMPS)

6

D

I

3
0

3579

246 810

VGS, GATE–T O–SOURCE VOLT AGE (VOLTS)

0.250
TJ = 25

0.225

0.200

0.175

0.150

°C

TJ = – 55

25

°C

VGS = 10 V

15 V

°C

100

°C

0.15

0.10

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0.05

DS(on)

0

R

03 6 15 24

ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

–55

°C

12 21 3 12 15

189

Figure 3. On–Resistance versus Drain Current

and T emperature

2.0
VGS = 10 V

1.8
ID = 6 A

1.6

1.4

1.2

1.0

0.8

(NORMALIZED)

0.6

, DRAIN–TO–SOURCE RESIST ANCE

0.4

0.2

DS(on)

R

0

–50

– 25 0 25 50 75 100 125 150

°

TJ, JUNCTION TEMPERATURE (

C) VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

175

0.125

0.100

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0.075

DS(on)

0.050

R

0 6 21 24

918

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

1000

VGS = 0 V

TJ = 125

°C

100

100

, LEAKAGE (nA)

DSS

I

10

020 5060

10 30 40

°C

Figure 5. On–Resistance Variation with

Temperature

POWER MOSFET SWITCHING

Motorola TMOS Power MOSFET Transistor Device Data

Figure 6. Drain–T o–Source Leakage

Current versus Voltage

3

MTD2955V

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
the drive circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V
be approximated by the following:

tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V
where
VGG = the gate drive voltage, which varies from zero to V
RG = the gate drive resistance
and Q2 and V
During the turn–on and turn–off delay times, gate current is

not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

= RG C

d(on)

t

= RG C

d(off)

) can be made from a rudimentary analysis of

G(A V)

. Therefore, rise and fall times may

SGP

)

GSP

GSP

are read from the gate charge curve.

GSP

In [VGG/(VGG – V

iss

In (VGG/V

iss

GSP

)

GSP

)]

GG

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off–state condition when cal­culating t
on–state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently , is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

1800
1600

1400
1200
1000

C, CAPACITANCE (pF)

800
600
400
200

VDS = 0 V

C

iss

C

rss

0

10 0 10 15 25

55

GATE–T O–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

VGS = 0 V

C

iss

C

oss

C

rss

V

GS

V

DS

Figure 7. Capacitance Variation

TJ = 25

20

°C

4

Motorola TMOS Power MOSFET Transistor Device Data

, GATE–T O–SOURCE VOLT AGE (VOLTS)

GS

V

10

9
8

Q1 Q2

7
6
5
4
3
2
1
0

Q3

0

2468 20

QT, TOTAL CHARGE (nC)

QT

V

GS

V

DS

1610 12

I

= 12 A

D

TJ = 25

1814

MTD2955V

1000

V

30

DS

, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

27
24
21
18
15
12
9

°

C

6
3

0

VDD = 30 V
ID = 12 A
VGS = 10 V
TJ = 25

°

C

100

t

r

t

t, TIME (ns)

10

1

1 10 100

f

t

d(off)

t

d(on)

RG, GATE RESISTANCE (OHMS)

Figure 8. Gate–T o–Source and Drain–To–Source

V oltage versus Total Charge

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

12

VGS = 0 V

11

TJ = 25

°

10

9
8
7
6
5
4
3

, SOURCE CURRENT (AMPS)

S

I

1
0

0.5 0.7 1.1 1.9

Figure 10. Diode Forward V oltage versus Current

C

0.9 1.3 1.521.7

VSD, SOURCE–TO–DRAIN VOL TAGE (VOLTS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for­ward biased. Curves are based upon maximum peak junc­tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”

Switching between the off–state and the on–state may tra­verse any load line provided neither rated peak current (IDM)
nor rated voltage (V
(tr,tf) do not exceed 10 µs. In addition the total power aver­aged over a complete switching cycle must not exceed
(T

J(MAX)

– TC)/(R

A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

) is exceeded and the transition time

DSS

).

θJC

able operation, the stored energy from circuit inductance dis­sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con­stant. The energy rating decreases non–linearly with an in­crease of peak current in avalanche and peak junction
temperature.

Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur­rent (ID), in accordance with industry custom. The energy rat­ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur­rents below rated continuous ID can safely be assumed to
equal the values indicated.

5

MTD2955V

SAFE OPERATING AREA

100

VGS = 15 V
SINGLE PULSE
TC = 25

°

C

10

100 µs

1 ms

1.0

, DRAIN CURRENT (AMPS)

D

I

0.1

0.1 10 100
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

R

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

1.0 150

10 ms

dc

LIMIT

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

1.0
D = 0.5

0.2

0.1

0.05

0.1

0.02

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

0.01

1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01

0.01

SINGLE PULSE

t, TIME (s)

225
200
175
150
125
100

75

AVALANCHE ENERGY (mJ)

50

, SINGLE PULSE DRAIN–TO–SOURCE

25

AS

E

0

25 50 75 100 125

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy versus

Starting Junction T emperature

P

(pk)

t

1

t

2

DUTY CYCLE, D = t1/t

2

R

(t) = r(t) R

θ

JC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T

J(pk)

– TC = P

θ

(pk)

JC

1

ID = 12 A

175

R

(t)

θ

JC

Figure 13. Thermal Response

di/dt

I

S

t

rr

t

t

a

b

TIME

t

p

0.25 I

S

I

S

Figure 14. Diode Reverse Recovery Waveform

6

Motorola TMOS Power MOSFET Transistor Device Data

INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface

MTD2955V

between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.

0.165

4.191

0.190

4.826

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by T
junction temperature of the die, R
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data sheet,
PD can be calculated as follows:

T

PD =

J(max)

R

θJA

The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a DPAK
device, PD is calculated as follows.

175°C – 25°C

PD =

71.4°C/W

The 71.4°C/W for the DPAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.1 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power

, the maximum rated

J(max)

, the thermal resistance

θJA

– T

A

= 2.1 Watts

0.118

0.100

3.0

2.54

0.063

1.6

0.243

6.172

inches

mm

dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
R

versus drain pad area is shown in Figure 15.

θJA

100

80

°

60

TO AMBIENT ( C/W)

40

, THERMAL RESISTANCE, JUNCTION

JA

θ

R

20

1.75 Watts

3.0 Watts

A, AREA (SQUARE INCHES)

Board Material = 0.0625
G–10/FR–4, 2 oz Copper

5.0 Watts

″

TA = 25°C

Figure 15. Thermal Resistance versus Drain Pad

Area for the DPAK Package (Typical)

Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.

1086420

Motorola TMOS Power MOSFET Transistor Device Data

7

MTD2955V

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC–59,
SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223,
SO–8, SO–14, SO–16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
registration. This is not the case with the DPAK and D2PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or “tombstoning” may occur due
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
Figure 16 shows a typical stencil for the DPAK and D2PAK
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.

• Always preheat the device.

• The delta temperature between the preheat and soldering

should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

SOLDER P ASTE
OPENINGS

STENCIL

Figure 16. Typical Stencil for DPAK and

D2P AK Packages

• When shifting from preheating to soldering, the maximum

temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should be

allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied during

cooling.

* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.

* Due to shadowing and the inability to set the wave height to
incorporate other surface mount components, the D2PAK is
not recommended for wave soldering.

8

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed. T aken together , these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
17 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
type of solder used, and the type of board or substrate material
being used. This profile shows temperature versus time. The

MTD2955V

line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in­frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177–189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.

200

°

150°C

100

°

50

°

STEP 1

PREHEA T

ZONE 1

“RAMP”

C

DESIRED CURVE FOR HIGH

C

C

TIME (3 TO 7 MINUTES TOTAL)

STEP 2

VENT

“SOAK”

MASS ASSEMBLIES

150°C

100°C

Figure 17. Typical Solder Heating Profile

STEP 3

HEATING

ZONES 2 & 5

“RAMP”

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

°

C

160

140°C

T

MAX

STEP 6

VENT

205

SOLDER JOINT

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

170°C

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

STEP 7

COOLING

°

TO 219°C

PEAK AT

Motorola TMOS Power MOSFET Transistor Device Data

9

MTD2955V

V

S

F

B

R

4

123

G

A

K

L

D

2 PL

C

J

H

0.13 (0.005) T

M

PACKAGE DIMENSIONS

SEATING

–T–

PLANE

E

U

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

CASE 369A–13

ISSUE Y

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.235 0.250 5.97 6.35
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38

Z

D 0.027 0.035 0.69 0.88
E 0.033 0.040 0.84 1.01
F 0.037 0.047 0.94 1.19

G 0.180 BSC 4.58 BSC

H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
L 0.090 BSC 2.29 BSC
R 0.175 0.215 4.45 5.46
S 0.020 0.050 0.51 1.27
U 0.020 ––– 0.51 –––
V 0.030 0.050 0.77 1.27
Z 0.138 ––– 3.51 –––

MILLIMETERSINCHES

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,

P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 4–32–1 Nishi–Gotanda, Shagawa–ku, Tokyo, Japan. 03–5487–8488

Customer Focus Center: 1–800–521–6274
Mfax: [e-mail] – TOUCHTONE 1–602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

Moto rola Fax Back System – US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
HOME PAGE: http://motorola.com/sps/

10

– http://sps.motorola.com/mfax/

◊

Motorola TMOS Power MOSFET Transistor Device Data

Mfax is a trademark of Motorola, Inc.

MTD2955V/D