Datasheet MT8870DS-1, MT8870DT, MT8870DT-1, MT8870DN-1, MT8870DC Datasheet (MITEL)



ISO2-CMOS

MT8870D/MT8870D-1

Integrated DTMF Receiver

Features

• Complet e DTMF R eceiv er

• Low power co nsu mptio n

• Internal gai n sett ing a mplif ier

• Adjustable guard time

• Central office qua lity

• Power-down m ode

• Inhibit m o de

• Backward compatible with
MT8870C/M T88 70C -1

Applications

• Receiver system for British Telecom (BT) or
CEPT Spec (MT8870 D-1)

• Paging systems

• Repeater systems/mobile radio

• Credit card systems

• Remote con trol

• Personal com put ers

• Telephone ans werin g mach in e

ISSUE 3 May1995

Ordering Information

MT8870DE/DE-1 18 Pin Plastic DIP
MT8870DC/DC-1 18 Pin Ceramic DIP
MT8870DS/DS-1 18 Pin SOIC
MT8870DN/D N-1 20 Pin SSOP
MT8870DT /DT-1 20 Pin TSS OP

-40 °C to +85 °C

Descript io n

The MT8870D/MT8870D-1 is a complete DTMF
receiver integrating both the bandsplit filter and
digital decoder functions. The filter section uses
switched capacitor techniques for high and low
group filters; the decoder uses digital counting
techniques to detect and decode all 16 DTMF tone­pairs into a 4-bit code. External component count is
minimized by on chip provision of a differential input
amplifier, clock oscillator and latched three-state bus
interface.

PWDN

IN +

IN -

GS

VDD VSS VRef INH

Bias

Circuit

Chip

Chip

Power

Bias

Dial
Tone
Filter

OSC1 OSC2 St/GT ESt STD TOE

High Group

Filter

Low Group

Filter

to all
Chip
Clocks

VRef
Buffer

Zero Crossing
Detectors

Digital
Detection
Algorithm

St
GT

Steering
Logic

Code
Converter
and Latch

Q1

Q2

Q3

Q4

Figure 1 - Functional Block Diagram

4-11

MT8870D/MT8870D-1 ISO

2

-CMOS

1

IN+

2

IN-

3

GS

INH

4
5

6
7
8
9

VRef

PWDN

OSC1
OSC2

VSS

18 PIN CERDIP/PLASTIC DIP/S OIC

18
17
16
15
14
13
12
11
10

VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE

IN+

IN-

GS

VRef

INH

PWDN

NC
OSC1
OSC2

VSS

1
2

3
4
5

6
7
8
9

10

20 PIN SSOP/TSSOP

20
19
18
17
16
15
14
13
12
11

VDD
St/GT
ESt
StD
NC

Q4
Q3
Q2
Q1
TOE

Figure 2 - Pin Connections

Pin Description

Pin #

18 20

11 IN+ Non-Inverting Op-Amp (Input).
2 2 IN- Inverting Op-Amp (Input).
33 GS Gain Select. Gives access to output of front end differential amplifier for connection of

44 V

Name Description

feedback resistor.
Reference Voltage (Output). Nominall y VDD/2 is used to bias inputs at mid-rail (see Fig. 6

Ref

and Fig. 10).

55 INH Inhibit (Input). Logi c high inhibi ts the det ection of tones repre senti ng chara cters A, B, C

and D. This pin input is internally pulled down.

66PWDNPower Down (Input). A ctive high. Powers down the device and inhi bits the oscillat or. This

pin input is internally pulled do wn.
78 OSC1Clock (Input).
89 OSC2Clock (Output). A 3.579545 MHz crystal connect ed between pins OS C1 and OS C2

completes the internal oscillator ci r cuit.
910 V

Ground (Inpu t). 0V typical.

SS

10 11 TOE Th ree S tate Outpu t Ena ble (Inp ut). Log ic high enables th e outpu ts Q1-Q4. This pin is

pulled up internally.

11-1412-15Q1-Q4 Three State Data (Outpu t). When enabled by TOE, provide the code corresponding to the

last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high

impedance.

15 17 StD Delayed Steering (Output).Presents a logic high when a received tone-pair has been

registered and the output latch updated; returns to logic low when t he voltage on St/GT falls

below V

TSt

.

16 18 ESt Early Steering (Output). Prese nts a logic high once the digit al algorit hm has detect ed a

valid tone pair (signal condition ). Any mome ntary loss of signal conditio n will cause ESt to

return to a logic low.

17 19 St/GT Steering Input/Guard time (Output) Bidirectional. A voltage greater than V

detected at

TSt

St causes the device to register the detected tone pair and update the output latch . A

voltage less than V

frees the device to accept a new tone pair. The GT output acts to

TSt

reset the external steering time-constant ; its state is a function of ESt and the voltage on St.

18 20 V

7,

16

4-12

Positive power supply (Input). +5V typical .

DD

NC No Connection.

ISO

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AAAAAAAAA
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Functional Descripti on

The MT8870D/MT8870D-1 monolithic DTMF
receiver offers small size, low power consumption
and high performance. Its architecture consists of a
bandsplit filter section, which separates the high and
low group tones, followed by a digital counting
section which verifies the frequency and duration of
the received tones before passing the corresponding
code to the output bus.

2

-CMOS MT8870D/MT8870D-1

V

DD

V

DD

St/GT

C

v

c

ESt

R

StD

Filter Section

Separation of the low-group and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies. The filter section also
incorporates notches at 350 and 440 Hz for
exceptional dial tone rejection (see Figure 3). Each
filter output is followed by a single order switched
capacitor filter section which smooths the signals
prior to limiting. Limiting is performed by high-gain
comparators which are provided with hysteresis to
prevent detection of unwanted low-level signals. The
outputs of the comparators provide full rail logic
swings at the frequencies of the incoming DTMF
signals.

Decoder Section

Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by ex traneous signals su ch as voice whi le

MT8870D/

MT8870D-1

t

=(RC)In(VDD/V

GTA

t

=(RC)In[VDD/(VDD-V

GTP

TSt

)

)]

TSt

Figure 4 - B asic Steer ing Circ uit

providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an in ac tive s ta te ( see “S te er in g Cir cu it”) .

Steering Circuit

Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt caus es v

(see Figure 4) to

c

rise as the capacitor discharges. Provided signal

0

10

AAA

AAAA

AAAA

AAAA

PRECISE
DIAL TONES

X=350 Hz
Y=440 Hz

DTMF TONES

20

ATTENUATION

(dB)

30

40

A=697 Hz
B=770 Hz
C=852 Hz
D=941 Hz
E=1209 Hz
F=1336 Hz
G=1477 H z
H=1633 H z

50

1kHz

XY ABCD

EF G H

FREQUENCY (Hz)

Figure 3 - Filter Response

4-13

MT8870D/MT8870D-1 ISO

2

-CMOS

condition is maintained (ESt remains high) for the
validation period (t
(V

) of the steering logic to register the tone pair,

TSt

), vc reaches the threshold

GTP

latching its corresponding 4-bit code (see Table 1)
into the output latch. At this point the GT output is
activated and drives v

to VDD. GT continues to drive

c

high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the
delayed steering output flag (StD) goes high,
signalling that a received tone pair has been
registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three
state control input (TOE) to a logic high. The
steering circuit works in reverse to validate the
interdigit pause between signals. Thus, as well as
rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions (dropout)
too short to be considered a valid pause. This facility,
together with the capability of selecting the steering
time constants externally, allows the designer to
tailor performance to meet a wide variety of system
requirements.

Guard Time Adjustment

In many situations not requiring selection of tone
duration and interdigital pause, the simple steering
circuit shown in Figure 4 is applicable. Component
values are chosen according to the formula:

t

REC=tDP+tGTP

tID=tDA+t

GTA

The valu e of tDP is a device parameter (see Figure

11) and t

is the minimum signal duration to be

REC

recognized by the receiver. A value for C of 0.1 µF is

t

V

DD

St/GT

ESt

V

DD

St/GT

=(RPC1)In[VDD/(VDD-V

GTP

=(R1C1)In(VDD/V

t

2

a) decreasing t

t

GTP

GTA

R

=(R1R2)/(R1+R2)

P

; (t

GTP

=(R1C1)In[VDD/(VDD-V

=(RPC1)In(VDD/V

t

GTA

=(R1R2)/(R1+R2)

R

P

C

1

R

R

1

C

1

)]

TSt

)

TSt

GTP<tGTA

)]

TSt

)

TSt

)

Digit TOE INH ESt Q
ANYLXHZZZZ

1HXH0001
2HXH0010
3HXH0011
4HXH0100
5HXH0101
6HXH0110
7HXH0111
8HXH1000
9HXH1001
0HXH1010

*HXH1011

#HXH1100
AHLH1101
BHLH1110
CHLH1111
DHLH0000
AHHL
BHHL
CHHL
DHHL

undetected, the output code
will remain the same as the
previous detected code

Q

Q

4

3

Q

2

1

Table 1. Functional Decode Table

L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE
X = DON‘T CARE

recommended for most applications, leaving R to be
selected by the designer.

Different steering arrangements may be used to
select independently the guard times for tone
present (t

) and tone absent (t

GTP

). This may be

GTA

necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters
such as talk off and noise immunity. Increasing t

REC

improves talk-off performance since it reduces the
probability that tones simulated by speech will
maintain signal condition long enough to be
registered. Alternatively, a relatively short t
a long t

would be appropriate for extremely noisy

DO

REC

with

environments where fast acquisition time and
immunity to tone drop-outs are required. Design
information for guard time adjustment is shown in
Figure 5.

4-14

R

R

ESt

2

1

b) decreasing t

Figure 5 - Guard Time Adjustment

GTA

; (t

GTP>tGTA

)

Power-down and Inhibit Mode

2

ISO

-CMOS MT8870D/MT8870D-1

A logic high applied to pin 6 (PWDN) will power down
the device to minimize the power consumption in a
standby mode. It stops the oscillator and the
functions of the filters.

Inhibit mode is enabled by a logic high input to the
pin 5 (INH). It inhibits the detection of tones
representing characters A, B, C, and D. The output
code will remain the same as the previous detected
code (see Table 1).

Differential Input Configuration

The input arrangement of the MT8870D/MT8870D-1
provides a differential-input operational amplifier as
well as a bias source (V

) which is u se d to b ias th e

Ref

inputs at mid-rail. Provision is made for connection of
a feedback resistor to the op-amp output (GS) for
adjustment of gain. In a single-ended configuration,
the input pins are connected as shown in Figure 10
with the op-amp connected for unity gain and V

Ref

biasing the input at 1/2VDD. Figure 6 shows the
differential configuration, which permits the
adjustment of gain with the feedback resistor R

.

5

C1R

C

Differential Input Amplifier

C1=C2=10 nF
R
R

1

R

2

4

R

3

1=R4=R5
2

R

VOLTAGE GAIN (Av diff)=

INPUT IMPEDANCE

(Z

=100 kΩ

=60kΩ, R3=37.5 kΩ

R

2R5

=

3

R2+R

5

) = 2

INDIFF

IN+

IN-

R

2

R

+

1

MT8870D/
MT8870D-1

+

-

R

2

1

ωc

GS

5

V

Ref

All resistors are ±1% tolerance.
All capacitors are ±5% tolerance.

R

5

R

1

2

Crystal Oscillator

The internal clock circuit is completed with the
addition of an external 3.579545 MHz crystal and is
normally connected as shown in Figure 10 (Single­Ended Input Configuration). However, it is possible
to configure several MT8870D/MT8870D-1 devices
employing only a single oscillator crystal. The
oscillator output of the first device in the chain is
coupled through a 30 pF capacitor to the oscillator
input (OSC1) of the next device. Subsequent devices
are connected in a similar fashion. Refer to Figure 7
for details. The problems associated with
unbalanced loading are not a concern with the
arrangement shown, i.e., precision balancing
capacitors are not required.

Figure 6 - Differential Input Configuration

To OSC1 of next

MT8870D/MT8870D-1

C=30 pF
X-tal=3.579545 MHz

OSC1

OSC2

C

X-tal

OSC2

OSC1

C

Figure 7 - Oscillator Connection

Parameter Unit Resonator

R1 Ohms 10.752
L1 mH .432
C1 pF 4.984
C0 pF 37.915

Qm - 896.37

∆f % ±0.2%

Table 2. Recommended Resonator Specifications

Note: Qm= qu al ity f act o r of R L C m od el , i .e. , 1 /2ΠƒR1C1.

4-15

MT8870D/MT8870D-1 ISO

2

Applications

RECEIVER SYSTEM FOR B RIT IS H TEL ECO M
SPEC POR 1151

-CMOS

t

=(RPC1)In[VDD/(VDD-V

GTP

TSt

)]

The circuit shown in Fig. 9 illustrates the use of
MT8870D-1 device in a typical receiver system. BT
Spec defines the input signals less than -34 dBm as
the non-operate level. This condition can be
attained by choosing a suitable values of R

and R

1

to provide 3 dB attenuation, such that -34 dBm input
signal will correspond to -37 dBm at the gain setting
pin GS of MT8870D-1. As shown in the diagram, the
component values of R

and C2 are the guard time

3

requirements when the total component tolerance is
6%. For better performance, it is recommended to
use the non-symmetric guard time circuit in Fig. 8.

=(R1C1)In(VDD/V

t

GTA

R

V

DD

2

St/GT

R

1

ESt

C

1

R

2

=(R1R2)/(R1+R2)

P

Notes:
R1=368K Ω ± 1%

=2.2M Ω ± 1%

R

2

=100nF ± 5%

C

1

TSt

)

Figure 8 - Non-Symmetric Guard Time Circuit

DTMF
Input

V

DD

C

1

C

R

1

R

2

X

1

MT8870D-1

IN+
IN­GS
V

Ref

INH
PWDN
OSC 1
OSC 2
V

SS

V

DD

St/GT

ESt

StD

Q4
Q3
Q2
Q1

TOE

2

R

3

NOTES:
R

= 102KΩ ± 1%

1

R

= 71.5KΩ ± 1%

2

R

= 390KΩ ±1 %

3

C

= 100 nF ± 5%

1,C2

X

= 3.579545 MHz ± 0.1%

1

V

= 5.0V ± 5%

DD

Figure 9 - Single-Ended Input Configuration for BT or CEPT Spec

4-16

2

ISO

-CMOS MT8870D/MT8870D-1

Absolute Maximum Ratings

†

Parameter Symbol Min Max Units

1 DC Power Supply Voltage V
2 Voltage on any pin V
3 Current at any pin (other than supply) I
4 Storage temperature T
5 Package power dissipation P

† Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Derate ab o ve 75 °C at 16 m W / ° C . All leads sold ered to bo a r d.

Recommended Operating Conditions - Voltages are with respect to ground (V

Parameter Sym Min Typ

1 DC Power Supply Voltage V
2 Operating Temperature T
3 Crystal/Clock Frequency fc

DD

4.75 5.0 5.25 V

O

-40 +85 °C

3.579545

DD

I

I

STG

D

‡

Max Units Test Conditions

VSS-0.3 VDD+0.3 V

-65 +150 °C

) unless otherwise stated .

SS

MHz

4 Crystal/Clock Freq.Tolerance ∆fc ±0.1 %

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to producti on testing.

7V

10 mA

500 mW

DC Electrical Characteristics - V

Characteristics Sym Min Typ

S

1
2 Operating supply current I
3 Power consumption P

4
5 Low level input voltage V
6 Input leakage current I
7 Pull up (source) current I

8 Pull down (sink) current I

9 Input impedance (IN+, IN-) R
10 Steering threshold voltage V
11
12 High level output voltage V
13 Output low (sink) current I
14 Output high (source) current I
15 V
16 V

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to producti on testing.

Standby supply current I

U
P
P

L

Y

High level input V

I
N
P
U

T

S

Low level output voltage V

O
U

T
P
U

T
S

output voltage V

Ref

output resistance R

Ref

=5.0V± 5%, VSS=0V, -40°C ≤ TO ≤ +85°C, unless otherwise stated.

DD

‡

Max Units Test Conditions

DDQ

DD

O

IH

IL

IH/IIL

SO

SI

IN

TSt

OL

OHVDD
OL
OH

Ref

OR

3.5 V VDD=5.0V

2.2 2. 4 2 .5 V VDD = 5.0V

-0.03 V No load

1.0 2.5 mA V

0.4 0.8 mA V

2.3 2.5 2.7 V No load, VDD = 5.0V

10 25 µA PWDN=V

3.0 9.0 mA
15 mW fc=3.579545 MHz

1.5 V VDD=5.0V

0.1 µAVIN=V

7.5 20 µA TOE (pin 10)=0,

15 45 µA INH=5.0V, PWDN=5.0V,

10 MΩ @ 1 kHz

VSS+0.03 V No load

1kΩ

V

V

DD

DD

OUT
OUT

SS

=5.0V

=5.0V

=0.4 V
=4.6 V

DD

or V

DD

4-17

MT8870D/MT8870D-1 ISO

2

-CMOS

Operating Characteristics - V

=5.0V±5%, VSS=0V, -40°C ≤ TO ≤ +85°C ,unless otherwise stated.

DD

Gain Setting Amplifier

Characteristics Sym Min Typ

1 Input leakage current I
2 Input resistance R
3 Input offset voltage V

IN

IN

OS

10 MΩ

‡

Max Units Test Co ndi tions

100 nA V

SS

25 m V
4 Power supply rejection PSRR 50 dB 1 kHz
5 Common mode rejection CMRR 40 dB 0.75 V ≤ V

at V

Ref

6 DC open loop voltage gain A
7 Unity gain bandwidth f
8 Output voltage swing V
9 Maximum capacitive load (GS) C

10 R e sistive load (GS) R
11 Common mode range V

VOL

C

O

L
L

CM

MT8870D AC Electrical Characteristics -V

Characteristics Sym Min Typ

32 dB

0.30 MHz

4.0 V

Load ≥ 100 kΩ to V

pp

100 pF

50 kΩ

2.5 V

=5.0V ±5%, VSS=0V, -40°C ≤ TO ≤ +85°C , using T est Circuit shown in

DD

Figure 10.

‡

Max Units Notes*

pp

No Load

≤ VIN ≤ V

IN

=2.5 V

DD

≤ 4.25 V biased

@ GS

SS

V alid input signal levels (each

1

tone of composite signal)

-29 +1 d Bm 1,2,3, 5,6,9

27.5 869 mV

RMS

1,2,3,5, 6, 9
2 Negative twist accept 8 dB 2,3,6,9,12
3 Positive twist accept 8 dB 2,3,6,9, 12
4 Frequency deviat ion ac cept ±1.5% ± 2 Hz 2,3,5,9
5 Frequency deviation reject ±3.5% 2,3,5,9
6 Third tone tolerance -16 dB 2,3,4,5,9, 10
7 Noise tolerance -12 dB 2,3,4,5,7,9,10
8 Dial tone tolerance +22 dB 2,3,4,5,8,9,11

‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to produ ct ion testin g.

*NOTES

1. dBm= decibel s abov e or belo w a refer enc e power of 1 mW into a 600 ohm lo ad.

2. Digit sequence consists of all DTMF tones.

3. Tone duration= 4 0 m s , ton e pa us e= 40 ms.

4. Sign al c on dit ion consis ts o f nominal D TM F fr e qu en ci es .

5. Both to ne s in compo si te si gn al h av e an equal am pl itude.

6. Tone pair is d ev ia ted b y ±1 .5 % ± 2 H z .

7. Band w id th li mited (3 k H z ) G a us si an n oi se .

8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.

9. For a n err o r ra te of better t ha n 1 i n 1 0,000.

10. Refe ren ce d to lowest l ev e l f r eq ue nc y co m po ne nt in D TM F si gn al .

11. Re fe r en c ed to th e minimum v ali d ac ce p t level.

12. Guaranteed by design and characterization.

4-18

2

ISO

-CMOS MT8870D/MT8870D-1

MT8870D-1 AC Electrical Characteristics -V

Characteristi cs Sym Min Typ

V alid input signal levels (each

1

tone of composite signal)

2 Input Signal Level Reject

=5.0V±5%, VSS=0V, -40°C ≤ TO ≤ +85°C , using T est Circuit shown in

DD

Figure 10.

‡

Max Units Notes*

-31 +1 dBm T ested at V

21.8 869 mV

RMS

1,2,3,5,6,9

-37 dBm T ested at V

10.9 mV

RMS

1,2,3,5,6,9

DD

DD

=5.0V

=5.0V

3 Negative twist accept 8 dB 2,3,6,9,13
4 Positive twist acce p t 8 dB 2,3,6,9,13
5 Frequency deviation accept ±1.5%± 2 Hz 2,3,5,9
6 Frequency deviation reject ± 3.5% 2, 3,5, 9
7 Third zone tolerance -18.5 dB 2,3,4,5,9,12
8 Noise tolerance -12 dB 2,3,4,5,7,9,10
9 Dial tone tolerance +22 dB 2,3,4,5,8,9,11

‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to produ ctio n testing.

*NOTES

1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.

2. Digit se qu en c e c o ns is ts of a ll D TM F tones.

3. Tone du rat ion = 40 ms, t on e p au s e= 40 m s .

4. Signa l co nd iti on c on s is ts of no m in al D TM F fr eq ue n ci es .

5. Both ton es i n c o mposite si gn al ha v e a n equal a m pl itu de .

6. Tone pa ir i s de vi at ed by ±1 .5 %± 2 H z .

7. Band w id th lim i ted (3 kH z ) G au s si an no is e .

8. The p re ci se d ia l tone freq uencies are ( 3 50 Hz and 440 Hz) ± 2 %.

9. For a n e rro r ra te of better th an 1 in 1 0,0 00 .

10. Refe ren ce d to lowest l ev e l f r eq ue nc y co m po ne nt in D TM F si gn al .

11. Re fe r en c ed to th e minimum v ali d ac ce p t level.

12. Referenced to Fig. 10 input DTMF tone level at -25dBm (-28dBm at GS Pin) interference frequency range between 480-3400Hz.

13. Guaranteed by design and characterization.

4-19

MT8870D/MT8870D-1 ISO

2

-CMOS

AC Electrical Characteristics - V

=5.0V±5%, VSS=0V, -40°C ≤ To ≤ +85°C , using Test Circuit shown in Figure 10.

DD

Characteristics Sym Mi n Typ

1
2 Tone absent detect time t
3 Tone durat ion a ccep t t
4 Tone durat ion reject t
5 Interdigit pause accept t

Tone present det ect time t

T

I

M

I
N
G

6 Interdigit pause reject t
7
8 Propagation delay (St to StD) t
9 Output data set up (Q to StD) t

10 Propagati on delay (TOE to Q ENABLE) t

11 Propagation delay (TOE to Q DISABLE ) t

12
13 Power-down time t

Propagation delay (St to Q) t

O
U

T
P

U

T
S

P

Power-up time t

D

W

N

DP

DA
REC
REC

ID

DO

PQ

PStD

QStD

PTE

PTD

PU

PD

‡

Max Units Conditions

5 11 14 ms Note 1

0.5 4 8.5 ms Note 1
40 ms Note 2

20 ms Note 2

40 ms Note 2

20 ms Note 2

811µsTOE=V

12 16 µsTOE=V

3.4 µsTOE=V
50 ns load of 10 kΩ,

50 pF

300 ns load of 10 kΩ ,

50 pF
30 ms Note 3
20 ms

DD
DD
DD

14
15 Clock input rise ti me t
16 Clock input fall time t
17 Clock in put dut y cycle D C
18 Capacitive load (OSC2) C

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to producti on testing.

*NOTES:

1. Used for g ua rd- t im e c a lc ul ati on p ur p os e s only.

2. These, use r adjustab le p arameters , a re not dev ic e sp ec if ic at ions. The a dj us table set tin gs o f these m in im um s a nd m ax im u ms

3. With valid ton e present at input, t

Crystal/clock frequency f

C

L
O
C

K

are recommendations based upon network requirements.

C

DTMF
Input

1

R

R

X-tal

equals time from PDWN goi ng low until ESt go in g hig h.

PU

V

DD

1

2

MT8870D/MT8870D-1

IN+
IN­GS
V

Ref

INH
PDWN
OSC 1
OSC 2
V

SS

V

DD

St/GT

ESt
StD

Q4
Q3
Q2
Q1

TOE

C
LHCL
HLCL

CL

LO

3.5759 3.5795 3.5831 MHz
110 ns E xt. clock
110 ns E xt. clock

40 50 60 % Ext. clock

30 pF

C

2

R

3

NOTES:
R

=100KΩ ± 1%

1,R2

R

=300 KΩ ± 1%

3

C

=100 nF ± 5%

1,C2

X-tal=3.579545 MHz ± 0.1%

4-20

Figure 10 - Single-Ended Input Configuration

EVENTS

2

ISO

-CMOS MT8870D/MT8870D-1

D

ABC

EFG

t

REC

V

in

t

DP

t

REC

TONE #n

t

ID

TONE
#n + 1

t

DA

t

DO

TONE
#n + 1

ESt

t

GTP

t

GTA

V

St/GT

t

Q

1-Q4

StD

TOE

PQ

DECODED TONE # (n-1)

t

PSrD

t

QStD

# n # (n + 1)

HIGH IMPEDANCE

t

PTD

t

PTE

EXPLANATION OF EVENTS

A) TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED.
B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS
C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMIAN LATCHED UNTIL NEXT VALID

TONE.
D) OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE.
E) TONE #n + 1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY

HIGH IMPEDANCE).
F) ACCEPTABLE DROPOUT OF TONE #n + 1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED.
G) END OF TONE #n + 1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT

VALID TONE.

TSt

EXPLANATION OF SYMBOLS

V

in

DTMF COMPOSITE INPUT SIGNAL.
ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
Q

1-Q4

4-BIT DECODED TONE OUTPUT.
StD DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE

REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL.
TOE TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q
t

REC

t

REC

t

ID

t

DO

t

DP

t

DA

t

GTP

t

GTA

MAXIMUM DTMF SIGNAL DURATION NOT DETECED AS VALID

MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION

MAXIMUM TIME BETWEEN VALID DTMF SIGNALS.

MAXIMUM ALL OWAB L E DR OP O U T D UR I N G VALID DTMF SIGN AL.

TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS.

TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS.

GUARD TIME, TONE PRESENT.

GUARD TIME, TONE ABSENT.

TO ITS HIGH IMPEDANCE STATE.

1-Q4

Figure 11 - Timing Diagram

4-21

MT8870D/MT8870D-1 ISO

NOTE S:

2

-CMOS

4-22