Datasheet MT8870D Specification

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Page 1



ISO2-CMOS

MT8870D/MT8870D-1

Integrated DTMF Receiver

Features

• Complete DTMF Receiver

• Low power consumption

• Internal gain setting ampliﬁer

• Adjustable guard time

• Central ofﬁce quality

• Power-down mode

• Inhibit mode

• Backward compatible with MT8870C/MT8870C-1

Applications

• Receiver system for British Telecom (BT) or CEPT Spec (MT8870D-1)

• Paging systems

• Repeater systems/mobile radio

• Credit card systems

• Remote control

• Personal computers

• Telephone answering machine

ISSUE 4 August 1996

Ordering Information

MT8870DE/DE-1 18 Pin Plastic DIP MT8870DC/DC-1 18 Pin Ceramic DIP MT8870DS/DS-1 18 Pin SOIC MT8870DN/DN-1 20 Pin SSOP

-40 °C to +85 °C

Description

The MT8870D/MT8870D-1 is a complete DTMF receiver integrating both the bandsplit ﬁlter and digital decoder functions. The ﬁlter section uses switched capacitor techniques for high and low group ﬁlters; the decoder uses digital counting techniques to detect and decode all 16 DTMF tonepairs into a 4-bit code. External component count is minimized by on chip provision of a differential input ampliﬁer, clock oscillator and latched three-state bus interface.

PWDN

IN +

IN -

VDD VSS VRef INH

Bias

Circuit

Chip

Power

Bias

Dial Tone Filter

OSC1 OSC2 St/GT ESt STD TOE

High Group

Filter

Low Group

Filter

to all Chip Clocks

VRef Buffer

Zero Crossing Detectors

Digital Detection Algorithm

St GT

Code Converter and Latch

Steering Logic

Figure 1 - Functional Block Diagram

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MT8870D/MT8870D-1 ISO

-CMOS

IN+

IN-

INH

4 5

6 7 8 9

VRef

PWDN

OSC1 OSC2

VSS

18 PIN CERDIP/PLASTIC DIP/SOIC

18 17 16 15 14 13 12 11 10

VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE

IN+

IN-

VRef

INH

PWDN

NC OSC1 OSC2

VSS

1 2

3 4

5 6

7 8 9

20 PIN SSOP

20 19 18 17 16 15 14 13 12 11

VDD St/GT ESt StD NC

Q4 Q3 Q2 Q1 TOE

Figure 2 - Pin Connections

Pin Description

Pin #

18 20

1 1 IN+ Non-Inverting Op-Amp (Input). 2 2 IN- Inverting Op-Amp (Input). 33 GS Gain Select. Gives access to output of front end differential ampliﬁer for connection of

44 V

Name Description

feedback resistor. Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at mid-rail (see Fig. 6

Ref

and Fig. 10).

5 5 INH Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C

and D. This pin input is internally pulled down.

6 6 PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This

pin input is internally pulled down. 7 8 OSC1 Clock (Input). 8 9 OSC2 Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2

completes the internal oscillator circuit. 910 VSSGround (Input). 0V typical.

10 11 TOE Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is

pulled up internally.

11-1412-15Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the

last valid tone-pair received (see Table 1). When T OE is logic low, the data outputs are high

impedance.

15 17 StD Delayed Steering (Output).Presents a logic high when a received tone-pair has been

registered and the output latch updated; returns to logic low when the voltage on St/GT falls

below V

TSt

16 18 ESt Early Steering (Output). Presents a logic high once the digital algorithm has detected a

valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to

return to a logic low.

17 19 St/GT Steering Input/Guard time (Output) Bidirectional. A voltage greater than V

detected at

TSt

St causes the device to register the detected tone pair and update the output latch. A

voltage less than V

frees the device to accept a new tone pair. The GT output acts to

TSt

reset the external steering time-constant; its state is a function of ESt and the voltage on St.

18 20 V

4-12

Positive power supply (Input). +5V typical.

NC No Connection.

Page 3

ISO

Functional Description

The MT8870D/MT8870D-1 monolithic DTMF receiver offers small size, low power consumption and high performance. Its architecture consists of a bandsplit ﬁlter section, which separates the high and low group tones, followed by a digital counting section which veriﬁes the frequency and duration of the received tones before passing the corresponding code to the output bus.

-CMOS MT8870D/MT8870D-1

St/GT

ESt

StD

Filter Section

Separation of the low-group and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass ﬁlters, the bandwidths of which correspond to the low and high group frequencies. The ﬁlter section also incorporates notches at 350 and 440 Hz for exceptional dial tone rejection (see Figure 3). Each ﬁlter output is followed by a single order switched capacitor ﬁlter section which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals.

Decoder Section

MT8870D/

MT8870D-1

=(RC)In(VDD/V

GTA

=(RC)In[VDD/(VDD-V

GTP

TSt

)

)]

TSt

Figure 4 - Basic Steering Circuit

providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry speciﬁcations) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state (see “Steering Circuit”).

Steering Circuit

Before registration of a decoded tone pair, the receiver checks f or a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes vc (see Figure 4) to rise as the capacitor discharges. Provided signal

ATTENUATION

(dB)

XY ABCD

FREQUENCY (Hz)

Figure 3 - Filter Response

PRECISE DIAL TONES

X=350 Hz Y=440 Hz

DTMF TONES A=697 Hz

B=770 Hz C=852 Hz D=941 Hz E=1209 Hz F=1336 Hz G=1477 Hz H=1633 Hz

1kHz

EF G H

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MT8870D/MT8870D-1 ISO

-CMOS

condition is maintained (ESt remains high) for the validation period (t (V

) of the steering logic to register the tone pair,

TSt

), vc reaches the threshold

GTP

latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and drives vcto VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output ﬂag (StD) goes high, signalling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.

Guard Time Adjustment

In many situations not requiring selection of tone duration and interdigital pause, the simple steering circuit shown in Figure 4 is applicable. Component values are chosen according to the formula:

REC=tDP+tGTP

tID=tDA+t

GTA

The value of tDP is a device parameter (see Figure

11) and t

is the minimum signal duration to be

REC

recognized by the receiver. A value for C of 0.1 µF is

St/GT

ESt

St/GT

=(RPC1)In[VDD/(VDD-V

GTP

=(R1C1)In(VDD/V

GTA

=(R1R2)/(R1+R2)

a) decreasing t

=(R1C1)In[VDD/(VDD-V

GTP

=(RPC1)In(VDD/V

GTA

=(R1R2)/(R1+R2)

GTP

; (t

)]

TSt

)

TSt

GTP<tGTA

)]

TSt

)

TSt

)

Digit TOE INH ESt Q ANYLXHZZZZ

1HXH0001 2HXH0010 3HXH0011 4HXH0100 5HXH0101 6HXH0110 7HXH0111 8HXH1000 9HXH1001 0HXH1010

*HXH1011 #HXH1100 AHLH1101 BHLH1110 CHLH1111 DHLH0000 AHHL BHHL CHHL DHHL

undetected, the output code will remain the same as the previous detected code

Table 1. Functional Decode Table

L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE X = DON‘T CARE

recommended for most applications, leaving R to be selected by the designer.

Different steering arrangements may be used to select independently the guard times for tone present (t

) and tone absent (t

GTP

). This may be

GTA

necessary to meet system speciﬁcations which place both accept and reject limits on both tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing t

REC

improves talk-off performance since it reduces the probability that tones simulated by speech will maintain signal condition long enough to be registered. Alternatively, a relatively shor t t

REC

with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 5.

4-14

ESt

b) decreasing t

Figure 5 - Guard Time Adjustment

GTA

; (t

GTP>tGTA

)

Page 5

Power-down and Inhibit Mode

ISO

-CMOS MT8870D/MT8870D-1

A logic high applied to pin 6 (PWDN) will power down the device to minimize the power consumption in a standby mode. It stops the oscillator and the functions of the ﬁlters.

Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of tones representing characters A, B, C, and D. The output code will remain the same as the previous detected code (see Table 1).

Differential Input Conﬁguration

The input arrangement of the MT8870D/MT8870D-1 provides a differential-input operational ampliﬁer as well as a bias source (V

) which is used to bias the

Ref

inputs at mid-rail. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a single-ended conﬁguration, the input pins are connected as shown in Figure 10 with the op-amp connected for unity gain and V

Ref

biasing the input at1/2VDD. Figure 6 shows the differential conﬁguration, which permits the adjustment of gain with the feedback resistor R5.

C1R

Differential Input Amplifier

C1=C2=10 nF R1=R4=R5=100 kΩ

=60kΩ, R3=37.5 kΩ

2R5

R2+R

VOLTAGE GAIN (Av diff)=

INPUT IMPEDANCE

) = 2

INDIFF

IN+

IN-

MT8870D/ MT8870D-1

ωc

Ref

All resistors are ±1% tolerance. All capacitors are ±5% tolerance.

Crystal Oscillator

The internal clock circuit is completed with the addition of an external 3.579545 MHz crystal and is normally connected as shown in Figure 10 (SingleEnded Input Conﬁguration). However, it is possible to conﬁgure several MT8870D/MT8870D-1 devices employing only a single oscillator crystal. The oscillator output of the ﬁrst device in the chain is coupled through a 30 pF capacitor to the oscillator input (OSC1) of the next device. Subsequent devices are connected in a similar fashion. Refer to Figure 7 for details. The problems associated with unbalanced loading are not a concern with the arrangement shown, i.e., precision balancing capacitors are not required.

Figure 6 - Differential Input Conﬁguration

To OSC1 of next

MT8870D/MT8870D-1

C=30 pF X-tal=3.579545 MHz

OSC1

OSC2

X-tal

OSC2

OSC1

Figure 7 - Oscillator Connection

Parameter Unit Resonator

R1 Ohms 10.752 L1 mH .432 C1 pF 4.984 C0 pF 37.915

Qm - 896.37

∆f%±0.2%

Table 2. Recommended Resonator Speciﬁcations

Note: Qm=quality factor of RLC model, i.e., 1/2ΠƒR1C1.

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MT8870D/MT8870D-1 ISO

Applications

RECEIVER SYSTEM FOR BRITISH TELECOM SPEC POR 1151

-CMOS

=(RPC1)In[VDD/(VDD-V

GTP

TSt

)]

The circuit shown in Fig. 9 illustrates the use of MT8870D-1 device in a typical receiver system. BT Spec deﬁnes the input signals less than -34 dBm as the non-operate level. This condition can be attained by choosing a suitable values of R1 and R2 to provide 3 dB attenuation, such that -34 dBm input signal will correspond to -37 dBm at the gain setting pin GS of MT8870D-1. As shown in the diagram, the component values of R3 and C2 are the guard time requirements when the total component tolerance is 6%. For better performance, it is recommended to use the non-symmetric guard time circuit in Fig. 8.

St/GT

ESt

=(R1C1)In(VDD/V

GTA

=(R1R2)/(R1+R2)

Notes: R1=368K Ω ± 1% R

=2.2M Ω ± 1%

=100nF ± 5%

TSt

)

Figure 8 - Non-Symmetric Guard Time Circuit

DTMF Input

MT8870D-1

IN+ INGS V

Ref

INH PWDN OSC 1 OSC 2 V

St/GT

ESt

StD

Q4 Q3 Q2 Q1

TOE

NOTES: R

= 102KΩ ± 1%

= 71.5KΩ ± 1%

= 390KΩ ±1 %

= 100 nF ± 5%

1,C2

= 3.579545 MHz ± 0.1%

= 5.0V ± 5%

Figure 9 - Single-Ended Input Conﬁguration for BT or CEPT Spec

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ISO

-CMOS MT8870D/MT8870D-1

Absolute Maximum Ratings

†

Parameter Symbol Min Max Units

1 DC Power Supply Voltage V 2 Voltage on any pin V 3 Current at any pin (other than supply) I 4 Storage temperature T 5 Package power dissipation P

† Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Derate above 75 °C at 16 mW / °C. All leads soldered to board.

Recommended Operating Conditions - Voltages are with respect to ground (V

Parameter Sym Min Typ

1 DC Power Supply Voltage V 2 Operating Temperature T 3 Crystal/Clock Frequency fc

4.75 5.0 5.25 V

-40 +85 °C

3.579545

STG

‡

Max Units Test Conditions

VSS-0.3 VDD+0.3 V

-65 +150 °C

) unless otherwise stated.

MHz

4 Crystal/Clock Freq.Tolerance ∆fc ±0.1 %

‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

10 mA

500 mW

DC Electrical Characteristics - V

Characteristics Sym Min Typ

1 2 Operating supply current I 3 Power consumption P

4 5 Low level input voltage V 6 Input leakage current IIH/I 7 Pull up (source) current I

8 Pull down (sink) current I

9 Input impedance (IN+, IN-) R 10 Steering threshold voltage V 11 12 High level output voltage V 13 Output low (sink) current I 14 Output high (source) current I 15 V 16 V

‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Standby supply current I

U P P

High level input V

I N P U

Low level output voltage V

O U

T P U

T S

output voltage V

Ref

output resistance R

Ref

=5.0V± 5%, VSS=0V, -40°C ≤ TO≤ +85°C, unless otherwise stated.

‡

Max Units Test Conditions

DDQ

IN TSt OL OHVDD

Ref OR

3.5 V VDD=5.0V

2.2 2.4 2.5 V VDD = 5.0V

-0.03 V No load

1.0 2.5 mA V

0.4 0.8 mA V

2.3 2.5 2.7 V No load, VDD = 5.0V

10 25 µA PWDN=V

3.0 9.0 mA 15 mW fc=3.579545 MHz

1.5 V VDD=5.0V

0.1 µAVIN=VSSor V

7.5 20 µA TOE (pin 10)=0,

15 45 µA INH=5.0V, PWDN=5.0V,

10 MΩ @ 1 kHz

VSS+0.03 V No load

1kΩ

VDD=5.0V

=0.4 V

OUT

=4.6 V

OUT

4-17

Page 8

MT8870D/MT8870D-1 ISO

-CMOS

Operating Characteristics - V

=5.0V±5%, VSS=0V, -40°C ≤ TO≤ +85°C ,unless otherwise stated.

Gain Setting Ampliﬁer

Characteristics Sym Min Typ‡Max Units Test Conditions

1 Input leakage current I 2 Input resistance R 3 Input offset voltage V

10 MΩ

100 nA VSS≤ VIN≤ V

25 mV

4 Power supply rejection PSRR 50 dB 1 kHz 5 Common mode rejection CMRR 40 dB 0.75 V ≤ VIN≤ 4.25 V biased

6 DC open loop voltage gain A 7 Unity gain bandwidth f 8 Output voltage swing V

9 Maximum capacitive load (GS) C 10 Resistive load (GS) R 11 Common mode range V

VOL

L L

MT8870D AC Electrical Characteristics -V

32 dB

0.30 MHz

4.0 V

2.5 V

Figure 10.

at V

Load ≥ 100 kΩ to VSS@ GS

100 pF

50 kΩ

No Load

=5.0V ±5%, VSS=0V, -40°C ≤ TO≤ +85°C , using Test Circuit shown in

Ref

=2.5 V

Characteristics Sym Min Typ‡Max Units Notes*

V alid input signal lev els (each

tone of composite signal)

-29 +1 dBm 1,2,3,5,6,9

27.5 869 mV

RMS

1,2,3,5,6,9 2 Negative twist accept 8 dB 2,3,6,9,12 3 Positive twist accept 8 dB 2,3,6,9,12 4 Frequency deviation accept ±1.5% ± 2 Hz 2,3,5,9 5 Frequency deviation reject ±3.5% 2,3,5,9 6 Third tone tolerance -16 dB 2,3,4,5,9,10 7 Noise tolerance -12 dB 2,3,4,5,7,9,10 8 Dial tone tolerance +22 dB 2,3,4,5,8,9,11

‡ Typical ﬁgures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

*NOTES

1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.

2. Digit sequence consists of all DTMF tones.

3. Tone duration= 40 ms, tone pause= 40 ms.

4. Signal condition consists of nominal DTMF frequencies.

5. Both tones in composite signal have an equal amplitude.

6. Tone pair is deviated by ±1.5 %± 2 Hz.

7. Bandwidth limited (3 kHz ) Gaussian noise.

8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.

9. For an error rate of better than 1 in 10,000.

10. Referenced to lowest level frequency component in DTMF signal.

11. Referenced to the minimum valid accept level.

12. Guaranteed by design and characterization.

4-18

Page 9

ISO

-CMOS MT8870D/MT8870D-1

MT8870D-1 AC Electrical Characteristics -V

Characteristics Sym Min Typ

V alid input signal lev els (each

tone of composite signal)

=5.0V±5%, VSS=0V, -40°C ≤ TO≤ +85°C , using Test Circuit shown

in Figure 10.

‡

Max Units Notes*

-31 +1 dBm T ested at VDD=5.0V

21.8 869 mV

RMS

1,2,3,5,6,9

-37 dBm T ested at VDD=5.0V

2 Input Signal Level Reject

10.9 mV

RMS

1,2,3,5,6,9

3 Negative twist accept 8 dB 2,3,6,9,13 4 Positive twist accept 8 dB 2,3,6,9,13 5 Frequency deviation accept ±1.5%± 2 Hz 2,3,5,9 6 Frequency deviation reject ±3.5% 2,3,5,9 7 Third zone tolerance -18.5 dB 2,3,4,5,9,12 8 Noise tolerance -12 dB 2,3,4,5,7,9,10 9 Dial tone tolerance +22 dB 2,3,4,5,8,9,11

‡ Typical ﬁgures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

*NOTES

1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.

2. Digit sequence consists of all DTMF tones.

3. Tone duration= 40 ms, tone pause= 40 ms.

4. Signal condition consists of nominal DTMF frequencies.

5. Both tones in composite signal have an equal amplitude.

6. Tone pair is deviated by ±1.5 %± 2 Hz.

7. Bandwidth limited (3 kHz ) Gaussian noise.

8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.

9. For an error rate of better than 1 in 10,000.

10. Referenced to lowest level frequency component in DTMF signal.

11. Referenced to the minimum valid accept level.

12. Referenced to Fig. 10 input DTMF tone level at -25dBm (-28dBm at GS Pin) interference frequency range between 480-3400Hz.

13. Guaranteed by design and characterization.

4-19

Page 10

MT8870D/MT8870D-1 ISO

-CMOS

AC Electrical Characteristics - V

=5.0V±5%, VSS=0V, -40°C ≤ To ≤ +85°C , using Test Circuit shown in Figure 10.

Characteristics Sym Min Typ

1 2 Tone absent detect time t 3 Tone duration accept t 4 Tone duration reject t 5 Interdigit pause accept t

Tone present detect time t

I N G

6 Interdigit pause reject t 7 8 Propagation delay (St to StD) t 9 Output data set up (Q to StD) t

10 Propagation delay (TOE to Q ENABLE) t

11 Propagation delay (TOE to Q DISABLE) t

12 13 Power-down time t

Propagation delay (St to Q) t

O U

T P

Power-up time t

DA REC REC

ID DO PQ

PStD QStD

PTE

PTD

PU PD

‡

Max Units Conditions

5 11 14 ms Note 1

0.5 4 8.5 ms Note 1 40 ms Note 2

20 ms Note 2

40 ms Note 2

20 ms Note 2

811µs TOE=V

12 16 µs TOE=V

3.4 µs TOE=V 50 ns load of 10 kΩ,

50 pF

300 ns load of 10 kΩ,

50 pF 30 ms Note 3 20 ms

DD DD DD

14 15 Clock input rise time t 16 Clock input fall time t 17 Clock input duty cycle DC 18 Capacitive load (OSC2) C

‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

*NOTES:

1. Used for guard-time calculation purposes only.

2. These, user adjustable parameters, are not device speciﬁcations. The adjustable settings of these minimums and maximums

3. With valid tone present at input, tPU equals time from PDWN going low until ESt going high.

Crystal/clock frequency f

L O C

are recommendations based upon network requirements.

DTMF Input

X-tal

MT8870D/MT8870D-1

IN+ INGS V

Ref

INH PDWN OSC 1 OSC 2 V

St/GT

ESt

StD

Q4 Q3 Q2 Q1

TOE

C LHCL HLCL

3.5759 3.5795 3.5831 MHz 110 ns Ext. clock 110 ns Ext. clock

40 50 60 % Ext. clock

30 pF

NOTES: R1,R2=100KΩ ± 1% R

=300KΩ ± 1%

=100 nF ± 5%

1,C2

X-tal=3.579545 MHz ± 0.1%

4-20

Figure 10 - Single-Ended Input Conﬁguration

Page 11

EVENTS

ISO

-CMOS MT8870D/MT8870D-1

ABC

EFG

REC

TONE #n

TONE #n + 1

ESt

GTP

GTA

St/GT

1-Q4

DECODED TONE # (n-1)

PSrD

StD

TOE

EXPLANATION OF EVENTS

TONE. D) OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE. E) TONE #n + 1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY

HIGH IMPEDANCE). F) ACCEPTABLE DROPOUT OF TONE #n + 1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED. G) END OF TONE #n + 1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT

VALID TONE.

QStD

# n

HIGH IMPEDANCE

PTD

# (n + 1)

PTE

TSt

EXPLANATION OF SYMBOLS

DTMF COMPOSITE INPUT SIGNAL.

ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. Q1-Q44-BIT DECODED TONE OUTPUT. StD DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE

REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. TOE TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q1-Q4 TO ITS HIGH IMPEDANCE STATE. t

REC

GTP

GTA

MAXIMUM DTMF SIGNAL DURATION NOT DETECED AS VALID

MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION

MAXIMUM TIME BETWEEN VALID DTMF SIGNALS.

MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL.

TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS.

TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS.

GUARD TIME, TONE PRESENT.

GUARD TIME, TONE ABSENT.

Figure 11 - Timing Diagram

4-21

Page 12



ISO2-CMOS

MT8880C/MT8880C-1

Integrated DTMF Transceiver

Features

• Complete DTMF transmitter/receiver

• Central ofﬁce quality

• Low power consumption

• Microprocessor port

• Adjustable guard time

• Automatic tone burst mode

• Call progress mode

Applications

• Credit card systems

• Paging systems

• Repeater systems/mobile radio

• Interconnect dialers

• Personal computers

Description

ISSUE 3 September 1995

Ordering Information

MT8880CE/CE-1 20 Pin Plastic DIP MT8880CC/CC-1 20 Pin Ceramic DIP MT8880CS/CS-1 20 Pin SOIC MT8880CN/CN-1 24 Pin SSOP MT8880CP/CP-1 28 Pin Plastic LCC

-40°C to +85°C

based upon the industry standard MT8870 monolithic DTMF receiver; the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress ﬁlter can be selected allowing a microprocessor to analyze call progress tones. A standard microprocessor bus is provided and is directly compatible with 6800 series microprocessors. The MT8880C-1 is functionally identical to the MT8880C except for the performance of the receiver section, which is enhanced to accept and reject lower signal levels.

The MT8880C/C-1 is a monolithic DTMF transceiver with call progress ﬁlter. It is fabricated in Mitel’s ISO2-CMOS technology, which provides low power dissipation and high reliability. The DTMF receiver is

Row and

Column

Counters

Digital Algorithm and Code Converter

Steering

Logic

ESt St/GT

TONE

IN+

INGS

OSC1 OSC2

∑

Tone Burst

Gating Cct.

Oscillator

Circuit

Bias

Circuit

DDVRefVSS

Dial Tone Filter

D/A

Converters

Control

Logic

High Group

Filter

Low Group

Filter

Control

Logic

Figure 1 - Functional Block Diagram

Transmit Data

Status

Control

Receive Data

Data

Bus

Buffer

Interrupt

Logic

I/O

Control

D0 D1 D2 D3

IRQ/CP

Φ2 CS R/

RS0

4-33

Page 13

MT8880C/MT8880C-1 ISO

IN+

IN-

VRef

VSS OSC1 OSC2

TONE

4 5

6 7 8

20 PIN CERDIP/PLASTIC DIP/SOIC 28 PIN PLCC

20 19 18 17 16 15 14 13 12 11

VDD St/GT ESt D3 D2 D1 D0 IRQ/CP Φ2 RS0

IN+

INGS

VRef

VSS OSC1 OSC2

NC NC

TONE

-CMOS

1 2

3 4 5

6 7 8

9 10 11 12

24 PIN SSOP

24 23 22 21 20 19 18 17 16 15 14 13

VDD St/GT ESt D3 D2 D1 D0 NC NC IRQ/CP

Φ2 RS0

VRef

VSS OSC1 OSC2

NC NC

5 6 7 8 9 10 11

13 W

TONE

IN-

IN+

•

RS0

VDD

St/GT

EST

/CP IRQ

25 24 23 22 21 20 19

NC NC NC D3 D2 D1 D0

Figure 2 - Pin Connections

Pin Description

Pin #

20 24 28

1 1 1 IN+ Non-inverting op-amp input. 2 2 2 IN- Inverting op-amp input. 334 GSGain Select. Gives access to output of front end differential ampliﬁer for connection of

446V 557VSSGround input (0V). 6 6 8 OSC1 DTMF clock/oscillator input. 7 7 9 OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the

8 10 12 TONE Tone output (DTMF or single tone). 91113R/WRead/Write input. Controls the direction of data transfer to and from the MPU and the

10 12 14 CS Chip Select, TTL input (CS=0 to select the chip). 11 13 15 RS0 Register Select input. See register decode table. TTL compatible. 12 14 17 Φ2 System Clock input. TTL compatible. N.B. Φ2 clock input need not be active when the

13 15 18 IRQ/CPInterrupt Request to MPU (open drain output). Also, when call progress (CP) mode has

14-1718-2119-22D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or Φ2 is low.

Name Description

feedback resistor. Reference Voltage output, nominally VDD/2 is used to bias inputs at mid-rail (see Fig. 13).

Ref

internal oscillator circuit. Leave open circuit when OSC1 is clock input.

transceiver registers. TTL compatible.

device is not being accessed.

been selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input op-amp. The input signal m ust be within the bandwidth limits of the call progress ﬁlter. See Figure 8.

18 22 26 ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid

tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.

19 23 27 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than V

causes the device to register the detected tone pair and update the output latch. A voltage less than V external steering time-constant; its state is a function of ESt and the voltage on St.

frees the device to accept a new tone pair. The GT output acts to reset the

TSt

detected at St

TSt

20 24 28 VDDPositive power supply input (+5V typical).

8,9

3,5,

NC No Connection.

10, 11, 16,

23-

4-34

16,

Page 14

ISO

Functional Description

The MT8880C/C-1 Integrated DTMF Transceiver architecture consists of a high performance DTMF receiver with internal gain setting ampliﬁer and a DTMF generator which employs a burst counter such that precise tone bursts and pauses can be synthesized. A call progress mode can be selected such that frequencies within the speciﬁed passband can be detected. A standard microprocessor interface allows access to an internal status register, two control registers and two data registers.

Input Conﬁguration

-CMOS MT8880C/MT8880C-1

IN+

IN-

Ref

The input arrangement of the MT8880C/C-1 provides a differential-input operational ampliﬁer as well as a bias source (V

) which is used to bias the inputs at

Ref

VDD/2. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a single-ended conﬁguration, the input pins are connected as shown in Figure 3.

Figure 4 shows the necessary connections for a differential input conﬁguration.

IN+

VOLTAGE GAIN

) = RF / R

IN-

Ref

MT8880C/C-1

Figure 3 - Single-Ended Input Conﬁguration

Receiver Section

Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass ﬁlters, the bandwidths of which correspond to the low and high group frequencies (see Fig. 7). These ﬁlters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each ﬁlter output is followed by a single order switched capacitor ﬁlter section which smooths the signals prior to limiting. Limiting is performed by high-gain comparators

MT8880C/C-1

DIFFERENTIAL INPUT AMPLIFIER

C1 = C2 = 10 nF R1 = R4 = R5 = 100 kΩ R2 = 60kΩ, R3 = 37.5 kΩ R3 = (R2R5)/(R2 + R5)

VOLTAGE GAIN

diff) = R5/R1

INPUT IMPEDANCE

diff) = 2 R12 + (1/ωC)

Figure 4 - Differential Input Conﬁguration

which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals.

Following the ﬁlter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry speciﬁcations) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state.

4-35

Page 15

MT8880C/MT8880C-1 ISO

-CMOS

Steering Circuit

Before registration of a decoded tone pair, the receiver checks for a valid signal duration (ref erred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes vc (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt remains high) for the validation period (t (V

) of the steering logic to register the tone pair,

TSt

latching its corresponding 4-bit code (see Figure 7) into the Receive Data Register. At this point the GT output is activated and drives vcto VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output ﬂag goes high, signalling that a received tone pair has been registered. The status of the delayed steering ﬂag can be monitored by checking the appropriate bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering ﬂag is active.

), vc reaches the threshold

GTP

Guard Time Adjustment

The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the formula:

= tDP+t

REC

tID=tDA+t

The value of tDP is a device parameter (see AC Electrical Characteristics) and t signal duration to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most applications, leaving R1 to be selected by the designer. Different steering arrangements may be used to select independently the guard times for tone present (t

) and tone absent (t

GTP

GTA

is the minimum

REC

). This may be

GTA

The contents of the output latch are updated on an active delayed steering transition. This data is presented to the four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.

St/GT

ESt

St/GT

ESt

St/GT

= (RPC1) In [VDD / (VDD-V

GTP

= (R1C1) In (VDD/V

GTA

= (R1R2) / (R1 + R2)

a) decreasing tGTP; (tGTP < tGTA)

= (R1C1) In [VDD / (VDD-V

GTP

= (RpC1) In (VDD/V

GTA

= (R1R2) / (R1 + R2)

TSt

)]

)

MT8880C/C-1

4-36

= (R1C1) In (VDD / V

GTA

= (R1C1) In [VDD / (VDD-V

GTP

TSt

)

Figure 5 - Basic Steering Circuit

TSt

)]

ESt

b) decreasing tGTA; (tGTP > tGTA)

Figure 6 - Guard Time Adjustment

Page 16

ISO

-CMOS MT8880C/MT8880C-1

Increasing t

improves talk-off performance since

REC

it reduces the probability that tones simulated by speech will maintain a valid signal condition long enough to be registered. Alternatively, a relatively short t

with a long tDO would be appropriate for

REC

extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in Figure 9 with a description of the events in Figure 11.

Call Progress Filter

A call progress mode, using the MT8880C/C-1, can be selected allowing the detection of various tones which identify the progress of a telephone call on the network. The call progress tone input and DTMF input are common, however, call progress tones can only be detected when CP mode has been selected. DTMF signals cannot be detected if CP mode has been selected (see Table 5). Figure 8 indicates the useful detect bandwidth of the call progress ﬁlter. Frequencies presented to the input, which are within the ‘accept’ bandwidth limits of the ﬁlter, are hardlimited by a high gain comparator with the IRQ/CP pin serving as the output. The squarewave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of the call progress tone being detected. Frequencies which are in the ‘reject’ area will not be detected and consequently the IRQ/CP pin will remain low.

DTMF Generator

LOW

HIGH

DIGIT D

697 1209 1 0001 697 1336 2 0010 697 1477 3 0011 770 1209 4 0100 770 1336 5 0101 770 1477 6 0110 852 1209 7 0111 852 1336 8 1000 852 1477 9 1001 941 1336 0 1010 941 1209 * 1011 941 1477 # 1100 697 1633 A 1101 770 1633 B 1110 852 1633 C 1111 941 1633 D 0000

0= LOGIC LOW, 1= LOGIC HIGH

Figure 7 - Functional Encode/Decode Table

LEVEL

(dBm)

The DTMF transmitter employed in the MT8880C/C1 is capable of generating all sixteen standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor D/A converters. The row and column tones are mixed and ﬁltered providing a DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format shown in Figure 7 must be written to the transmit Data Register. Note that this is the same as the receiver output code. The individual tones which are generated (f

LOW

and f

) are referred to

HIGH

as Low Group and High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 941 Hz. The high group frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (pre-emphasis) is 2dB to compensate for high group attenuation on long loops.

-25

0 250 500 750

FREQUENCY (Hz)

= Reject = May Accept = Accept

Figure 8 - Call Progress Response

The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time segment length which will ultimately determine the frequency of the tone. When the divider reaches the appropriate count, as determined by the input code, a reset pulse is issued and the counter starts again. The number

4-37

Page 17

MT8880C/MT8880C-1 ISO

-CMOS

EVENTS

ESt

St/GT

RX0-RX

Read Status Register

IRQ/CP

ABCDEF

REC

DECODED TONE # (n-1)

REC

TONE #n

GTP

PStRX

PStb3

# n

TONE #n + 1

GTA

TONE #n + 1

TSt

# (n + 1)

Figure 9 - Receiver Timing Diagram

of time segments is ﬁxed at 32, however, by varying the segment length as described above the tone output signal frequency will be varied. The divider output clocks another counter which addresses the sinewave lookup ROM.

The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and highly accurate DC voltage levels. Two identical circuits are employed to produce row and

column tones which are then mixed using a low noise summing ampliﬁer. The oscillator described needs no “start-up” time as in other DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burst accuracy. A bandwidth limiting ﬁlter is incorporated and serves to attenuate distortion products above 8 kHz. It can be seen from Figure 10 that the distortion products are very low in amplitude.

Scaling Information

10 dB/Div Start Frequency = 0 Hz Stop Frequency = 3400 Hz Marker Frequency = 697 Hz and 1209 Hz

4-38

Figure 10 - Spectrum Plot

Page 18

ISO

-CMOS MT8880C/MT8880C-1

Burst Mode

In certain telephony applications it is required that DTMF signals being generated are of a speciﬁc duration determined either by the particular application or by any one of the e xchange transmitter speciﬁcations currently existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms±1 ms which is a standard interval for autodialer and central ofﬁce applications. After the burst/pause has been issued, the appropriate bit is set in the Status Register indicating that the transmitter is ready for more data. The timing described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode) is selected, a second burst/ pause time of 102 ms ±2 ms is available. This extended interval is useful when precise tone bursts of longer than 51 ms duration and 51 ms pause are desired. Note that when CP mode and Burst mode have been selected, DTMF tones may be transmitted only and

In applications where a non-standard burst/pause duration is required, burst mode must be disabled

not

received.

and the transmitter gated on and off by an external hardware or software timer.

Single Tone Generation

A single tone mode is available whereby individual tones from the low group or high group can be generated. This mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion measurements. Refer to Control Register B description for details.

Distortion Calculations

The MT8880C/C-1 is capable of producing precise tone bursts with minimal error in frequency (see Table 1). The internal summing ampliﬁer is followed by a ﬁrst-order lowpass switched capacitor ﬁlter to minimize harmonic components and intermodulation products. The total harmonic distortion for a

tone

can be calculated using Equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage. The Fourier

components of the tone output correspond to V2f....

Vnf as measured on the output waveform. The total harmonic distortion for a

dual tone

can be calculated

single

EXPLANATION OF EVENTS

A) TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

RETAINED UNTIL NEXT VALID TONE PAIR. D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED. F) END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

RETAINED UNTIL NEXT VALID TONE PAIR.

EXPLANATION OF SYMBOLS

V ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. RX0-RX34-BIT DECODED DATA IN RECEIVE DATA REGISTER b3 DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE

b2 INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS

IRQ/CP INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS

REC

GTP

GTA

DTMF COMPOSITE INPUT SIGNAL.

REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A

VALID DTMF SIGNAL.

CLEARED AFTER THE STATUS REGISTER IS READ.

MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.

MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.

MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.

MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.

TIME TO DETECT VALID FREQUENCIES PRESENT.

TIME TO DETECT VALID FREQUENCIES ABSENT.

GUARD TIME, TONE PRESENT.

GUARD TIME, TONE ABSENT.

Figure 11 - Description of Timing Events

4-39

Page 19

MT8880C/MT8880C-1 ISO

+ V

fundamental

THD(%) = 100

+ V

Equation 1. THD (%) For a Single Tone

+ V

+ .. V

+ .... V

+ V

+ .... V

+ V

IMD

-CMOS

Maximum Series Resistance:150 ohms Maximum Drive Level: 2mW

e.g. CTS Knights MP036S

Toyocom TQC-203-A-9S

A number of MT8880C/C-1 devices can be connected as shown in Figure 12 such that only one crystal is required. Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left unconnected.

THD (%) = 100

+ V

Equation 2. THD (%) For a Dual Tone

OUTPUT FREQUENCY

ACTIVE

INPUT

SPECIFIED ACTUAL

(Hz)

%ERROR

L1 697 699.1 +0.30 L2 770 766.2 -0.49 L3 852 847.4 -0.54 L4 941 948.0 +0.74 H1 1209 1215.9 +0.57 H2 1336 1331.7 -0.32 H3 1477 1471.9 -0.35 H4 1633 1645.0 +0.73

Table 1. Actual Frequencies Versus Standard

Requirements

using Equation 2. VLand VH correspond to the low group amplitude and high group amplitude, respectively, and V

is the sum of all the

IMD

intermodulation components. The internal switchedcapacitor ﬁlter following the D/A converter keeps distortion products down to a very low level as shown in Figure 10.

DTMF Clock Circuit

The internal clock circuit is completed with the addition of a standard television colour burst crystal. The crystal speciﬁcation is as follows:

Frequency: 3.579545 MHz Frequency Tolerance: ±0.1% Resonance Mode: Parallel Load Capacitance: 18pF

MT8880C/C-1

OSC1 OSC2

3.579545 MHz

MT8880C/C-1

OSC1 OSC2

MT8880C/C-1

OSC1 OSC2

Figure 12 - Common Crystal Connection

Microprocessor Interface

The MT8880C/C-1 employs a microprocessor interface which allows precise control of transmitter and receiver functions. There are ﬁve internal registers associated with the microprocessor interface which can be subdivided into three categories, i.e., data transfer, transceiver control and transceiver status. There are two registers associated with data transfer operations.

The Receive Data Register contains the output code of the last valid DTMF tone pair to be decoded and is a read only register. The data entered in the Transmit Data Register will determine which tone pair is to be generated (see Figure 7 for coding details). Data can only be written to the transmit register. Transceiver control is accomplished with two Control Registers (CRA and CRB) which occupy the same address space. A write operation to CRB can be executed by setting the appropriate bit in CRA. The following write operation to the same address will then be directed to CRB and subsequent write cycles will then be directed back to CRA. A software reset must be included at the beginning of all programs to initialize the control and status registers after power up or power reset (see Figure 16). Refer to Tables 3, 4, 5 and 6 for details concerning the Control Registers. The IRQ/CP pin can be programmed such that it will provide an interrupt request signal upon validation of DTMF signals or when the transmitter is ready for more data (Burst mode only). The IRQ/CP pin is conﬁgured as an open drain output device and as such requires a pull-up resistor (see Figure 13).

4-40

Page 20

ISO

-CMOS MT8880C/MT8880C-1

RS0 R/W FUNCTION

0 0 Write to Transmit

Data Register

0 1 Read from Receive

Data Register

1 0 Write to Control

1 1 Read from Status

Table 2. Internal Register Functions

BIT NAME FUNCTION DESCRIPTION

b0 TOUT TONE OUTPUT A logic ‘1’ enables the tone output. This function can be

implemented in either the burst mode or non-burst mode.

b1 CP/DTMF MODE CONTROL In DTMF mode (logic ‘0’) the device is capable of generating

and receiving Dual Tone Multi-Frequency signals. When the CP (Call Progress) mode is selected (logic ‘1’) a 6th order bandpass ﬁlter is enabled to allow call progress tones to be detected. Call progress tones which are within the speciﬁed bandwidth will be presented at the IRQ/CP pin in rectangular wave format if the IRQ bit has been enabled (b2=1). Also, when the CP mode and BURST mode have both been selected, the transmitter will issue DTMF signals with a burst and pause of 102 ms (typ) duration. This signal duration is twice that obtained from the DTMF transmitter if DTMF mode had been selected. Note that DTMF signals cannot be decoded when the CP mode of operation has been selected.

b3 b2 b1 b0

RSEL IRQ CP/DTMF TOUT

Table 3. CRA Bit Positions

b3 b2 b1 b0

C/RS/D TEST BURST

Table 4. CRB Bit Positions

b2 IRQ INTERRUPT ENABLE A logic ‘1’ enables the INTERRUPT mode. When this mode is

active and the DTMF mode has been selected (b1=0) the IRQ/ CP pin will pull to a logic ‘0’ condition when either 1) a valid DTMF signal has been received and has been present for the guard time duration or 2) the transmitter is ready for more data (BURST mode only).

b3 RSEL REGISTER SELECT A logic ‘1’ selects Control Register B on the next Write cycle to

the Control Register address. Subsequent Write cycles to the Control Register are directed back to Control Register A.

Table 5. Control Register A Description

4-41

Page 21

MT8880C/MT8880C-1 ISO

BIT NAME FUNCTION DESCRIPTION

b0 BURST BURST MODE A logic ‘0’ enables the burst mode. When this mode is

b1 TEST TEST MODE By enabling the test mode (logic’1’), the IRQ/CP pin will

-CMOS

selected, data corresponding to the desired DTMF tone pair can be written to the Transmit Register resulting in a tone burst of a speciﬁc duration (see AC Characteristics). Subsequently, a pause of the same duration is induced. Immediately following the pause, the Status Register is updated indicating that the Transmit Register is ready for further instructions and an interr upt will be generated if the interrupt mode has been enabled. Additionally, if call progress (CP) mode has been enabled, the burst and pause duration is increased by a factor of two. When the burst mode is not selected (logic ‘1’) tone bursts of any desired duration may be generated.

present the delayed steering (inv erted) signal from the DTMF receiver. Refer to Figure 9 (b3 waveform) for details concerning the output waveform. DTMF mode must be selected (CRA b1=0) before test mode can be implemented.

b2 S/D SINGLE /DUAL TONE

GENERATION

b3 C/R COLUMN/ROW TONES When used in conjunction with b2 (above) the transmitter

Table 6. Control Register B Description

BIT NAME STATUS FLAG SET STATUS FLAG CLEARED

b0 IRQ Interrupt has occurred. Bit one (b1)

or bit two (b2) is set.

b1 TRANSMIT DATA

b2 RECEIVE DATA

b3 DELAYED STEERING Set upon the valid detection of the

Pause duration has terminated and transmitter is ready for new data.

Valid data is in the Receive Data Register.

absence of a DTMF signal.

Table 7. Status Register Description

A logic ‘0’ will allow Dual Tone Multi-Frequency signals to be produced. If single tone generation is enabled (logic ‘1’), either row or column tones (low group or high group) can be generated depending on the state of b3 in Control Register B.

can be made to generate single row or single column frequencies. A logic ‘0’ will select row frequencies and a logic ‘1’ will select column frequencies.

Interrupt is inactive. Cleared after Status Register is read.

Cleared after Status Register is read or when in non-burst mode.

Cleared after Status Register is read.

Cleared upon the detection of a valid DTMF signal.

4-42

Page 22

ISO

-CMOS MT8880C/MT8880C-1

DTMF/CP INPUT

DTMF OUTPUT

Notes: R1, R2 = 100 kΩ 1% R3 = 374 Ω 1% R4 = 3.3 kΩ 10%

= 10 k Ω (min.)

C1 = 100 nF 5% C2 = 100 nF 5% C3 = 100 nF 10%* C4 = 10 nF 10% X-tal = 3.579545 MHz

X-tal

MT8880C/C-1

IN+ INGS VRef VSS OSC1 OSC2 TONE R/

* Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT8880 can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided.

VDD

St/GT

ESt

D3 D2 D1 D0

IRQ/CP

Φ2

RS0

To µP or µC

TEST POINT

130 pF

Figure 13 - Application Circuit (Single-Ended Input)

MMD6150 (or equivalent)

24 kΩ

5.0 VDC

2.4 kΩ

MMD7000 (or equivalent)

TEST POINT

Figure 14 - Test Circuit

Test load for

5.0 VDC

3 kΩ

70 pF

IRQ/CP pinTest load for D0-D3 pins

4-43

Page 23

MT8880C/MT8880C-1 ISO

-CMOS

6802

Address

IRQ

VMA

Data

+5V

Peripheral decode

3.3k

MT8880C/C-1

IRQ RS0

Φ2 Data

Figure 15 - MT8880C/C-1 to 6802 Interface

EXAMPLE 1: A software reset must be included at the beginning of all programs to initialize the control

registers after power up. The initialization procedure should be implemented 100ms after power up.

Description Control Data

CS RS0 R/W b3b2 b1 b0

1) Read Status Register 0 1 1 X X X X

2) Write to Control Register 0 1 0 0 0 0 0

3) Write to Control Register 0 1 0 0 0 0 0

4) Write to Control Register 0 1 0 1 0 0 0

5) Write to Control Register 0 1 0 0 0 0 0

6) Read Status Register 0 1 1 X X X X

EXAMPLE 2: Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones Description

CS RS0 R/W b3b2 b1 b0

1) Write to Control Register A 0 1 0 1 1 0 1 (tone out, DTMF, IRQ, Select Control Register B)

2) Write to Control Register B 0 1 0 0 0 0 0 (burst mode)

3) Write to Transmit Data Register 0 0 0 0 1 1 1 (send a digit 7)

--------------------------------------

wait for an interrupt or poll Status Register ----------------------------------------------

4) Read the Status Register 0 1 1 X X X X

-if bit 1 is set, the Tx is ready for the next tone, in which case... Write to Transmit Register 0 0 0 0 1 0 1 (send a digit 5)

-if bit 2 is set, a DTMF tone has been received, in which case....

Read the Receive Data Register 0 0 1 X X X X

-if both bits are set... Read the Receive Data Register 0 0 1 X X X X Write to Transmit Data Register 0 0 0 0 1 0 1

NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE DATA IS WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms).

4-44

Figure 16 - Application Hints

Page 24

Absolute Maximum Ratings*

Parameter Symbol Min Max Units

ISO

-CMOS MT8880C/MT8880C-1

1 Power supply voltage VDD-V

2 Voltage on any pin V 3 Current at any pin (Except V

DD andVSS

)10mA 4 Storage temperature T 5 Package power dissipation P

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions - Voltages are with respect to ground (V

Parameter Sym Min Typ

1 Positive power supply V 2 Operating temperature T 3 Crystal clock frequency f

‡ Typical ﬁgures are at 25 °C and for design aid only: not guaranteed and not subject to production testing.

DC Electrical Characteristics

CLK

†

- VSS=0 V.

Characteristics Sym Min Typ

1 2 Operating supply current I 3 Power consumption P 4

5 Low level input voltage

6 Steering threshold voltage V 7

Operating supply voltage V

S U P

High level input voltage

(OSC1)

N P U

(OSC1)

T S

Low level output voltage (OSC2) V

8 High level output voltage

U T

(OSC2) V

9 Output leakage current

(IRQ) I

10 V 11 V 12 13 High level input voltage V 14 Input leakage current I

15 16 Sink current I 17 18 Sink current I

† Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical ﬁgures are at 25 °C, VDD =5V and for design aid only: not guaranteed and not subject to production testing.

i t

Data

Bus ESt

and

St/Gt

IRQ/

output voltage V

Ref

output resistance R

Ref

Low level input voltage V

Source current I

Sink current I

4.75 5.00 5.25 V

-40 +85 °C

3.575965 3.579545 3.583124 MHz

4.75 5.0 5.25 V

IHO

ILO

OLO

OHO

OL OL

TSt

Ref OR

3.5 V

2.2 2.3 2.5 V VDD=5V

4.9 V

2.4 2.5 2.6 V No load, VDD=5V

2.0 V

-1.4 -6.6 mA VOH=2.4V

2.0 4.0 mA VOL=0.4V

-0.5 -3.0 mA VOH=4.6V 2 4 mA VOL=0.4V

416 mAVOL=0.4V

‡

VSS-0.3 VDD+0.3 V

-65 +150 °C

) unless otherwise stated.

Max Units Test Conditions

7.0 11 mA

57.8 mW

1.5 V

No load

0.1 V No load

VDD=5 V

110µAVOH=2.4 V

1.3 kΩ

0.8 V

10 µAVIN=VSS to V

1000 mW

4-45

Page 25

MT8880C/MT8880C-1 ISO

-CMOS

Electrical Characteristics Gain Setting Ampliﬁer - Voltages are with respect to ground (V

Characteristics Sym Min Typ Max Units Test Conditions

) unless otherwise stated, VSS= 0V.

1 Input leakage current I 2 Input resistance R 3 Input offset voltage V

10 MΩ

100 nA VSS ≤ VIN≤ V

25 mV 4 Power supply rejection PSRR 50 dB 1 kHz 5 Common mode rejection CMRR 40 dB 6 DC open loop voltage gain A

VOL

40 dB CL= 20p 7 Unity gain bandwidth BW 1.0 MHz CL= 20p 8 Output voltage swing V

9 Allowable capacitive load (GS) C

10 Allowable resistive load (GS) R 11 Common mode range V

Figures are for design aid only: not guaranteed and not subject to production testing. Characteristics are over recommended operating conditions unless otherwise stated.

L L

MT8880C-1 AC Electrical Characteristics

0.5 VDD-0.5 V RL ≥ 100 kΩ to V

100 pF PM>40°

50 kΩ VO= 4Vpp

1.0 VDD-1.0 V RL= 50kΩ

†

- Voltages are with respect to ground (VSS) unless otherwise stated.

Characteristics Sym Min Typ Max Units Notes*

Valid input signal levels (each tone of composite

signal) R X

-31 dBm 1,2,3,5,6,9

21.8 mV

RMS

1,2,3,5,6,9

+1 dBm 1,2,3,5,6,9

869 mV

RMS

1,2,3,5,6,9

2 Input Signal Level Reject -37 dBm 1,2,3,5,6,9

10.9 mV

† Characteristics are over recommended temperature and at VDD=5V, using the test circuit shown in Figure 13.

MT8880C AC Electrical Characteristics

Characteristics Sym Min Typ

†

- Voltages are with respect to ground (VSS) unless otherwise stated. ‡

Max Units Notes*

RMS

1,2,3,5,6,9

-29 dBm 1,2,3,5,6,9

Valid Input signal levels

† Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13.

AC Electrical Characteristics

(each tone of composite

signal)

†

- Voltages are with respect to ground (VSS) unless otherwise stated. fC=3.579545 MHz.

Characteristics Sym Min Typ

Positive twist accept 8 dB 2,3,6,9

27.5 mV +1 dBm 1,2,3,5,6,9

869 mV

‡

Max Units Notes*

RMS

1,2,3,5,6,9

2 Negative twist accept 8 dB 2,3,6,9 3 Freq. deviation accept ±1.5%±2Hz 2,3,5,9

4 Freq. deviation reject ±3.5% 2,3,5

5 Third tone tolerance -16 dB 2,3,4,5,9,10 6 Noise tolerance -12 dB 2,3,4,5,7,9,10 7 Dial tone tolerance 22 dB 2,3,4,5,8,9,11

† Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical ﬁgures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing. * See “Notes” following AC Electrical Characteristics Tables.

4-46

Page 26

ISO

-CMOS MT8880C/MT8880C-1

AC Electrical Characteristics†- Call Progress - Voltages are with respect to ground (V

Characteristics Sym Min Typ

1 Lower freq. (ACCEPT) f 2 Upper freq. (ACCEPT) f 3 Lower freq. (REJECT) f 4 Upper freq. (REJECT) f 5 Call progress tone detect level

LA HA LR HR

-30 dBm

‡

Max Units Notes*

320 Hz @ -25 dBm 510 Hz @ -25 dBm 290 Hz @ -25 dBm 540 Hz @ -25 dBm

) unless otherwise stated.

(total power)

† Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical ﬁgures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing * See “Notes” AC Electrical Characteristics Tables

AC Electrical Characteristics

†

- Voltages are with respect to ground (VSS) unless otherwise stated.

Characteristics Sym Min Typ‡Max Units Conditions

1 2 Tone absent detect time t 3 Tone duration accept t 4 Tone duration reject t 5 Interdigit pause accept t 6 Interdigit pause reject t 7 Delay St to b3 t 8 Delay St to RX0-RX

9 10 Tone pause duration t 11 Tone burst duration (extended) t 12 Tone pause duration (extended) t 13 14 Low group output level V 15 Pre-emphasis dB 16 Output distortion (Single Tone) THD -35 dB 25 kHz Bandwidth

17 Frequency deviation f 18 Output load resistance R 19 20 Φ2 high pulse width t 21 Φ2 low pulse width t 22 Φ2 rise and fall time tR,t 23 Address, R/W hold time t 24 Address, R/W setup time (before Φ2) t 25 Data hold time (read) t 26 Φ2 to valid data delay (read) t 27 Data setup time (write) t

Tone present detect time t

R X

Tone burst duration t

T X

High group output level V

T O N E

O U T

Φ2 cycle period t

P U

I N T E R F A C E

DA REC REC

PStb3

PStRX

BST

BSTE

PSE

HOUT

LOUT

D LT

CYC

AH,tRWH

AS,tRWS

DHR DDR

DSW

3 11 14 ms Note 12

0.5 4 8.5 ms Note 12 40 ms User adjustable

20 ms User adjustable

40 ms User adjustable

20 ms User adjustable

13 µs

8 µs 50 52 ms DTMF mode 50 52 ms DTMF mode

100 104 ms Call Progress mode 100 104 ms Call Progress mode

-6.1 -2.1 dBm RL=10kΩ

-8.1 -4.1 dBm RL=10kΩ 2 3 dB RL=10kΩ

RL=10kΩ

±0.7 ±1.5 % fC=3.579545 MHz

10 50 kΩ

250 ns 115 ns 110 ns

25 ns 26 ns 23 ns 22 ns *

100 ns 200 pF load

45 ns

# # # #

4-47

Page 27

MT8880C/MT8880C-1 ISO

-CMOS

AC Electrical Characteristics† (Cont‘d) - Voltages are with respect to ground (V

Characteristics Sym Min Typ

28 Data hold time (write) t 29 Input Capacitance (data bus) C 30 Output Capacitance (IRQ/CP) C 31 32 Clock input rise time t 33 Clock input duty cycle t 34 Clock input duty cycle DC 35 Capacitive load (OSC2) C

† Timing is over recommended temperature & power supply voltages. ‡ Typical ﬁgures are at 25°C and for design aid only: not guaranteed and not subject to production testing. * The data bus output buffers are no longer sourcing or sinking current by t

See Figure 6 regarding guard time adjustment.

NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.

Crystal/clock frequency f

D T

F C

L K

2) Digit sequence consists of all 16 DTMF tones.

3) Tone duration=40 ms. Tone pause=40 ms.

4) Nominal DTMF frequencies are used.

5) Both tones in the composite signal have an equal amplitude.

6) The tone pair is deviated by ±1.5%±2 Hz.

7) Bandwidth limited (3 kHz) Gaussian noise.

8) The precise dial tone frequencies are 350 and 440 Hz (±2%).

9) For an error rate of less than 1 in 10,000.

10) Referenced to the lowest amplitude tone in the DTMF signal.

11) Referenced to the minimum valid accept level.

12) For guard time calculation purposes.

DHW

OUT

C LHCL HLCL

10 ns

3.5759 3.5795 3.5831 MHz

40 50 60 % Ext. clock

DHR

‡

5pF 5pF

Max Units Notes*

110 ns Ext. clock 110 ns Ext. clock

30 pF

) unless otherwise stated.

4-48

Page 28

CYC

ISO

-CMOS MT8880C/MT8880C-1

Φ2

RS0

Figure 17 - Φ2 Pulse

RWS

DDR

DHR

RWH

DATA BUS

Φ2

RS0

R/W

DATA BUS

RWS

Figure 18 - MPU Read Cycle

DSW

Valid Data

RWH

DHW

Figure 19 - MPU Write Cycle

4-49

Page 29



Contents

• DTMF Receiver Development

• Mobile Radio Applications

• Inside The MT8870

• Distributed Control Systems

• DTMF Receiver Application

• Data Communication Using DTMF

Introduction

Application Note

MSAN-108

Applications Of The MT8870

Integrated DTMF Receiver

ISSUE 1 June 1983

frequencies were carefully chosen such that they are not harmonically related and that their intermodulation products result in minimal signalling impairment (Fig. 1a). This scheme allows for 16 unique combinations. Ten of these codes represent the numerals zero through nine, the remaining six (*,#,A,B,C,D) being reserved for special signalling. Most telephone keypads contain ten numeric push buttons plus the asterisk (*) and octothorp (#). The buttons are arranged in a matrix, each selecting its low group tone from its respective row and its high group tone from its respective column (Fig. 1b).

The purpose of this Application Note is to provide information on the operation and application of DTMF Receivers. The MT8870 Integrated DTMF Receiver will be discussed in detail and its use illustrated in the application examples which follow.

More than 25 years ago the need for an improved method for transferring dialling information through the telephone network was recognized. The traditional method, Dial pulse signalling, was not only slow, suffering severe distortion over long wire loops, but required a DC path through the communications channel. A signalling scheme was developed utilizing voice frequency tones and implemented as a very reliable alternative to pulse dialling. This scheme is known as DTMF (Dual Tone MultiFrequency), Touch-Tone™ or simply, tone dialling. As its acronym suggests, a valid DTMF signal is the sum of two tones, one from a low group (697-941Hz) and one from a high group (1209-1633Hz) with each group containing four individual tones. The tone

Tones generated from a telephone typically have -2 dB twist (pre-emphasis) applied to compensate for high frequency

AMPLITUDE

roll off along the telephone line.

The DTMF coding scheme ensures that each signal contains one and only one component from each of the high and low groups. This signiﬁcantly simpliﬁes decoding because the composite DTMF signal may be separated with bandpass ﬁlters, into its two single frequency components each of which may be handled individually. As a result DTMF coding has proven to provide a ﬂexible signalling scheme of excellent reliability, hence motivating innovative and competitive decoder design.

Development

Early DTMF decoders (receivers) utilized banks of bandpass ﬁlters making them somewhat cumbersome and expensive to implement. This generally restricted their application to central ofﬁces (telephone exchanges).

The ﬁrst generation receiver typically used LC ﬁlters, active ﬁlters and/or phase locked loop techniques to

2 dB

685 709 756 784 837 867 925 957 1189

697 770 852 941

Standard DTMF frequency spectrum ± (1.5% + 2 Hz). Second harmonics of the low group (possibly created due to a non-linear channel) fall within the passband of the high group (Indicated by A,B,C,D). This is a potential source of interference.

ABCD

1314 1453 1607

1358 1501 16591229

1209 1336 1477 1633

Figure 1a - The Dual Tone Multifrequency (DTMF) Spectrum

f (Hz)

logarithmic

A-49

Page 30

MSAN-108 Application Note

HIGH GROUP TONES

H4 =

H3 =

H2 =

L1 = 697 Hz

L2 = 770 Hz

H1 =

1209

Hz 1

1336 Hz

1477 Hz

1633 Hz

LEGEND :

DTMF signal not available on a standard pushbutton telephone keypad

LOW GROUP

TONES

Telephone DTMF keypad matrix. Column H reserved for special signalling.

L3 = 852 Hz

L4 = 941 Hz

Figure 1b - The Dual Tone Multifrequency (DTMF) Keypad

LOOP CURRENT

DETECT CIRCUIT

MT8870

DTMF

RECEIVER

is normally not available on a telephone keypad and is

DISCONNECT

RELAY

DECODE

LOGIC

CIRCUIT

RELAY

DRIVER

TO TELEPHONE

& REGULATOR

RINGING

DETECTOR

EXCHANGE

RECTIFIER

FILTER

RESET LOGIC

Block diagram of a toll call restrictor. This could be implemented on a small pc board and installed

in a telephone to disallow long distance calling.

LINE INTERFACE

MT8870

DTMF

RECEIVER

CENTRAL TELEPHONE SWITCHING OFFICE

Block diagram of a simple tome to pulse converter to allow TOUCH-TONE dialing into a step-by-

step or crossbar exchange.

LINE SPLIT RELAY

DISABLE

LOGIC

CONTROL

LOGIC

Figure 2 - Typical DTMF Receiver Applications

A-50

STEP-BY-STEP

EXCHANGE

LINE INTERFACE

MT4325

PULSE

DIALER

Page 31

Application Note MSAN-108

receive and decode DTMF tones. Initial functions were, commonly, phone number decoders and toll call restrictors. A DTMF receiver is also frequently used as a building block in a tone-to-pulse converter which allows Touch-Tone dialling access to mechanical step-by-step and crossbar exchanges (Fig. 2).

The introduction of MOS/LSI digital techniques brought about the second generation of tone receiver development. These devices were used to digitally decode the two discrete tones that result from decomposition of the composite signal. Two analog bandpass ﬁlters were used to perform the decomposition.

Totally self-contained receivers implemented in thick ﬁlm hybrid technology depicted the start of third generation devices. Typically, they also used analog active ﬁlters to bandsplit the composite signal and MOS digital devices to decode the tones.

The development of silicon-implemented switched capacitor sampled ﬁlters marked the birth of the fourth and current generation of DTMF receiver technology. Initially single chip bandpass ﬁlters were combined with currently available decoders enabling a two chip receiver design. A further advance in integration has merged both functions onto a single chip allowing DTMF receivers to be realized in minimal space at a low cost.

The second and third generation technologies saw a tendency to shift complexity away from the analog circuitry towards the digital LSI circuitry in order to reduce the complexity of analog ﬁlters and their inherent problems. Now that the ﬁlters themselves can be implemented in silicon, the distribution of complexity becomes more a function of performance and silicon real estate.

Inside The MT8870

signal, still in its composite form, is then split into its individual high and low frequency components by two sixth order switched capacitor and pass ﬁlters. Each component tone is then smoothed by an output ﬁlter and squared up by a hard limiting comparator.

The two resulting rectangular waves are applied to digital circuitry where a counting algorithm measures and averages their periods. An accurate reference clock is derived from an inexpensive external

3.58MHz colourburst crystal.

The timing diagram (Fig. 4) illustrates the sequence of events which follow digital detection of a DTMF tone pair. Upon recognition of a valid frequency from each tone group the Early Steering (ESt) output is raised. The time required to detect the presence of two valid tones, tDP, is a function of the decode algorithm, the tone frequency and the previous state of the decode logic. ESt indicates that two tones of proper frequency have been detected and initiates an RC timing circuit. If both tones are present for the minimum guard time, t

, which is determined by

GTP

the external RC network, the DTMF signal is decoded and the resulting data (Table 1) is latched in the output register. The Delayed Steering (StD) output is raised and indicates that new data is available. The time required to receive a valid DTMF signal, t

, is equal to the sum of tDP andt

REC

LOW

697 1209 1 1 0001 697 1336 2 1 0010 697 1477 3 1 0011 770 1209 4 1 0100 770 1336 5 1 0101 770 1477 6 1 0110 852 1209 7 1 0111 852 1336 8 1 1000 852 1477 9 1 1001 941 1209 0 1 1010 941 1336 * 1 1011 941 1477 # 1 1100 697 1633 A 1 1101 770 1633 B 1 1110 852 1633 C 1 1111 941 1633 D 1 0000

HIGH

- - ANY 0 ZZZZ

KEY TOE Q4Q3Q2Q

GTP

The MT8870 is a state of the art single chip DTMF receiver incorporating switched capacitor ﬁlter technology and an advanced digital counting/ averaging algorithm for period measurement. The block diagram (Fig. 3) illustrates the internal workings of this device.

To aid design ﬂexibility, the DTMF input signal is ﬁrst buffered by an input op-amp which allows adjustment of gain and choice of input conﬁguration. The input stage is followed by a low pass continuous RC active ﬁlter which performs an antialiasing function. Dial tone at 350 and 440Hz is then rejected by a third order switched capacitor notch ﬁlter. The

Table 1. MT8870 Output Truth Table

0=LOGIC LOW 1=LOGIC HIGH Z=HIGH IMPEDANCE Output truth table. Note that key "0" is output as "1010 (ie:10

" corresponding to standard telephony coding.

10)

A simpliﬁed circuit diagram (Fig. 5) illustrates how the chip’s steering circuit drives the external RC network to generate guard times. Pin 17, St/GT (Steering/Guard Time), is a bidirectional signal pin which controls StD, the output latches, and resets the timing circuit. When St/GT is in its input mode (St function) both Q1and Q2 are turned off and the voltage level at St/GT is compared to the steering threshold voltage V above V

will switch the comparator’s output from

TSt

A transition from below to

TSt

A-51

Page 32

MSAN-108 Application Note

MT8870

HIGH

FILTER

GROUP

BANDPASS

CODE

DIGITAL

ORDER

SWITCHED

CON-

CAPACITOR

AND

VERTER

DETECT

OUTPUT

LATCHES

CIRCUIT

LOW

GROUP

ORDER

FILTER

BANDPASS

SWITCHED

STEERING LOGIC

CAPACITOR

TOE

StD

ESt

St/GT

VDD

CHIP BIAS/POWER

VSS

BIAS

VDD

DIAL TONE

CHIP REF. VOLTAGE

ANTI-

CIRCUIT

VREF

INPUT

FILTER

350/440 Hz

FILTER

ALIASING

IN-

SIGNAL

ORDER

SW. CAP.

NOTCHES

ORDER

CONT. RC

IN+

CHIP

CLOCK

Figure 3 - MT8870 Functional Block Diagram

OSC2

External guard time, input, and clock components (dashed) are included for clarity.

OSC1

A-52

Page 33

Application Note MSAN-108

low to high strobing new data into the output latches, and raising the StD output. As long as an input level above V

is maintained StD will remain high

TSt

indicating the presence of a valid DTMF signal.

Initially, when no valid tone-pairs are present, capacitor C is fully charged applying a low voltage to St/GT. This causes a low at the comparator’s output and since ESt is also low, Q2 turns on ensuring that C is completely charged. In this condition St/GT is in its output mode (GT function). When a valid tonepair is received ESt is raised turning off Q2 which puts St/GT in its high impedance input mode and allows C to discharge through R. If this condition

EVENTS

ESt

St/GT

Q1-Q

REC

ABC

REC

TONE #n

GTP

DECODED TONE # (n-1)

persists for the tone-present guard time, t voltage at St/GT rises above V

raising StD which

TSt

GTP

, the

indicates reception of a valid DTMF signal. If the tone pair drops out before the duration of t

GTP

, ESt is lowered turning on Q2 which charges C resetting the tone-present guard time.

Once a DTMF signal is recognized as valid both ESt and the comparator output are high. This turns on Q1 which discharges C and initializes the toneabsent guard time, t

. After the DTMF signal is

GTA

removed, ESt is lowered, Q1 turns off placing St/GT in its input mode and C begins to charge through R.

EFG

TONE #n + 1

HIGH IMPEDANCE

# (n + 1)

TSt

QStD

# n

TONE #n + 1

GTA

PSrD

StD

TOE

PTD

PTE

EXPLANATION OF EVENTS

A) TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMIAN LATCHED UNTIL NEXT VALID TONE. D) OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE. E) TONE #n + 1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY HIGH IMPEDANCE). F) ACCEPTABLE DROPOUT OF TONE #n + 1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED. G) END OF TONE #n + 1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT VALID TONE.

EXPLANATION OF SYMBOLS

ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. Q

1-Q4

StD DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS

TOE TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q t

REC

GTP

GTA

DTMF COMPOSITE INPUT SIGNAL.

4-BIT DECODED TONE OUTPUT.

CONSTITUTING A VALID SIGNAL.

MAXIMUM DTMF SIGNAL DURATION NOT DETECED AS VALID MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION MAXIMUM TIME BETWEEN VALID DTMF SIGNALS. MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL. TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS. TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS. GUARD TIME, TONE PRESENT. GUARD TIME, TONE ABSENT.

TO ITS HIGH IMPEDANCE STATE.

1-Q4

Figure 4 - MT8870 Timing Diagram

A-53

Page 34

MSAN-108 Application Note

Valid tone present indication from DIGITAL DETECT circuit.

To OUTPUT LATCHES

DELAY

COMP.

MT8870

(18)

p Q

TSt

St/GT

(17)

n Q

(16)

ESt

A logical HIGH indicates that a valid signal is being receved.

(15)

StD

Simplified steering circuit. Initially ESt is low, C is fully charged applying 0V to St/GT and Q pair ESt is raised turning off Q the comparator output goes high indicating a valid signal, latches the outputs and turns on Q pair is lost ESt goes low Q

turns on resetting the timing circuit.

and Q

Steering circuit truth table. Note that pin 17 (St/GT) acts as both an input and an output depending on the relative states of ESt and the comparator output.

and allowing C to discharge through R which increases the voltae at St/GT. When VTSt is reached

turns off and C charges through R decreasing the voltage at St/GT. When V

STEERING TRUTH TABLE

ESt St(/GT) (St/)GT StD

<V >V <V >V

TSt TSt TSt TSt

0 1 1

0 Z Z 1

0 1 0 1

0 - LOGIC LOW 1 = LOGIC HIGH Z = HIH IMPEDANCE V

TSt

is on. Upon reception of a valid tone

which discharges C. When the tone

= Threshold Voltqae

(typically 1/2 V

is reached StD goes low

TSt

)

Figure 5 - MT8870 Steering And GuardTime Circuit Operation

If the same valid tone-pair does not reappear before t

then the voltage at St/GT falls below V

GTA

TSt

which

resets the timing circuit via Q2 and prepares the

other environments, such as two-way radio, the optimum tone duration and intra-digit times may

differ due to noise considerations. device to receive another signal. If the same valid tone-pair reappears before t on Q1 and discharging C which resets t case StD remains high and the tone dropout is disregarded as noise.

, ESt is raised turning

GTA

. In this

By adding an extra resistor and steering diode (Fig.

6b, 6c) t

GTP

and t

can be set to different values.

GTA

Guard time adjustment allows tailoring of noise

immunity and talk-off performance to meet speciﬁc

system needs. To provide good reliability in a typical telephony environment, a DTMF receiver should be designed to recognize a valid tone-pair greater than 40mS in duration and, to accept as successive digits, tonepairs that are greater than 40mS apart. However in

Talk-off is a measure of errors that occur when the

receiver falsely detects a tone pair due to speech or

background noise simulating a DTMF signal.

Increasing t

improves talk off performance since

GTP

A-54

Page 35

Application Note MSAN-108

MT8870

St/GT

ESt

(a)

ESt

= (RC)In(VDD/V

GTP

= (RC)In(VDD/[VDD-V

GTA

> t

GTP

GTA

= (R1C)In(VDD/V

GTP

= (RPC)In(VDD/[VDD-V

GTA

= R1R2/(R1 + R2)

)

TSt

])

TSt

]

TSt

)

(c)

Figure 6 - Guard Time Circuits

it reduces the probability that speech will maintain DTMF simulation long enough to be considered valid. The trade-off here is decreased noise immunity because dropout (longer than tDA) due to noise pulses will restart t environments, t absent guard time, t

should be decreased. The signal

GTP

GTA

. Therefore, for noisy

GTP

, determines the minimum time allowed between successive DTMF signals. A dropout shorter than t

will be considered noise

GTA

and will not register as a successive valid tone detection. This guards against multiple reception of a single character. Therefore, lengthening t

GTA

will increase noise immunity and tolerance to the presence of an unwanted third tone at the expense of decreasing the maximum signalling rate.

The intricacies of the digital detection algorithm have a signiﬁcant impact on the overall receiver performance. It is here that the initial decision is made to accept the signal as valid or reject it as speech or noise.

MT8870

< t

St/GT

ESt

GTP

= R1R2 (R1 + R2)

GTA

]

GTA

= (RPC)In(VDD/V = (R1C)In(VDD/[VDD-V

(b)

Tone present and absent guard times equal.

Tone present less than tone

TSt

])

absent guard time.

Tone present greater than tone absent guard time.

Note: Typically V

TSt

Many considerations must be taken into account in evaluating criteria for noise rejection. In the telephony environment two sources of noise are predominant. These are, third tone interference, which generally comes from dial tone harmonics, and band-limited white noise . In the MT8870 a complex digital averaging algorithm provides excellent immunity to voice, third tone and noise signals which prevail in a typical voice bandwidth channel.

The algorithm used in the MT8870 combines the best features from two previous generations of Mitel digital decoders with improvements resulting from years of practical use within the telephone environment. The algorithm has evolved through a combination of statistical calculations and empirical

"tweaks" to result in the realization of an extremely

reliable decoder.

Applications

TSt

)

])

TSt

Trade-offs must be made between eliminating talk off errors and eliminating the effects of unwanted third tone signals and noise. These are mutually conﬂicting events. On one hand valid DTMF signals present in noise must be recognized which requires relaxation of the detection criteria. On the other hand, relaxing the detection criteria increases the probability of receiving "hits" due to talk off errors.

The proven reliability of DTMF signalling has created a vast spectrum of possible applications. Until recently, many of these applications were rendered ineffective due to cost or size considerations. Now that a complete DTMF receiver can be designed with merely a single chip and a few external passive components one can take full advantage of a highly developed signalling scheme as a small, costeffective signalling solution.

A-55

Page 36

MSAN-108 Application Note

SOURCE OF DTMF SIGNALS

FUNCTIONAL

TRANSMISSION

MEDIUM

INTERFACE

MT8870

DTMF

RECEIVER

CONTROL

LOGIC

Figure 7 - Modular Approach to DTMF Receiver Systems

INTERFACE

The design of a DTMF receiving system can generally be broken down into three functional blocks (Fig. 7). The ﬁrst consideration is the interface to the transmission medium. This may be as simple as a few passive components to adequately conﬁgure the MT8870’s input stage or as complex as some form of demodulation, multiplexing or analog switching system. The second functional block is the DTMF receiver itself. This is where the receiving system’s parameters can be optimized for the speciﬁc signal conditions delivered from the

"front end" interface. The third, and perhaps most

widely varying function, is the output control logic. This may be as simple as a 4 to 16 line decoder, controlling a speciﬁc function for each DTMF code, or as complex as a full blown computer handling system protocols and adaptively varying the tone receiver’s parameters to adjust for changing signal conditions. Several currently applied and conceptually designed applications are described subsequently but ﬁrst let’s consider the design of a typical input stage.

The input arrangement of the MT8870 provides a differential input op amp as well as a bias source (V

) which is used to bias the inputs at mid-rail.

REF

The output of this op amp is available to provide feedback for gain adjustment.

A typical single ended input conﬁguration having unity gain is shown in Figure 8.

For balanced line applications good common mode rejection is offered by the differential conﬁguration (Fig. 9). In both cases, the inputs are biased to 1/2 VDD by V

. Consider an input stage which will

Ref

interface to a 600Ω balanced line. To reject common mode noise signals, a balanced differential ampliﬁer input provides the solution.

With the input conﬁgured for unity gain the MT8870 will accept maximum signal levels of +1 dBm (into 600Ω). The lowest DTMF frequency that must be detected is approximately 685Hz. Allowing 0.1dB of

A-56

Voltage Gain;

AV =

Input Impedance;

3dB Cutoff Frequency;

1 2

ω)

fc =

= R

S + 1/RC

1 + (1/ωRC)

2πRC

Figure 8 - Single Ended Input Conﬁguration

(3)

(2)

(1)

(4)

IN-

IN+

Ref

MT8870

Page 37

Application Note MSAN-108

attenuation at 685Hz, the required input time constant may be derived from;

M(ω)dB=20 log

+20 log

{(ωτ)

ωτ

1/2

+ 1}

where M(ω)dBis the ampliﬁer gain in decibels

ω is the radian frequency τ is the input time constant

Therefore

-0.1=20 log

(2π)685τ

{[(2π)685τ]

+ 1}

1/2

or τ = 1.52mS

Now, choosing R=220K gives a high input impedance (440K in the passband) and C= τ/R=6.9nF (use a standard value of 10 nF). For unity gain in the passband we choose Rf=R. Ra and Rb are biasing resistors. The choice of Ra is not critical and could be set at, say... 68K. Bias resistor Ra adds a zero to the non-inverting path through the differential ampliﬁer but has no affect on the inverting

path. This zero can be exactly cancelled by the added pole due to Rb if Rb is chosen as;

RaR

Rb =

Ra+R

With appropriate input transient protection, this circuit will provide an excellent bridging interface across a properly terminated telephone line for endto-end or key system applications. Transient protection may be achieved by splitting the input resistors and inserting zener diodes to achieve voltage clamping (Fig. 10). This allows the transient energy to be dissipated in the resistors and diodes and limits the maximum voltage that may appear at the op-amp inputs.

It is important to consider the amount of shunt capacitance introduced by the protection devices. In this case the parasitic capacitances of the zener diodes are in series which reduces their effect. Relatively large shunt capacitances will attenuate the high group frequencies causing the input signal to ”twist“ which degrades receiver performance.

Ra can be chosen to be a convenient value greater than 30KΩ.

Rb selection;

Voltage Gain;

Input Impedance;

3dB Cutoff Frequency;

Rb =

aRf

Ra + R

AV =

MT8870

(3)

(2)

)

fc =

= 2R

1 + (1/

S + 1/RC

RC)

1 2

IN-

(1)

IN+

(4)

Ref

Figure 9 - Differential Input Conﬁguration

A-57

Page 38

MSAN-108 Application Note

Twist" is known as the difference in amplitude between the low and high group tones. It is speciﬁed in dB as:

optics could easily be employed as a highly reliable communications method in a harsh interference infested environment.

TWIST

= 20

log

where VL is the amplitude of the low frequency tone

and VH is the amplitude of the high frequency tone.

Twist is usually caused by the frequency response characteristic of the communication channel. Along a telephone line higher frequencies tend to roll off faster than the lower ones so the line response is usually compensated for by applying pre-emphasis (negative twist) to the originating DTMF signal. In extreme cases the receiver may require compensation. This could be realized with a ﬁlter arrangement utilizing the input op amp.

Any communication path that can pass the human voice spectrum is eligible for DTMF signalling. Therefore a variety of ”front-end“ interfaces may be applicable in a given control system. More commonly used media are copper wire and RF channels. An optical ﬁbre could carry a light beam modulated by DTMF. Although this would incur a large overhead in terms of bandwidth utilization, optical ﬁbres do offer isolation from external electromagnetic interference. For example, if control or data signals must be sent near a high power transmission line environment, strong electric and magnetic ﬁelds could have a devastating effect on signals transmitted over wires. DTMF over ﬁbre-

In modern digital switching equipment the MT8870 can easily be interfaced to a digital PCM line by using a codec as an input interface (Fig. 11). Actually, all that is required for the interface is a PCM decoder. In fact, the output ﬁlter that normally is associated with PCM decoders is not required since the high group DTMF bandpass ﬁlter has an upper cutoff frequency low enough to meet the required roll-off of the PCM ﬁlter.

DTMF In Mobile Radio Applications

DTMF signalling plays an important role in distributed communications systems, such as multiuser mobile radio (Fig. 12). It is a "natural" in the two-way radio environment since it slips neatly into the center of the voice spectrum, has excellent noise immunity and highly integrated methods of implementation are currently available. It is also directly compatible with telephone signalling, simplifying automatic phone patch systems.

Several emergency medical service networks currently use DTMF signals to control radio repeaters. Functions are, typically, mobile identiﬁcation, selection of appropriate repeater links, selection of repeater frequencies, reading of repeater status, and for completing automatic phone patch links.

If available in a system of this type, audio from a long distance communications link (microwave,

0.01 µf

TIP

630 V

0.01 µf

RING

630 V

ZENERS ARE 15V 250mW RESISTORS ARE 1% 1/4 W (unless otherwise stated)

110 KΩ

110 KΩ 1W

Figure 10 - MT8870 Front End Protection Circuit

A-58

110 KΩ

KΩ

220

KΩ

MT8870

Ref

Page 39

Application Note MSAN-108

Vref

analog

FROM DIGITAL

SWITCH

digital input

output

TO MICROPROCESSOR BUS

PCM DECODER

Figure 11 - Interfacing The MT8870 To A Digital PABX Or Central Ofﬁce

satellite, etc.) could be switched, via commands from the user’s DTMF keypad, into the local repeater. This would offer the mobile user a variety of paths for

INTER-

CONNECTING

LINK

COMUNICATIONS

REPEATER

TRANSCEIVER

LOCAL REPEATER

MT8870

DTMF RECEIVER

I.D. DECODE

HORN SWITCH

MT5089

DTMF GENERATOR

AUDIO SWITCHING (MT8804 CROSSPOINT SWITCH)

DTMF KEYPAD

MT8870

DTMF RECEIVER

CALL INDICATOR

MT8870 TONE RECEIVER

communication without the assistance of a human operator.

INTER-

CONNECTING

LINK

USER MOBILE

SYSTEM

MT5089

DTMF GENERATOR

PHONE PATCH

MICROPROCESSOR CONTROL

TO TELEPHONE

EXCHANGE

REPEATER CONTROL SYSTEMUSER MOBILE SYSTEM

Features include selective calling, intercommunity RF link and automatic phone patch.

Figure 12 - DTMF Controlled Radio Repeater

A-59

Page 40

MSAN-108 Application Note

A multi-channel repeater system serving a multitude of user groups may be found to achieve its most effective performance in the "trunked" mode. In this case, one RF channel is reserved for system signalling. System operation could be achieved as follows.

Each mobile plus the repeater system contain a DTMF receiver, DTMF generator and appropriate control logic. Mobiles are assigned individual DTMF I.D. codes and always monitor the signalling channel when idle. An originating mobile automatically sends a DTMF sequence containing its own I.D. and the I.D. of the called party. This is recognized by the repeater control which retransmits the called party’s I.D. The answering mobile returns a DTMF handshake indicating to the repeater control that it is available to accept a call. At this time the repeater control sends a DTMF command sequence to both the originating and answering mobiles which instructs their logic circuits to switch to a speciﬁc, available channel. If all channels are busy the repeater control could send DTMF sequences to put both mobiles on "hold" and add their I.D.’s to a

"channel-request" queue. This arrangement would

allow users to access any available frequency and converse privately instead of being restricted to one assigned channel which is shared among several user groups.

As well as an individual I.D., each mobile belonging to a particular organization could also have a common group I.D. This would allow dispatch messages to be sent to all company mobiles simultaneously. Since mobiles would be under DTMF control, messages could be sent to an unattended vehicle and, at the user’s convenience, displayed on a readout .

Each radio link either established or attempted would result in DTMF I.D. codes being sent to the repeater control. These occurrences could easily be collected by a computer for statistical analysis or billing information. Customers who have defaulted on rental payments could be denied access to the system.

Simpliﬁed block diagrams of the control systems for both the repeater and mobiles are shown in Figures 13 and 14 respectively.

REPEATER RECEIVE

AUDIO PATHS

CH5 CH4 CH3 CH2 CH1

TEST/

PROGRAMMING

KEYPAD

AND DISPLAY

REPEATER TRANSMIT

AUDIO PATHS

CH5 CH4 CH3 CH2 CH1

MT8804

4 x 8

CROSS-

POINT

SWITCH

MT8804

CROSS-

POINT

SWITCH

MT8870

DTMF

RECEIVER

SINGLE CHIP MICROCOMPUTER

4 x 8

MT5089

GENERA-

CONTROL LOGIC OR

DTMF

TOR

STATION

MONITORS

PHONE

PATCH

PERIPHERAL PORT

HOST COMPUTER,

DATA LOGGER,

TO TELEPHONE

EXCHANGE

ETC

A-60

Figure 13 - Block Diagram of Control for "Trunked" Repeater System"

Page 41

Application Note MSAN-108

MOBILE TRANSCEIVER

carrier operated squelch

USER I.D. CODE

STRAPS

RECEIVER FUNCTIONS

mute

SINGLE CHIP MICROPROCESSOR

receive audio

MT8870

DTMF

RECEIVER

CONTROL LOGIC OR

transmit

enable

TRANSMITTER

FUNCTIONS

microphone

offhook

transmit

audio

MT5089

DTMF

GENERATOR

KEYPAD

AND DISPLAY

Figure 14 - Block Diagram of Mobile Radio Control System

Distributed Control Systems

There are many other applications which also fall into the distributed communications/control class. That is, several devices being controlled via a common communications medium whether it be RF, copper wire or optical ﬁbres, etc.

Consider, for example, an existing pair of wires circulating throughout a plant. By connecting DTMF receivers at strategic points along this path one could conceivably control the whole plant from a single DTMF transmitter (Fig. 15). Each DTMF receiver would monitor the common line until its speciﬁc I.D. was received, at which time it would transfer data to its functional control logic.

With some simple logic a circuit can be devised to recognize a sequence of programmed DTMF code. Figure 16 illustrates a method of detecting a DTMF code sequence of arbitrary length, N. The object is to compare N sequential 4-bit DTMF data words to N preprogrammed 4-bit I.D. words. Programming the I.D. code is accomplished by applying the desired logic levels to the inputs of N 4bit bus buffers. This may be achieved with straps as

shown, dipswitches or thumbwheels. Pull-up resistors should be applied to the buffer inputs. Initially, after a RESET has occurred, Q0 of the presettable shift register is set logically high, the remaining outputs are reset. This activates the ﬁrst bus buffer which applies its outputs to the Y inputs of a 4-bit comparator.The ”LAST DIGIT“ latch is reset, the ”ERROR-“ ﬂip-ﬂop and ”VALID DIGIT“ latch are set. These three signals are ANDed indicating a ”nomatch“ condition. When a valid DTMF signal is received its data appears at the comparators ”X“ inputs, a comparison occurs and the result appears at the ”X=Y“ output. After 3.4 µS (typical) Std rises indicating that the MT8870 output data is valid and strobes ”X=Y“ into the ”VALID DIGIT“ latch. The shift register advances one position which enables the next bus buffer. If the result of the comparison was true then the ”VALID DIGIT“ output is high. If all digits of the sequence match then the high output from the shift register “wraps around“ from Q

N-1

to Q0, which strobes the ”LAST DIGIT“ latch high. This activates the three input AND gate indicating a ”match” condition. If non-matching data is received any time during the detection sequence the ”ERROR-“ ﬂip-ﬂop is reset which disables the AND gate until a system ”RESET“ occurs. ”RESET“ may be generated in a variety of ways depending on the

A-61

Page 42

MSAN-108 Application Note

DTMF

SIGNAL

SOURCE

MT8870

DTMF

RECEIVER

MT8870

DTMF

RECEIVER

I.D. DECODE

LOGIC

DRIVER

I.D. DECODE

LOGIC

DRIVER

COMPUTER

VALVE

RECEIVER

Figure 15 - Distributed Control System

MT8870

DTMF

I.D. DECODE

LOGIC

SPRINKLER

DRIVER

ALARM

system design objective. If one DTMF code is reserved exclusively for the ”RESET“ function then the MT8870 outputs can be decoded directly. This requires that the controller send a ”RESET“ command prior to sending an I.D. sequence. Alternatively a ”time-out“ timer, triggered by StD, could serve to generate a system reset if a certain time lapse occurs between received signals. This method places time constraints on the system but eliminates the need to consume a DTMF command for the ”RESET“ function.

The concept of using a common transmission medium for control signalling applies to several possible situations. Plant process control, remote measurement control, selective intercom call systems, institutional intercom systems, two way radio control, pocket pagers and model car or boat remote control, just to mention a few.

Conversely, data could be collected from distributed sources. Implemented on a circulating wire or an RF channel, as illustrated in Figure 17, information could be collected by a central unit which individually polls each monitor to ask for data. Alternatively, the system could be interrupt driven (Fig.18). In this case each monitor, when ready to send data, generates an interrupt request by sending a DTMF I.D. sequence followed by a data stream. Interrupt masking or prioritizing could be achieved from the the central control end by applying DC levels across

a wire pair or sending a pilot tone in an RF system. Remote data collection units would monitor this signal to detect when a higher priority interupt is being handled or the communications channel is busy.

Data Communication Using DTMF

There is a vast array of potential applications for DTMF signalling using the existing telephone network. Considering that there are millions of ready-made data sets installed in convenient locations (i.e. the Touch Tone telephone) remote control and data entry may be performed by users without requiring them to carry around bulky data modems.

Potential applications include:

• home remote control

• remote data entry from any Touch-Tone keypad

• credit card veriﬁcation and inquiry

• salesman order entry

• catalogue store (stock/price returned via voice synthesis)

• stock broker buy/sell/inquire -using stock exchange listing mnemonics

• answering machine message retrieval

• automatic switchboard extension forwarding

A-62

Page 43

Application Note MSAN-108

VALID DIGIT

LATCH

RESET

FLIP-

FLOP

ERROR

MATCH

MT8870

Q Q Q Q

StD

1 2 3 4

COMPARATOR

3Y2Y1Y0

X=Y

4-BIT

3Q2Q1Q0

4-BIT

BUS BUFFER

Y3Y2Y1Y

I.D. DIGIT 0

STRAPS

RESET GENERATED FROM A DEDICATED MT8870 OUTPUT BUS DECODE OR A TIME-OUT TIMER

CK Di

3Q2Q1Q0

4-BIT

BUS BUFFER

Y3Y2Y1Y

I.D. DIGIT 1

STRAPS

N-BIT PRESETTABLE SHIFT REGISTER

... ... ...

... ......

3Q2Q1Q0

4-BIT

BUS BUFFER

Y3Y2Y1Y

I.D. DIGIT N-1

STRAPS

N-1

LOAD

N-1

LATCH

LAST DIGIT

RESET

This circut could be used to detect a valid I.D. number (address) or a "password".

Figure 16 - N-Character Sequence Identiﬁer

A household DTMF remote control system with an optional data port can boast a variety of conveniences (Fig. 19). Remote ON/OFF control may be given to electric appliances such as a slow cooker, exterior lighting and garage heater. An electro-mechanical solenoid operated valve allows remote control of a garden sprinkler. Video buffs could interface to their VCR remote control inputs and record T.V. shows with a few keystrokes of their friend’s telephone. This would enhance the function of timers which are currently available on most VCR’s. Schedule changes or unexpected broadcasts could be captured from any remote

location featuring a Touch-Tone™ phone. Security systems could be controlled and a microphone could be switched in for remote audio monitoring. Interfacing a home computer to the data port makes an excellent family message center. At the remote end messages are entered from a telephone keypad. The computer responds with voice messages generated by a speech synthesizer. In the home, messages to be left are entered via the computer keyboard. Messages to be read may be displayed on the computer monitor or ”played back“ through the speech synthesizer.

A-63

Page 44

MSAN-108 Application Note

MT5089

GENERATOR

RECEIVER

TRANSCEIVER

MT8870

DTMF

AND I.D.

LOGIC

DTMF

MT8870

DTMF

REMOTE

MT5089

DTMF

GENERATOR

CONTROL TRANSCEIVER

RECEIVER

TRANSCEIVER

MT8870

DTMF

AND I.D.

DECODE

LOGIC

REMOTE

MT5089

DTMF

GENERATOR

CENTRAL CONTROL

TRANSCEIVER

MT8870

DTMF

RECEIVER

AND I.D.

DECODE

LOGIC

MICROPROCESSOR

POLLING

ALGORITHM

REMOTE

MT5089

DTMF

GENERATOR

RECEIVER

DECODE

REMOTE DATA

MT8870

DTMF

RECEIVER

COLLECTION

LOGGER

WATER

LEVEL

MONITOR

SIESMIC

MONITOR

Polling system for multiple location remote data collection.

Figure 17 - DTMF Controlled Data Collection

MT5089

DTMF

GENERATOR

DATA

REMOTE MONITOR

LOGIC

INTERFACE

PRIORITY

SIGNAL

DETECTOR

MT5089

DTMF

GENERATOR

WEATHER

STATION

TEMPERATURE

TRANSDUCER

ALARM

SENSOR

PRESSURE

TRANSDUCER

LOGIC

INTERFACE

ALARM

SENSOR

A-64

MT8870

DTMF

RECEIVER

PRIORITY SIGNAL

INTERFACE

REMOTE MONITOR

COMPUTER

PRIORITY

SIGNAL

DETECTOR

Remote monitors send data while the interconnecting pair of wires is clear of other interrupts.

Figure 18 - Interrupt Driven Data Collection System

Page 45

Application Note MSAN-108

YOUR

HOUSE

HOME DTMF

CONTROL

SYSTEM

TOUCH-TONE

PHONE

OPTIONAL

chili

OUTSIDE

FLOOD

LIGHTS

SLOW

COOKER

VIDEO

CASSETTE

RECORDER

Figure 19 - Home DTMF Remote Control System

HOME COMPUTER

WITH VOICE

SYNTHESIZER

ABC

GHI

PRS

POS.4 POS.5 POS.6

(?) (@) (Λ)

POS.1 POS.2 POS.3

(W) (X) (Y)

NUMERAL

TYPICAL KEY

JKL

TUV

OPER

(a)

(9)

ESC ’ ’

DEF

!".

MNO

,;:

WXY

SPACE

ACK=11 CAN=58 CR=19 DC1=37

KEYS "2" THROUGH "9" EACH REPRESENT THREE ALPHABETIC CHARACTERS HENCE HAVE THREE INHERENT "POSITIONS" (POS.1, POS.2, AND POS.3) A PLASTIC OVERLAY CARD ADDS THREE MORE POSITIONS (POS.4, POS.5, AND POS.6) TO KEYS "1" THROUGH "0". * AND # ARE RESERVED EXCLUSIVELY FOR THE SPACE AND RETURN FUNCTIONS.

DEL ( )

#$%

<=>

BEL Q Z

DC2=38 DC3=39 DC4=47 DLE=29

(b)

EM=

ENQ=

EOT= ETB=

BS \ /

*+-

?@Λ

RETURN

ETX=

59 09 04 57

FF= FS=

GS=

07 18 68 69

a) Layout of a standard telephone keypad showing inherent character positions for coding purposes. b) Credit card size overlay expands each keys function by adding three more character positions. The * and # are reserved to send "SPACE" and "RETURN" as single key operations. Each other ASCII code requires two keystrokes. To send a character simply push the button on or over which it appears, then push the numeral corresponding to its position. For example, to send a "T" push ‘8’ followed by ‘1’, to send "%" push ‘5’ followed by ‘6’.

Figure 20 - Using A Pushbutton Phone As A Data Terminal

A-65

Page 46

MSAN-108 Application Note

A scheme for coding ASCII characters using one and two digit DTMF signals is outlined in the appendix. Notice that on a telephone keypad keys 2 through 9 are represented by three alpha-characters as well as a numeral. To send an alpha-character, using this scheme, ﬁrst press the key on which the character appears then press the key corresponding to the position in which the character appears on its key (1, 2 or 3 ). Numerals are sent by touching the desired number followed by a zero. The asterisk (*) and octothorp (#) have been reserved for "space" and

"return" respectively. A plastic overlay the size of a

credit card expands the number of useable

"positions" on each button (Fig. 20). This serves as a

guide for sending other ASCII codes and ﬁts snug into a credit card wallet. ASCII control characters that are not commonly used could be listed at the bottom of the card. This user-friendly algorithm

FROM PHONE

EXCHANGE

ANSWER

RELAY

LINE TERMINATION

2/4 WIRE CONVERTER

eliminates the need to memorize conversion codes and allows signiﬁcant functionality even without the overlay reference.

A simple block diagram shows how this scheme may be implemented for a home DTMF control system (Fig. 21). A ringing voltage detector signals the microprocessor of an incoming call. The microprocessor, after the prescribed number of rings, closes the answer relay engaging the proper terminating impedance. A two-to-four wire converter splits bidirectional audio from the balanced telephone line into separate single ended transmit and receive paths.

Receive audio is then switched to the DTMF receiver through the crosspoint switch. Upon receiving a valid DTMF signal, the microprocessor is alerted by

120V

MAINS

OPTIONAL

FM TRANSMITTER

AUDIO

OUT

RING

DETECTOR

PASSWORD

THUMBWHEELS

OPTIONAL

MICROCOMPUTER

MT8804

CROSS-

POINT

SWITCH

MT8870

DTMF

RECEIVER

LOGIC OR

MICROPROCESSOR

CONTROL

SYSTEM

DATA

PORT

OUTPUT

DRIVERS

TO NEARBY

CONTROLLED

DEVICES

HANDSFREE

INTERCOM

STATION

REMOTE

FM/DTMF

RECEIVER

AND

CONTROL

OUTPUT

DRIVERS

TO REMOTE

CONTROLLED

DEVICES

An FM transmitter could be used to couple control signals for distribution over existing power lines. This would eliminate the need for installing wires between the DTMF control unit and remote controlled devices.

Figure 21 - Block Diagram of Home DTMF Remote Control System

A-66

Page 47

Application Note MSAN-108

the rising edge of StD. The microprocessor then checks for a valid password sequence and decodes subsequent commands. A command can be entered to put the system into remote-control mode. In this case the crosspoint switch is conﬁgured to route DTMF signals into the FM-over-mains transmitter as well as the system tone receiver. Forwarding of control signals is accomplished by applying an FM carrier to the power line. This eliminates the need to string control wires haphazardly about the house. The appropriate device is selected by its unique DTMF I.D. code. The microcomputer keeps track of all device locations and their I.D. codes since it must decide when to supply function outputs to the ”nearby“ devices and when to let the ”remote“ receivers handle the data. Subsequent data is transmitted to a selected device until a ’reset‘ command is entered.

Upon receiving any DTMF signal, answer back tones are returned by the microprocessor to acknowledge valid or invalid operations and to indicate the state of an interrogated device. For example, a low to high tone transition could indicate that a particular device is on, a high to low transition indicating the off state. A command could be entered to put the system in an ’external‘ mode which would allow communications through the data port. A host computer could be connected to this port to broaden the scope of the system.

The resident microprocessor unit contains the software and hardware to control ringing veriﬁcation,

password and command decoding, ans w er back tone generation, audio routing, output function latches and an optional data port. Output drivers buffer the latches and switch relays or SCRs to control peripheral devices.

An inﬁnite variety of devices could be controlled by such a system, the spectrum of which is limited only by the ability to provide appropriate interfacing. This system could also be the heart of a DTMF intercom system allowing intercommunication, "phonepatching", and remote control from varied household locations. This type of system concept is, of course, anything but limited to home use. Many applications can provide conveniences to consumers, salespeople and executives.

For example, a merchant could verify credit card accounts quickly utilizing only a telephone keypad for data entry (Fig. 22). Each credit card company could reserve one or more telephone lines to provide this function, reducing the human effort required. The receiving end system would be required to answer the call, provide a short answer back tone or message, receive and decode the credit card account number, verify it, verify the owner’s name and give a go/no-go authorization. This return data could easily be provided with the aid of a voice synthesizer. An auto-dialler containing appropriate phone numbers could be installed at the merchant end as an added time saver.

CASHIER’S

PHONE

CREDIT CARD COMPANY - AUTO VERIFICATION LINE

CREDIT CARD ACCOUNTING

AUTO

MT8870

DTMF

RECEIVER

VERIFICATION/

AUTHORIZATION

SYTHESIZER

OPTIONAL

AUTO

DIALER

ANSWER/

LINE

TERMINATION

Figure 22 DTMF Data Communications For An Auto Veriﬁcation Line

COMPUTER

ALGORITHM

SPEECH

A-67

Page 48

MSAN-108 Application Note

With a similar arrangement, a travelling salesman could access price, delivery and customer status, enter or delete merchandise orders and retrieve messages all from the comfort of the customer’s ofﬁce (Fig. 23a). A department store could provide shop-by-phone service to its customers using telephone keypad data entry (Fig. 23b). Brokerage ﬁrms, utilizing the stock exchange mnemonic listings could provide trading price information and buy/sell service via telephone keypad entry. A voice synthesizer could provide opening and current trading price, volume of transactions and other pertinent data. A telephone answering system manufacturer could apply this technique, allowing users to access and change outgoing and incoming messages from a Touch-Tone phone.

A PBX manufacturer could offer a feature that relieves the switchboard attendant from unneccesary interaction. A call could be answered automatically and a recording may reply ”Thank you for calling XYZ. Please dial the extension you wish to contact or zero for the switchboard“. If the caller knows the called party’s extension in advance it is not neccesary to wait for the switchboard attendant to

forward the call. The attendant could be notiﬁed to intervene if there is no action by the caller say, ten seconds after the recording ends. This provides a similar function to a ”Direct Inward Dialling“ (DID) trunk but without the additional overhead incurred with renting a block of phone numbers as in the DID case.

Now that a DTMF receiver is so easy and inexpensive to implement there are many simple dedicated uses that become attractive. A useful home and ofﬁce application for DTMF receivers is in a self-contained telephone-line-powered toll call restrictor similar to the block diagram in Fig. 2a. This could be installed in an individual telephone or at the incoming main termination depending on which phone or phones are to be restricted. While disallowing visitors from making unauthorized long distance calls, the owner may still desire access to toll dialling. This could be provided by adding a logic circuit that disables the toll restrictor upon receiving a predetermined sequence of DTMF characters (Fig.

16). In this case, the user must enter his password

before dialling a long distance number.

OUTSIDE SALES

PERSON AT

CUSTOMER’S

TELEPHONE

CONSUMER AT

HOME PHONE

OPTIONAL

AUTO

DIALER

(a)

SALES WAREHOUSE/OFFICE

AUTO

ANSWER/

LINE

TERMINATION

CATALOGUE SHOPPING WAREHOUSE

AUTO

ANSWER/

LINE

TERMINATION

MT8870

DTMF

RECEIVER

MT8870

DTMF

RECEIVER

ORDER ENTRY

COMPUTER

STOCK/PRICE/

DELIVERY

ALGORITHM

SPEECH

SYNTHESIZER

ORDER ENTRY

COMPUTER

STOCK/PRICE/

DELIVERY

ALGORITHM

SPEECH

SYNTHESIZER

A-68

(b)

Figure 23 - Two Applications Of DTMF Data Communications

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Application Note MSAN-108

Conclusion

The applications for DTMF signalling are tremendous and due to innovative technological advances its use is increasingly widespread. DTMF offers highly reliable, cost effective signalling solutions which require no development effort on the user’s part. The advent of single chip receivers has allowed many products that were previously not costeffective to be manufactured in production quantities.

DTMF signalling was originally designed for telephony signalling over voice quality telephone lines. This signalling technique has been applied to a multitude of control and data communications systems. All that is required is a voice quality communication channel with appropriate interfacing. The applications are limited only by one’s imagination.

A-69

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MSAN-108 Application Note

Appendix

ASCII TO DTMF CONVERSION

Partial ASCII coding and conversion to 2 sequential DTMF signals

ASCII HEX DTMF ASCII HEX DTMF ASCII HEX DTMF

ACK 06 11 ! 21 44 A 41 21

BEL 07 01 " 22 45 B 42 22

BS 08 34 # 23 54 C 43 23

CAN 18 58 $ 24 55 D 44 31

CR 0D 19 % 25 56 E 45 32 DC1 11 37 & 26 79 F 46 33 DC2 12 38 ’ 27 16 G 47 41 DC3 13 39 ( 28 25 H 48 42 DC4 14 47 ) 29 26 I 49 43

DEL 7F 24 * 2A 64 J 4A 51 DLE 10 29 + 2B 65 K 4B 52

EM 19 59 ’ 2C 74 L 4C 53 ENQ 05 09 - 2D 66 M 4D 61 EOT 04 08 . 2E 46 N 4E 62 ESC 1B 14 / 2F 36 O 4F 63

ETB 17 57 0 30 00 P 50 71 ETX 03 07 1 31 10 Q 51 02

FF 0C 18 2 32 20 R 52 72 FS 1C 68 3 33 30 S 53 73

GS 1D 69 4 34 40 T 54 81

HT 09 12 5 35 50 U 55 82

LF 0A 13 6 36 60 V 56 83 NAK 15 48 7 37 70 W 57 91 NUL 00 04 8 38 80 X 58 92

RS 1E 77 9 39 90 Y 59 93

S0 0E 27 : 3A 76 Z 5A 03

S1 0F 28 ; 3B 75 [ 5B 87 SOH 01 05 < 3C 84 \ 5C 35

SP 20 * = 3D 85 ] 5D 88

STX 02 06 > 3E 86 ^ 5E 96 SUB 1A 67 ? 3F 94 _ 5F 89 SYN 16 49 @ 40 95 ’ 60 15

US 1F 78 DEL 7F 24

VT 0B 17

A-70

Datasheet MT8870D Specification

Specifications and Main Features

Frequently Asked Questions

User Manual