The MSM7575, developed for advanced digital cordless telephone systems, is a single channel
full duplex CODEC which performs mutual transcoding between the analog voice band signal
and the 64 kbps PCM serial data.
This device performs DTMF tone and several kinds of tone generation, transmit/receive data
mute and gain control, side-tone pass and its gain control, and VOX function.
Using advanced circuit technology, this device operates from a single 3 V power supply and
provides low power consumption.
FEATURES
••
• Single 3 V Power Supply OperationVDD: 2.7 V to ␣ 3.6 V
••
••
• Transmit/Receive Full-Duplex Single Channel Operation
••
••
• Transmit/Receive Synchronous Mode Only
••
••
• PCM Interface Data Format :
••
••
• Serial PCM Transmission Data Rate :64 kbps to 2048 kbps
••
••
• Low Power Consumption
••
Operating Mode : 24 mW Typ. (V
Power-Down Mode :0.03 mW Typ. (V
••
• Two Analog Input Amplifier Stages:Externally Gain Adjustable
••
••
• Analog Output Stage
••
••
• Master Clock Frequency :9.600/19.200 MHz Selectable
••
••
• Transmit/Receive Mute, Transmit/Receive Programmable Gain Control
••
••
• Side Tone Path with Programmable Attenuation(8-step Level Adjustment)
••
••
• Built-in DTMF Tone Generator
••
••
• Built-in Various Ringing Tones Generator
••
••
• Built-in Various Ring Back Tone Generator
••
••
• Control by Serial MCU Interface
••
••
• Built-in VOX Control
••
Transmit side:Voice/Silence Signal Detect
Receive side:Background Noise Generation
••
• Built-in Op-amps and Analog Switches for Various Analog Interfaces.
••
••
• Package:
••
64-pin plastic QFP(QFP64-P-1414-0.80-BK)(Product name : 7575GS-BK)
A-law/µ-law/linear (2's complement) Selectable
= 3.0 V)
DD
= 3.0 V)
DD
Push-pull Drive (direct drive of 350 W␣ + 120 nF)
1/25
2/25
¡ Semiconductor
MSM7575
BLOCK DIAGRAM
AIN2
GSX2
VOXI
PCMSO
Prefilter
+
-
AIN1+
GSX1
AOUT-
BPF
P
/
S
XSYNC
RSYNC
PCMRI
S
/
P
Postfilter
LPF
BCLK
PWI
AOUT+
-1
VFRO
AIN1-
-1
VOXO
Compand
Voice Signal
Detect
A/D
D/A
++
EXCK
PDN/
RESET
MCU Interface
Clock/
Timing
ATT
ATT
ATT
+
-
-
+
SAO
-1
ATT
Expand
VREF
+
RINGC
AVIN
REF1
+
-
+
REF2
+
AIN3-
GSX3
AIN3+
+
AIN4-
GSX4
AIN4+
IO1
IO2
SW1
IO3
IO4
SW2
IO5
IO6
SW3
IO7
IO8
SW4
IO9
IO10
SW5
IO11
SW6
IO12
SW7
IO13
SW8
IO14
SW9
V
DD
V
DD
V
DD
MCK
X1
X2
DEN
DOUT
DIN
TOUT1
TOUT2
TOUT3
SGB
SG
AG
DG
V
DD
Tone GEN.
Back ground
Noise Gen.
To each circuit
¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
MSM7575
VOXO
DOUT
DIN
EXCK
DEN
PCMRI
PCMSO
RSYNC
XSYNC
BCLK
DG
IO1
10
11
12
13
MCKX2NC
64
63
1
2
3
4
5
6
7
8
9
62
NC
61
X1
PDN/RESETNCTOUT3
60
59
58
57
TOUT2
TOUT1
56
55
RINGC
VDD
54
53
REF2
52
REF1
51
AVIN
50
NC
49
48VOXI
47
46
45
44
43
42
41
40
39
38
37
36
AOUT+
AOUT-
PWI
VFRO
SAO
GSX2
AIN2
GSX1
AIN1-
AIN1+
GSX4
AIN4-
AIN4+
14
IO2
15
IO3
16
IO4AIN3+
NC : No connect pin
17
IO5
18
IO6
19
IO7
20
IO8
21
22
23
24
IO9
IO10
IO11
IO12
64-Pin Plastic QFP
25
IO13
26
IO14
27
NC
28
NC
29
NC
30
SGB
31
SG
32
AG
35
34
33
GSX3
AIN3-
3/25
¡ Semiconductor
MSM7575
PIN AND FUNCTIONAL DESCRIPTIONS
AIN1+, AIN1–, AIN2, GSX1, GSX2
Transmit analog input and the output for transmit gain adjustment. The pin AIN1– (AIN2)
connects to the inverting input of the internal transmit amplifier, and the pin AIN1+ connects to
the non-inverting input of the internal transmit amplifier. The pin GSX1 (GSX2) connects to
output of the internal transmit amplifier. Gain adjustment should be referred to Fig. 1.
VFRO, AOUT+, AOUT–, PWI, SAO, RINGC
Used for the receive analog output and the output for receive gain adjustment. VFRO is an
output of the receive filter. AOUT+ and AOUT– are differential analog signal outputs which can
directly drive ZL = 350 W + 120 nF or the 1.2 kW load. Gain adjustment should be referred to Fig.
1.
The ORed signal with the control register data CR4-B5 and the external pin RINGC determines
the output pins (AOUT+ and AOUT- /SAO+ and SAO-) for the speech signal and an acoustic
component of the sounder tone, DTMF tone, R tone, F tone, various kinds of tones at either the
VFRO pin or the SAO pin.
Differential
Analog Input
0.1 mF
Vi
10 mF
+
–
Transmit Gain: V
= (R2/R1) ¥ (R4/R3)
Receive Gain: Vo/V
= 2 ¥ (R6/R5)
= 120 nF
Z
L
+ 350 W
C1
C1R1
C2
V
R1
R3
GSX2
VFRO
O
R2
R4
/Vi
R5
R6
Differential
Analog
Output
R2
AIN1–
AIN1+
GSX1
SG
AIN2
GSX2
VFRO
PWI
AOUT–
AOUT+
–
+
–
+
–
+
–1
V
REF
to ENCODER
SELECT
from
DECODER
from MCU INT.
TOUT1
Sounder Output
Signal
SAO
RINGC
+1
Figure 1 Analog Input/Output Interface
+
–
TOUT2
TOUT3
from MCU INT.
4/25
¡ Semiconductor
MSM7575
TOUT1, TOUT2, TOUT3
These are pins for outputs of the NOR gates whose inputs are the comparator output signal
between the SAO output level and the SG level, and each register signal stored by the MCU
interface.
The each output is NOR-gated with the comparator output and the invented signal of CR1-B7 at
TOUT3, the inverted signal of CR1-B6 at TOUT2, and the inverted signal of CR1-B5 at TOUT1.
AVIN, REF1, REF2
These pins are for inputs of two comparators internal to the device. AVIN is connected to each
non-inverting input of comparator1 and comparator2. REF1 is connected to an inverting input
of comparator1 and REF2 is connected to an inverting input of comparator2. The output of each
comparator is connected to the input of ENOR. The interval analog switch SW1 is ON/OFF
controlled by the output which is the logical OR of the ENOR and the CR5-B7 signal. When CR5B7 is at "0", the SW1 is turned to OFF if AVIN is within the voltage range of REF1 and REF2 and
the SW1 is turned to ON if AVIN is out of the voltage range of REF1 and REF2.
AIN3+, AIN3-, GSX3, AIN4+, AIN4-, GSX4
These pins are for inputs and outputs of the internal op-amps. Refer to BLOCK DIAGRAM for
the connection.
IO1 to IO14
These pins are for inputs and outputs of the internal analog switch. Refer to BLOCK DIAGRAM
and FUNCTIONAL DESCRIPTION for the connection and the control method.
X1, X2
Crystal oscillator connection pins. X2 is for the clock output pin. When a conventional external
clock is used, X1 should be connected to the ground, X2 should be left open, and the clock should
be input to the MCK pin.
For the use of a self-oscilation circut
MSM7575
X1
X2
MCK
For the use of an external clock
MSM7575
X1
X2
MCK
9.6 MHz or
19.2 MHz
9.6 MHz or
19.2 MHz
Figure 2 Connection to a Crystal Oscillator or an External Clock
5/25
¡ Semiconductor
MSM7575
SG, SGB
Analog signal ground output.
The output voltage is about 1.4 V. The bypass capacitors (10 µF in parallel with 0.1 µF ceramic
type) should be put between this pin and AG to get the specified noise characteristics. This
output voltage is 0 V during power-down.
AG
Analog ground.
DG
Digital ground.
This ground is separated from the analog signal ground(AG) in this device. The DG pin must be
kept as close to the AG pin possible on the PCB.
V
DD
+3 V power supply.
PDN/RESET
Power down and reset control input.
“L” level makes the whole chip enter to power down state, and, at the same time, all of control
register data are reset to the initial state. Set this pin to “H” level during normal operating mode.
The power down state is controlled by a logical OR with CR0-B5 of the control register. When
using the pin PDN/RESET for the power down and reset control, CR0-B5 should be set to digital
“0”.
MCK
Master clock input.
The frequency must be 9.6 MHz or 19.2 MHz. The applied clock frequency is selected by the
control register data CR0-B6. The master clock signal is allowed to be asynchronous with BCLK,
XSYNC, and RSYNC.
PCMSO
Transmit PCM data output.
This PCM output signal is output from MSB in synchronization with the rising edge of BCLK or
XSYNC. A pull-up resistor must be connected to this pin, because this output is configuared as
an open drain.
During power down, this output is at high impedance state.
6/25
¡ Semiconductor
MSM7575
PCMRI
Receive PCM data input.
This PCM input signal is shifted on the falling edge of BCLK and input from MSB.
BCLK
Shift clock input for the PCM data (PCMSO, PCMRI).
The frequency is set in the range of 64 kHz to 2048 kHz.
XSYNC
8 kHz synchronous signal input for Transmit PCM data.
This signal should be synchronized with BCLK. XSYNC is used for indicating MSB of the
transmit serial PCM.
Be sure to input the XSYNC signal because it is also used as the input of the timing circuit and
the clock source of the tone generator.
RSYNC
8 kHz synchronous signal input for Receive PCM data.
This signal should be synchronized with BCLK signal. RSYNC is used for indicating the MSB
of the receive serial PCM.
BCLK
XSYNC
PCMSO
RSYNC
PCMRI
MSBLSB
MSBLSB
8kHz
(125ms)
Figure 3 PCM Interface Basic Timing Diagram
7/25
¡ Semiconductor
MSM7575
VOXO
Transmit VOX function signal output.
VOX function is to recognize the presence or absence of the transmit voice signal by detecting the
signal energy. “H” and “L” levels set to this pin correspond to the presence and the absence,
respectively. This result appears also at the register data CR7-B7. The signal energy detect
threshold is set by the control register data CR6-B6, B5.
VOXI
Signal input for receive VOX function.
The “H” level at VOXI indicates the presence of voice signal, the decoder block processes normal
receive signal, and the voice signal appears at analog output pins . The “L” level indicates the
absence of voice signal, the background noise generated in this device is transferred to the analog
output pins. The background noise amplitude is set by the control register CR6. Because this
signal is ORed with the register data CR6-B3, the control register data CR6-B3 should be set to
digital “0”.
Voice Input
GSX2
VOXO
VOXI
Voice Output
VFRO
(Absence)
(Presence)
T
VXON
Presence
Detect
T
VXOFF
Absence
Detect (Hang-over time)
(a) Transmit VOX Function Timing Diagram
(Absence)
(Presence)
(Presence)
(Presence)
Normal Voice Signal
Decoded Time period
Background
Noise
(b) Receive VOX Function (CR6-B3: digital "0") Timing Diagram
Note:VOXO, VOXI function become valid when setting CR6-B7 to digital “1”.
Figure 4 VOX Function
8/25
¡ Semiconductor
(b)
,
MSM7575
DEN , EXCK, DIN, DOUT
Serial control ports for MCU interface. Reading and writing data is performed by an external
MCU through these pins. Total 8 registers with 8 bits are provided on the devices.
DEN is the “Enable” control signal input, EXCK is the data shift clock input, DIN is the address
and data input, and DOUT is the data output from which inverted data of the contents of the
register is output.
Fig.5 shows the input or output timing diagram.
DEN
EXCK
W
A2
DIN
A1A0B7B6B5B4B3B2B1B0
DOUT
DEN
EXCK
DIN
DOUT
R A2A1A0
High Impedance
Figure 5 MCU Interface Input/Output Timing
Register map is shown below.
Name
CR0
CR1
CR2
CR3
CR4
CR5
Address
A2A1A0
000
001
010
011
100
101
B7B6B5B4B3B2B1B0
A/m
SEL
TOUT3
-CONT
TX
ON/OFFTXGAIN2TXGAIN1TXGAIN0
Side Tone
GAIN2
DTMF/
OTHERS
SEL
SW7-
CONT
High Impedance
(a) Write Data Timing Diagram
B7B6B5B4B3B2B1B0
Read Data Timing Diagram
Table-1
Control and Detect Data
MCK
SEL
TOUT2
-CONT
Side Tone
GAIN1
TONE
SEND
SW8-
CONT
PDN
ALL
TOUT1
-CONT
Side Tone
GAIN0
SAO/
VFRO
SW9-
CONT
TONE
ON/OFF
TONE4TONE3TONE2TONE1TONE0
SW5&
SW6-CONT
PDN
TX
————RX PAD
PDN
RX
RX
ON/OFFRXGAIN2RXGAIN1
TONE
GAIN3
SW4-
CONT
—LNR
TONE
GAIN2
SW3-
CONT
TONE
GAIN1
SW2-
CONT
PDN
SAO/AOUT
RX
GAIN0
TONE
GAIN0
SW1-
CONT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CR6
CR7
110
111
VOX
ON/OFFONLVL1
VOX
OUT
TX NOISE
LVL1
ON
LVL0
TX NOISE
LVL0
IN
RX NOISE
LEVEL SEL
OFF
TIME
—————
VOX
RX NOISE
LVL1
RX NOISE
LVL0
R/W
R
R/W : Enable to read/write R : Read only register.
*2 Use the P-message weighted filter
*3 PCMRI input code"11010101"(A-law)
"11111111"(m-law)
*4 0.320 Vrms = 0 dBm0 = –7.7 dBm
*5 Value in ( ) is for C
= 10 pF Pull-up £ 20 kW
Load
Note:All ADPCM coder and decoder characteristics comply with ITU-T Recommendation
G.721.
14/25
¡ Semiconductor
AC Characteristics (DTMF and Other Tones)
Parameter
Frequency Difference
Original (reference)
Tone Signal Level
*6
Relative Level of
DTMF Tones
Symbol
D
D
V
DTMF Tones–7—+7Hz
FT1
Other Tones
FT2
TL
Transmit
TH
RL
Tones
V
V
Receive
V
Tones
RH
DTMFVTH/VTL
Condition
DTMF (Low)
DTMF (High)
and Other Tones
DTMF (Low)
DTMF (High)
and Other Tones
, VRH/V
RL
*6 Not contain the setting value of the programmable gain
2.7 V to 3.6 V, Ta = –25°C to +70°C)
(V
DD =
Min.Typ.Max.Unit
–7—+7Hz
–18
–16
–4
–2
+1dBm0R
–16
–14
–2
0
+2
MSM7575
–14
–12
+2
+3
dBm0
dBm0
0
dBm0
dBm0
AC Characteristics (Programmable Gain Stages)
Parameter
Gain Accuracy
Symbol
D
G
All gain stages, to programmed value–10+1dB
Condition
AC Characteristics (VOX Function)
Parameter
Transmit VOX Detect Time
(Voice signal ON/OFF detect time
Transmit VOX Detect Level
Accuracy
(Threshold Level)
Symbol
t
VXON
t
)
VXOF
D
VX
Condition
OFF Æ ON—5—ms
ON Æ OFF
VOXO,
Fig.4
To the setting of detect level
by CR6-B6, B5.
2.7 V to 3.6 V, Ta = –25°C to +70°C)
(V
DD =
Min.Typ.Max.Unit
(V
2.7 V to 3.6 V, Ta = –25°C to +70°C)
DD =
Min.Typ.Max.Unit
150/310 160/320 170/330ms
–2.5dB
0+2.5
15/25
¡ Semiconductor
TIMING DIAGRAM
Transmit Side PCM Data Interface
MSM7575
BCLK
XSYNC
PCMSO
0
t
XS
12345678910
t
SX
t
XD1
t
t
WS
XD2
MSBLSB
t
SDX
Receive Side PCM Data Interface
BCLK
RSYNC
PCMRI
0
t
RS
12345678910
t
SR
t
DS
t
WS
t
DH
MSB
Figure 6 PCM Data Interface
LSB
t
XD3
16/25
¡ Semiconductor
Serial Port Data Transfer for MCU Interface
DEN
t
M5
EXCK
t
M2
123456
1112
MSM7575
t
M10
DIN
DOUT
t
M1tM3
t
t
M4
M6
t
M7
W/RA2A1A0B7
t
M8
B7
Figure 7 MCU Interface
t
M9
B1B0
B1B0
t
M11
17/25
¡ Semiconductor
MSM7575
FUNCTIONAL DESCRIPTION
Control Registers
(1) CR0 (Basic operating mode)
B7B6B5B4B3B2B1B0
CR0MCK SELPDN ALLPDN TXPDN RX—LNR
Initial Value
A/m SEL
00000000
Note) "Initial": Reset state by PDN/RESET
B7 ...PCM Companding law select:0/µ-law, 1/A-law
B6 ...Master clock frequency select:0/9.600 MHz, 1/19.200 MHz
B5 ...Power down (whole system):0/Power on, 1/Power down
When using this data for power down control, pin PDN/RESET should be set at
“H”level. The control registers are not reset by this signal.
B4 ...Power down (Transmit only):0/Power on, 1/Power down
B3 ...Power down (Receive only including the op-amps of GSX3, GSX4 and comparator): 0/
Power on, 1/Power down
B2 ...Not used
B1 ...PCM interface linear code select:
0/Companding law selected by CR0-B7
1/14-bit Linear code (2's complement) in spite of the value of CR0-B7
B0 ...Power Down for Sounder output amps: (SAO), or Receiver output amp (AOUT, VFRO ):
When this data is set to digital “1”, the circut which is not selected by CR4-B5 are at the
power down state.
When this data is set to digital "0", sounder amplifiers and receiver amplifiers are in the
power-on state.
PDN
SAO/AOUT
18/25
¡ Semiconductor
(2) CR1
B7B6B5B4B3B2B1B0
CR1
Initial Value
TOUT3
–CONT
00000000
TOUT2
–CONT
TOUT1
–CONT
B7 ... TOUT3 control bit :
0/TOUT3 = "0", 1/Enable TOUT3
B6 ... TOUT2 control bit :
0/TOUT2 = "0", 1/Enable TOUT2
B5 ... TOUT1 control bit :
0/TOUT1 = "0", 1/Enable TOUT1
B4 ... Not used
B3 ... Not used
B2 ... Not used
B1 ... Not used
B0 ... Receive side PAD : 1/inserted,12 dB loss
0/no PAD
MSM7575
————RX PAD
19/25
¡ Semiconductor
MSM7575
(3)CR2 (PCM CODEC operational mode setting and transmit/receive gain adjustment)
This programmable gain table should be assigned, not only for transmit/receive voice signal, but
also for the transmitted DTMF and other tones. The transmission of these tone signals are
enabled, by the CR4-B6 data described later, The original (reference) signal amplitude of these
tones are analogically defined as follows.
DTMF high-group-tones and others............... –14 dBm0/Tone
For example, when selecting +8 dB (B6, B5, B4) = (1,1,1) as a transmit gain, each tone signal
amplitude with analogical expression on the pin PCMSO becomes as follows .
DTMF high-group tones and other tones ...... –6 dBm0
Gain setting of side tone (path to receive side from transmit side) and receive side tone is
performed by register CR3.
20/25
¡ Semiconductor
(4) CR3 (Side tone and other tone generator gain setting)
B7B6B5B4B3B2B1B0
CR3
Side. Tone
GAIN2GAIN1GAIN0ON/OFFGAIN3GAIN2GAIN1
Initial Value
Side. Tone Side. ToneTONETONETONETONETONE
00000000
B7, B6, B5 ... Side tone path gain setting, refer to Table-3.
B4 ... Tone generator enable :0/Disable, 1/Enable
B3, B2, B1, B0 ... Tone generator gain adjustment for receive side, refer to Table-4
Table-3 Side Tone Gain Setting Table
MSM7575
GAIN0
Table-4 Receive Tone Generator Gain Setting Table
B3B2B1B0
0000
0001
0010
0011
0100
0101
0110
0111
B7B6B5
000
001
010
011
100
101
110
111
Tone Generator Gain
–36 dB
–34 dB
–32 dB
–30 dB
–28 dB
–26 dB
–24 dB
–22 dB
Side Tone Path Gain
OFF
–21 dB
–19 dB
–17 dB
–15 dB
–13 dB
–11 dB
–9 dB
B3B2B1B0
1000
1001
1010
1011
1100
1101
1110
1111
Tone Generator Gain
–20 dB
–18 dB
–16 dB
–14 dB
–12 dB
–10 dB
–8 dB
–6 dB
The tone generator gain setting table for receive side, shown by Table-4, depends upon the
following reference level.
DTMF high-group tones and others ............ 0 dBm0
For example, when selecting –6 dB (B3, B2, B1, B0) = (1, 1, 1, 1) as a tone generator gain, each DTMF
tone signal amplitude on SAO or VFRO is as follows.
B3 ... Receive VOX function setting :0/Background noise transmit, 1/Voice signal detect
When using this data for control, the pin VOXI should be set at a “L” level.
B2 ... Background noise amplitude setting :0/Automatic, 1/Programmable by B1 and B0
Automatic : The noise is set at the voice signal amplitude at the time when B3
(or VOXI) changes from “1” to digital “0”.
B1, B0 ... (0, 0):No noise
(0, 1):–55 dBm0
(1, 0):–45 dBm0
(1, 1):–35 dBm0
(8) CR7 (Detect register, read only)
B7B6B5B4B3B2B1B0
CR7
Initial
VOX
OUT
000*****
TX NOISE
LVL1
TX NOISE
LVL0
—————
B7 ... Transmit VOX function result :0/Absence, 1/Presence
B6, B5 ... Transmit voiceless level (indicator) :
(0, 0) : below –60 dBm0Note) These outputs are valid only when VOX
(0, 1) : –50 to –60 dBm0function is enabled by CR6-B7.
(1, 0) : –40 to –50 dBm0
(1, 1) : over –40 dBm0
B4 ... Not used
B3 ... Not used
B2 ... Not used
B1 ... Not used
B0 ... Not used
For IC test
*
24/25
¡ Semiconductor
PACKAGE DIMENSIONS
QFP64-P-1414-0.80-BK
Mirror finish
MSM7575
(Unit : mm)
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.87 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
25/25
E2Y0002-29-62
NOTICE
1.The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9.MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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