Datasheet MSM7542TS-K, MSM7542GS-K, MSM7541RS, MSM7542RS, MSM7541TS-K Datasheet (OKI)

E2U0014-28-81

¡ Semiconductor MSM7541/7542

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7541/7542

Single Rail CODEC

GENERAL DESCRIPTION

The MSM7541 and MSM7542 are single-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices are
optimized for telephone terminals in digital wireless systems.
The MSM7541 and MSM7542 use newly designed operational amplifiers to maintain small
current deviations caused by power voltage fluctuations.
The devices use the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal, which is of a differential type, directly drives a piezoelectric type
handset receiver.

FEATURES

• Single power supply: +3.0 V to +3.8 V

• Low power consumption
Operating mode: 23 mW Typ. VDD = 3.3 V
Power save mode: 1 mW Typ. VDD = 3.3 V
Power down mode: 0.04 mW Typ. VDD = 3.3 V

• ITU-T Companding law

MSM7541: m-law
MSM7542: A-law

• Built-in PLL eliminates a master clock

• Serial data rate: 64/128/256/512/1024/2048 kHz

96/192/384/768/1536/1544/200 kHz

• Adjustable transmit gain

• Adjustable receive gain

• Built-in reference voltage supply

• Built-in analog loop back test mode

• Differential type analog output. Directly drives a piezoelectric type receiver equivalent to 1.2
kW + 55 nF

• Package options:
20-pin plastic skinny DIP (DIP20-P-300-2.54-S1) (Product name : MSM7541RS)

(Product name : MSM7542RS)

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7541GS-K)

(Product name : MSM7542GS-K)

26-pin plastic TSOP (TSOPII26/20-P-300-1.27-K) (Product name : MSM7541TS-K)

(Product name : MSM7542TS-K)

1/20

¡ Semiconductor MSM7541/7542

BLOCK DIAGRAM

AIN+
AIN–

GSX

TMC

VFRO

PWI

AOUT–

AOUT+

+
–

–
+

SG

–
+

SG

–
+

SG

RC

Active

SG

Power
Down

BPF

(8th)

LPF

(5th)

AD

Conv.

Auto
Zero

DA

Conv.

PWD

Logic

Voltage

Ref.

Transmit

Controller

PLL

R–TIM

Receive

Controller

SG

Signal

Ground

PCMOUT
XSYNC
BCLOCK

RSYNC
PCMIN

PDN
V

DD

AG
DG

SGC
SG

2/20

¡ Semiconductor MSM7541/7542

y

PIN CONFIGURATION (TOP VIEW)

SG

AOUT+

AOUT–

PWI

VFRO

V

DD

DG

PDN

RSYNC

PCMIN

1

2

3

4

5

6

7

8

9

20

19

18

17

16

15

14

13

12

10 11

SGC

AIN+

AIN–

GSX

TMC

NC

AG

BCLOCK

XSYNC

PCMOUT

SG

AOUT+

AOUT–

NC

PWI

VFRO

NC

V

DD

DG

PDN

RSYNC

PCMIN

1

2

3

4

5

6

7

8

9

10

11

24

23

22

21

20

19

18

17

16

15

14

12 13

NC : No connect pin

24-Pin Plastic SOP

SGC

AIN+

AIN–

GSX

NC

TMC

NC

NC

AG

BCLOCK

XSYNC

PCMOUT

SG

AOUT+

AOUT–

PWI

VFRO

V

DD

DG

PDN

RSYNC

PCMIN

1

2

3

4

5

9

10

11

12

26

25

24

23

22

18

17

16

15

13 14

NC : No connect pin

26-Pin Plastic TSOP

SGC

AIN+

AIN–

GSX

TMC

NC

AG

BCLOCK

XSYNC

PCMOUT

NC : No connect pin

20-Pin Plastic Skinn

DIP

3/20

¡ Semiconductor MSM7541/7542

PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN–, GSX

Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.

1) Inverting input type

AG

C1

Analog input

R1

2) Non inverting input type

C2

Analog input

R5

R3

R2

R4

GSX
AIN–
AIN+
SG

AIN+
AIN–
GSX

SG

R1 : variable

–
+

+
–

R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)

Gain = R2/R1 £ 10

R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)

Gain = 1 + R4 / R3 £ 10

Analog signal ground.

VFRO

Receive filter output.
The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage (SG)
when the digital signal of +3 dBmO is input to PCMIN and can drive a load of 20 kW or more.
For driving a load of 20 kW or less, the output signal of AOUT+ and AOUT– is available.
To apply the output signal of AOUT+ and AOUT– for driving, connect a resistor of 20 kW or more
between the pins VFRO and PWI.
When adding the frequency characteristics to the receive signal, refer to the application example.
During power saving or power down mode, the output of VFRO is at the voltage level of AG.

4/20

¡ Semiconductor MSM7541/7542

PWI, AOUT+, AOUT–

PWI is connected to the inverting input of the receive driver. The receive driver output is
connected to the AOUT– pin. Therefore, the receive level can be adjusted with the pins VFRO,
PWI, and AOUT–. When the PWI pin is not used, connect the PWI pin to the AOUT– pin, and
leave open the pins AOUT– and AOUT+. The output of AOUT+ is inverted with respect to the
output of AOUT–. Since the signal from which provides differential drives of an impedance of

1.2 kW + 55 nF, these outputs can directly be connected to a receiver of handset using a

piezoelectric earphone. Refer to the application example.

VI

Receive Filter

–
+

SG

–
+

SG

VFRO

PWI

AOUT–

AOUT+

R6

R7

ZLVO

R6 > 20 kW
ZL ≥ 2.4 kW

Gain = VO/VI = 2 ¥ R7/R6 £ 2

During power saving and power down modes, the outputs of AOUT+ and AOUT– are in a high
impedance state.

The electrical driving capability of the AOUT– pin and AOUT+ pin is ±1.3 V maximum. The

output load resistor has a minimum value of 1.2 kW.

If an output amplitude less than ±1.3 V is allowed, these outputs can drive a load resistance less

than that described above.
For more details, refer to SINGLE POWER SUPPLY PCM CODEC APPLICATION NOTE.

V

DD

Power supply for +3.0 V to +3.8 V. (Typically 3.3 V)

PCMIN

PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLOCK signal.
The data rate of the PCM signal is equal to the frequency of the BCLOCK signal.
The PCM signal is shifted at a falling edge of the BCLOCK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLOCK

Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.

5/20

¡ Semiconductor MSM7541/7542

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be

synchronized in phase with the BCLOCK. The frequency should be 8 kHz ±50 ppm to guarantee

the AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLOCK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.

TMC

Control signal input for mode selection.
This pin select the normal operating mode or the analog loop-back mode.
In the analog loop-back mode, the receive filter output is connected to the transmit filter input
and the digital signal input to the PCMIN pin is converted from a digital to an analog signal (D/
A conversion). Next, the analog signal is converted to a digital signal (A/D conversion) through
the receive filter and transmit filter. The result is output to the PCMOUT pin.
When in the analog loop-back mode, the VFRO pin outputs the SG level. (signal ground)

TMC Input

< 0.16 ¥ V

> 0.45 ¥ V

DD

DD

Mode

Normal operation

Analog loop-back

6/20

¡ Semiconductor MSM7541/7542

DG

Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.

PDN

Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLOCK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between
BCLOCK and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down modes.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7542(A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

+0

–0

–Full scale

PCMIN/PCMOUT

MSM7541 (m-law)

MSD

1000 0000

1111 1111

0111 1111

0000 0000

MSM7542 (A-law)

MSD

1010 1010

1101 0101

0101 0101

0010 1010

7/20

¡ Semiconductor MSM7541/7542

SG

Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.

The output drive current capability is ±200 mA.

This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power saving or power down modes.

SGC

Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.

8/20

¡ Semiconductor MSM7541/7542

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Storage Temperature

Symbol

V

DD

V

AIN

V

DIN

T

STG

Condition

—

—

—

—

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage

Symbol

V

Operating Temperature Ta

Analog Input Voltage

Digital Input High Voltage

Digital Input Low Voltage

Clock Frequency

Sync Pulse Frequency

Clock Duty Ratio

Digital Input Rise Time

Digital Input Fall Time

Transmit Sync Pulse Setting Time

Receive Sync Pulse Setting Time

Sync Pulse Width

PCMIN Set-up Time

PCMIN Hold Time

V

AIN

V

V

F

F

D

t

t

t

XS

t

SX

t

RS

t

SR

t

WS

t

DS

t

DH

R

Digital Output Load

C

Analog Input Allowable DC Offset

Allowable Jitter Width

V

—

Voltage must be fixed

DD

Connect AIN– and GSX

IH

XSYNC, RSYNC, BCLOCK,

PCMIN, PDN, TMC

IL

BCLOCK

C

XSYNC, RSYNC

S

BCLOCK

C

XSYNC, RSYNC, BCLOCK,

Ir

PCMIN, PDN, TMC

If

BCLOCKÆXSYNC, See Timing Diagram

XSYNCÆBCLOCK, See Timing Diagram

BCLOCKÆRSYNC, See Timing Diagram

RSYNCÆBCLOCK, See Timing Diagram

XSYNC, RSYNC

Pull-up resistor

DL

DL

Transmit gain stage, Gain = 1

off

Transmit gain stage, Gain = 10

XSYNC, RSYNC, BCLOCK

Condition

—

—

—

—

Rating

0 to 7

–0.3 to V

–0.3 to V

DD

DD

+ 0.3

+ 0.3

–55 to +150

Min. Typ. Max. Unit

3.0

3.3

3.8

–30 +25 +85

—

0.45 ¥ V

0

DD

—

—

—

1.4

V

DD

0.16 ¥ V

DD

64, 128, 256, 512, 1024,

2048, 96, 192, 384, 768,

1536, 1544, 200

6.0

40

—

—

100

100

100

100

1 BCLK

100

100

0.5

—

–100

–10

—

8.0

50

—

—

—

—

—

—

—

—

—

—

—

—

—

—

10.0

60

50

50

—

—

—

—

100

—

—

—

100

+100

+10

500

Unit

V

V

V

°C

V

°C

V

PP

V

V

kHz

kHz

%

ns

ns

ns

ns

ns

ns

ms

ns

ns

kW

pF

mV

mV

ns

9/20

¡ Semiconductor MSM7541/7542

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

= 3.0 V to 3.8 V, Ta = –30°C to +85°C)

(V

DD

Parameter

Power Supply Current

Symbol

I

DD1

I

DD4

I

DD2

Condition

V

= 3.8 V

Operating mode

V

DD

DD

= 3.3 V

Power-save mode, PDN = 1,

XSYNC or BCLOCK Æ OFF

Min.

—

—

—

Typ.

10.0

7.0

0.3

Max.

12.0

9.0

1.0

Unit

mA

mA

mA

Input High Voltage

Input Low Voltage

High Level Input Leakage Current

Low Level Input Leakage Current

Digital Output Low Voltage

Digital Output Leakage Current

Input Capacitance

Power-down mode, PDN = 0

I

DD3

V

IH

V

IL

I

IH

I

IL

Pull-up resistance > 500 W

V

OL

I

O

C

IN

—

5

50

mA

0.45 ¥

—

V

—

DD

V

DD

V

0.16 ¥

—

—

—

—

0.0

—

—

0.0

—

—

—

—

0.2

—

V

2.0

0.5

0.4

10

DD

V

mA

mA

V

mA

— —5—pF

10/20

¡ Semiconductor MSM7541/7542

Transmit Analog Interface Characteristics

(V

= 3.0 V to 3.8 V, Ta = –30°C to +85°C)

DD

Parameter

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

Symbol

R

INX

R

LGX

C

LGX

V

OGX

V

OSGX

Condition Min. Typ. Max. Unit

AIN+, AIN–

GSX with respect to SG

Gain = 1

10

20

—

–0.7

–20

—

—

—

—

—

—

—

50

+0.7

+20

MW

kW

pF

V

mV

Receive Analog Interface Characteristics

= 3.0 V to 3.8 V, Ta = –30°C to +85°C)

(V

DD

Parameter

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

Symbol

R

INPW

R

LVF

R

LAO

C

LVF

C

LAO

V

OVF

V

OAO

V

OSVF

V

OSAO

PWI 10

VFRO with respect to SG

AOUT+, AOUT– (each) with

respect to SG

VFRO

AOUT+, AOUT–

VFRO, R

respect to SG

AOUT+, AOUT–, R

with respect to SG

VFRO with respect to SG

AOUT+, AOUT–, Gain = 1 with

respect to SG

Condition Min. Typ. Max. Unit

= 20 kW with

L

= 1.2 kW

L

20

1.2

—

—

–1.0

–1.3

–100

–100

—

—

—

—

—

—

—

—

—

—

—

—

100

50

+1.0

+1.3

+100

+100

MW

kW

kW

pF

pF

mV

mV

V

V

11/20

¡ Semiconductor MSM7541/7542

AC Characteristics

(V

= 3.0 V to 3.8 V, Ta = –30°C to +85°C)

DD

Parameter

Transmit Frequency Response

Receive Frequency Response

Transmit Signal to Distortion Ratio 1020 dB

Receive Signal to Distortion Ratio 1020 dB

Transmit Gain Tracking

Receive Gain Tracking

Symbol

Loss T1

Loss T2

Loss T3

Loss T4

Loss T5

Loss T6

Loss R1

Loss R2

Loss R3

Loss R4

Loss R5

SD T1 35 43 —3

SD T2 35 42 —0

SD T3 35 39 —–30

SD T4 28 30.5 —–40

SD T5 23 25 —–45

SD R1 36 43 —3

SD R2 36 41 —0

SD R3 36 41 —–30

SD R4 30 33 —–40

SD R5 24 27 —–45

GT T1 –0.2 0 +0.2

GT T2 Reference

GT T3 1020 –0.2 –0.02 +0.2 dB–40

GT T4 –0.5 +0.2 +0.5

GT T5 –1.2 +0.4 +1.2

GT R1 –0.2 0 +0.2

GT R2 Reference

GT R3 1020 –0.2 –0.06 +0.2 dB

GT R4 –1.0 –0.10 +1.0

GT R5 –1.5 –0.20 +1.5

Freq.

(Hz)

300 –0.15 +0.1 +0.20 dB

1020 Reference dB

2020 –0.15 — +0.20 dB

3000 –0.15 — +0.20 dB

3400 0 — 0.80 dB

300 –0.15 — +0.20 dB

1020 Reference dB

2020 –0.15 — +0.20 dB0

3000 –0.15 — +0.20 dB

3400 0.0 — 0.80 dB

Level

(dBm0)

60 20 26 — dB

–10

–50

–55

–10

–40

–50

–55

0

3

3

Condition

*1

*1

Min. Typ. Max. Unit

*1 Psophometric filter is used

12/20

¡ Semiconductor MSM7541/7542

AC Characteristics (Continued)

(V

= 3.0 V to 3.8 V, Ta = –30°C to +85°C)

DD

Parameter

Idle Channel Noise

Absolute Level (Initial Difference)

Absolute Level

(Deviation of Temperature and Power)

Absolute Delay

Transmit Group Delay

Receive Group Delay

Crosstalk Attenuation

Symbol

Freq.

(Hz)

Level

(dBm0)

Condition

Min. Typ. Max. Unit

AIN = SG

Nidle T

— — –70 –68

—

*1

Nidle R

AV T 0.338 0.35 0.362

— –76

—

V

DD

*1 *2

= 3.3 V

— –74

Ta = 25°C

AV R 0.483 0.50 0.518

1020

0

AV Tt –0.2 — +0.2

V

DD

*3

= +3 to

3.8 V

Ta = –30

AV Rt –0.2 — +0.2

to +85°C

*3

A to A

Td 1020 — — 0.60 ms0

BCLOCK

= 64 kHz

tgd T1

tgd T2

tgd T3

tgd T4

tgd T5

tgd R1

tgd R2

tgd R3

tgd R4

tgd R5

CR T 7585—

500

600

1000

2600

2800

500

600

1000

2600

2800

*4

*4

TRANS Æ RECV

— 0.19 0.75

— 0.11 0.35

— 0.02 0.1250

— 0.05 0.125

— 0.75

0.07

— 0.00 0.75

— 0.35

0.00

— 0.00 0.125 ms0

— 0.09 0.125

— 0.12 0.75

1020 dB0

CR R 70

RECV Æ TRANS

65 —

dBmOp

Vrms

dB

dB

ms

*1 Psophometric filter is used
*2 Input "0" code to PCMIN
*3 AVR is defined at VFRO output
*4 Minimum value of the group delay distortion

13/20

¡ Semiconductor MSM7541/7542

AC Characteristics (Continued)

(V

= 3.0 V to 3.8 V, Ta = –30°C to +85°C)

DD

Parameter

Symbol

Freq.

(Hz)

(dBm0)

4.6 kHz to

Discrimination 0

DIS

72 kHz

300 to

S

3400

fa = 470

IMD

fb = 320

— 1020 –1.0 — +1.0 dBD-to-D Mode Gain 0

Digital Output Delay Time

PSR T

PSR R

t

SD

t

XD1

t

XD2

t

XD3

0 to

50 kHz

CL = 100 pF + 1 LSTTL

*1 The measurement under idle channel noise

Level

Condition

0 to

4000 Hz

4.6 kHz to

100 kHz

TMC = 1

PCMIN to

PCMOUT

*1

PP

Min. Typ. Max. Unit

30 32 — dB

— –37.5 –35 dBmOOut-of-band Spurious 0

— –52 –35 dBmOIntermodulation Distortion –4 2fa – fb

—30—dBPower Supply Noise Rejection Ratio 50 mV

50 — 200

50 — 200

ns

50 — 200

50 — 200

14/20

¡ Semiconductor MSM7541/7542

TIMING DIAGRAM

PCM Data Input/Output Timing

Transmit Timing

BCLOCK 12345678910

XSYNC

t

XS

t

XD1

t

SX

t

WS

t

SD

t

XD2

t

XD3

PCMOUT D2 D3 D4 D5 D6 D7 D8MSD

When t
When t

£ 1/2 • Fc, the Delay of the MSD bit is defined as t

XS

£ 1/2 • Fc, the Delay of the MSD bit is defined as tSD.

SX

XD1

.

Receive Timing

BCLOCK 12345678910

t

RS

RSYNC

PCMIN D2 D3 D4 D5 D6 D7MSD

t

SR

t

WS

t

DS

t

DH

D8

11

11

15/20

¡ Semiconductor MSM7541/7542

APPLICATION CIRCUIT

Analog interface Digital interface

+3.3 V

Analog input

Analog output

0 V

+3.3 V

0 to 10 W

0.1 mF

+

51 kW

51 kW

0.1 mF

MSM7541/7542

AIN–

GSX

AIN+

SG

AOUT–

PWI

VFRO

SGC

AG

1 mF10 mF

V

DD

PCMOUT

XSYNC

RSYNC

BCLOCK

PCMIN

PDN

TMC

DG

PCM signal output

8 kHz SYNC signal input

BCLOCK input

PCM data input

Power Down control input

Analog loop-back
control input

FREQUENCY CHARACTERISTICS ADJUSTMENT CIRCUIT

Microphone amp

M

Receiver impedance to

1.2 kW + 55 nF

C1

R1

C2

C4

R3 C3

R2

R4

AIN–

GSX

AIN+

SG

AOUT+

AOUT–

PWI

VFRO

Transmit frequency
characteristic
Adjustment determined with
C1, C2, R1, R2.

Receive frequency
characteristic
Adjustment determined with
C3, C4, R3, R4.

16/20

¡ Semiconductor MSM7541/7542

RECOMMENDATIONS FOR ACTUAL DESIGN

• To assure proper electrical characteristics, use bypass capacitors with excellent high frequency

characteristics for the power supply and keep them as close as possible to the device pins.

• Connect the AG pin and the DG pin each other as close as possible. Connect to the system

ground with low impedance.

• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an

IC socket is unavoidable, use the short lead type socket.

• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave

source such as power supply transformers surround the device.

• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch-

up phenomenon when turning the power on.

• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)

power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.

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¡ Semiconductor MSM7541/7542

PACKAGE DIMENSIONS

(Unit : mm)

DIP20-P-300-2.54-S1

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

1.49 TYP.

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¡ Semiconductor MSM7541/7542

(Unit : mm)

SOP24-P-430-1.27-K

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.58 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

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¡ Semiconductor MSM7541/7542

(Unit : mm)

TSOPII26/20-P-300-1.27-K

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.38 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

20/20