Page 1
E2B0026-27-Y2
¡ Semiconductor
This version: Nov. 1997
Previous version: Mar. 1996
MSM6779¡ Semiconductor
MSM6779
160-DOT SEGMENT DRIVER (TCP)
GENERAL DESCRIPTION
The MSM6779 is a LCD dot matrix segment driver. Fabricated in CMOS technology, the device
consists of 160-bit latches I and II, a 160-bit level shifter, and a 4-level driver. The MSM6779
latches the 4-bit parallel display data sent from a microcontroller or a LCD controller to generate
a LCD driving signal. This MSM6779 has a power-save function that sets all the drivers except
one to the low supply current status (IDD SBY).
This driver's 3V-operation allows significant reduction in current consumption, suitable for
battery-driving. The bias voltage to specify a drive level can be supplied externally. The
MSM6779 can be used for various types of LCD panels.
FEATURES
• Logic supply voltage : 2.7 V to 5.5 V
• LCD drive voltage : A wide range from 14 V to 28 V
• Applicable LCD duty : 1/64 to 1/256
• The bias voltage can be supplied externally.
• LCD outputs : 160
• A power-save function to reduce power consumption in a large-screen LCD panel.
• A 4-bit parallel data transfer to reduces its transfer speed to 1/4 of conventional serial transfer,
providing low power consumption.
• Data transfer clock frequency : 6.5 MHz (VDD=4.5 V)
4.0 MHz (VDD=2.7 V)
• 35mm-wide-film TCP
Tin-plating
User area : 8 mm
1/9
Page 2
BLOCK DIAGRAM
MSM6779¡ Semiconductor
V
V
V
V
EEL
DF
DISPOFF
LOAD
D
D
D
D
SHL
O3O2O
1
1L
3L
4L
160-DOT 4-LEVEL DRIVER
O
158
160-bit LEVEL SHIFTER
O
O
160
159
V
1R
V
3R
V
4R
V
EER
V
DD
´
V
EE
V
DD
´
V
SS
160-bit LATCH (II)
0
1
2
3
DATA
CONTROL
160-bit LATCH (I) (4X40)
20-bit SHIFT REGISTER
EIO
V
V
CP
DD
SS
CONTROL
1
CIRCUIT
EIO
2
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Page 3
PIN CONFIGURATION (TOP VIEW)
V
1R
V
3R
V
4R
V
EER
V
DDR
SHL
V
SS
EIO
2
D
0
D
1
D
2
D
3
CP
LOAD
DF
DISPOFF
EIO
1
V
DDL
V
EEL
V
4L
V
3L
V
1L
MSM6779¡ Semiconductor
O
160
O
159
O
158
O
3
O
2
O
1
Note: The drawing shown does not specify the exact outline of the TCP; it only specifies the pin
layout.
3/9
Page 4
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Condition Rating Unit
Supply Voltage (1) V
Supply Voltage (2) V
Input Voltage V
Storage Temperature T
DD
–
STG
DD
*1
V
EE
I
MSM6779¡ Semiconductor
Ta=25˚C –0.3 to 6.5 V
Ta=25˚C 0 to 30 V
Ta=25˚C –0.3 to V
—
–30 to +85 ˚C
0.3 V
DD
+
*1 V1>V3>V4>VEE, V
V1=V1L=V
1R, V3=V3L=V3R
DD≥V1>V3≥VDD
, V4=V4L=V4R, VEE=V
–10 V, V
+10 V≥V
EE
4>VEE
EEL=VEER
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Condition Range Unit
Supply Voltage (1) V
Supply Voltage (2) V
DD
DD
*1
V
–
EE
Operating Temperature Top — –20 to +75 ˚C
*1 V1>V3>V4>VEE, V
DD≥V1>V3≥VDD
–7 V, V
V1=V1L=V1R, V3=V3L=V3R, V4=V4L=V4R, VEE=V
Note: Unlike mold packages, TCP has a low light resistance. Therefore,
they are protected from light.
— 2.7 to 5.5 V
— 14 to 28 V
+7 V≥V
EE
4>VEE
EEL=VEER
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Page 5
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter Symbol Condition Min. Typ. Max. Unit
"H" level Input Voltage V
"L" level Input Voltage V
"H" level Input Current I
"L" level Input Current I
"H" level output Voltage V
"L" level output Voltage V
ON Resistance R
Stand-by Current Consumption I
Current Consumption (1) I
Current Consumption (2) I
Current Consumption (3) I
Input Capacitance C
IH
IL
IH
IL
OHIO
OLIO
ON
DD
SBY
DDfCP
EE
V
I
VI=VDD, VDD=5.5 V
VI=0 V, VDD=5.5 V
VDD–VEE=25 V,
V
I V
f
CP
V
No load
V
No load
fCP=4.0 MHz, VDD=3.0 V
V
No load
fCP=4.0 MHz, VDD=3.0 V
V
No load
f=1 MHz — 5 — pF
*1
—
*1
—
*1
*1
=–0.2 mA, VDD=2.7 V
=0.2 mA, VDD=2.7 V
=2.7 V,
DD
*3 *4
=0.25 V
N–VO
I
=4.0 MHz, VDD=3.0 V
=25 V,
DD–VEE
*5
=4.0 MHz, VDD=3.0 V
=25 V,
DD–VEE
*6
=25 V,
DD–VEE
*7
=25 V,
DD–VEE
*8
MSM6779¡ Semiconductor
2.7 V to 5.5 V, Ta=–20 to +75˚C)
(V
DD
=
0.8 V
DD
— — 0.2 V
—— 1mA
——–1mA
*2
*2
VDD–0.4 — — V
— — 0.4 V
— 1.5 3.0 kW
— — 300 mA
— — 1.5 mA
— — 2.0 mA
— — ±200 mA
——V
V
DD
*1 Applicable to LOAD, CP, D0~D3, EIO1, EIO2, SHL, DF, DISPOFF pins
*2 Applicable to EIO
*3 V
N=VDD–VEE
*4 Applicable to O1~O
*5 Display data 1010.....f
, EIO2 pins
1
, V4=14/16 (VDD–VEE), V3=2/16 (VDD–VEE), VDD=V
pins
160
= 45 Hz, Current from VDD to VSS when the display data is not
DF
1
fetching.
*6 Display data 1010.....f
= 45 Hz, Current from VDD to VSS when the display data is
DF
fetching.
*7 Display data 1010.....f
= 45 Hz, Current from VDD to V
DF
EE
*8 Display data 1010.....fDF = 45 Hz, Current on V1, V3, and V4 pins.
V
1=VIL=VIR
, V3=V3L=V3R, V4=V4L=V4R, VEE=V
EEL=VEER
Note: The above values are quaranteed when TCP is protected from light.
5/9
Page 6
Switching Characteristics
(2.7£VDD<4.5 V, Ta=–20 to +75˚C)
Parameter Symbol Condition Min. Typ. Max. Unit
Clock Frequency f
Clock Pulse Width t
Load Pulse Width t
Clock Pulse Rise/Fall Time t
Data Set-up Time t
Data Hold Time t
Clock Load Time 1 t
Clock Load Time 2 t
Load Clock Time 1 t
Load Clock Time 2 t
Propagation Delay Time t
, EIO2 Set-up Time t
EIO
1
, EIO2 Hold Time t
EIO
1
CP
W1
W2
, t
r
DSU
DHD
CL1
CL2
LC1
LC2
PHL
ESU
EHD
f
DUTY=50%, VDD=2.7 V — — 4.0 MHz
— 90——ns
— 110 — — ns
— ——20ns
— 80——ns
— 65——ns
—0——ns
— 100 — — ns
— 100 — — ns
— 100 — — ns
CL=15 pF — — 380 ns
— 80——ns
— 80——ns
Note: The above values are quaranteed when TCP is protected from light.
MSM6779¡ Semiconductor
D0~D
LOAD
LOAD
CP
CP
t
t
W1
0.8 V
DD
t
DSU
0.8 V
3
t
CL1
0.2 V
DD
DD
1
f
t
W1
0.8 V
DD
0.2 V
DD
t
DHD
t
LC2
t
CL2
0.8 V
DD
0.2 V
DD
t
W2
t
r
2 38 39 40 41
0.2V
DD
0.2 V
0.8 V
0.2 V
t
r
0.8 V
DD
t
f
DD
DD
DD
t
W1
0.8 V
DD
t
LC1
0.8 V
DD
0.2 V
DD
EIO1, EIO2 (Output)
EIO1, EIO2 (Input)
t
PHL
0.2 V
0.2 V
DD
DD
t
ESU
t
EHD
0.2 V
DD
6/9
Page 7
Switching Characteristics
Parameter Symbol Condition Min. Typ. Max. Unit
Clock Frequency f
Clock Pulse Width t
Load Pulse Width t
Clock Pulse Rise/Fall Time t
Data Set-up Time t
Data Hold Time t
Clock Load Time 1 t
Clock Load Time 2 t
Load Clock Time 1 t
Load Clock Time 2 t
Propagation Delay Time t
, EIO2 Set-up Time t
EIO
1
, EIO2 Hold Time t
EIO
1
(4.5£V
CP
W1
W2
, t
r
DSU
DHD
CL1
CL2
LC1
LC2
PHL
ESU
EHD
DUTY=50%, VDD=4.5 V — — 6.5 MHz
— 56——ns
— 70——ns
f
— ——20ns
— 50——ns
— 40——ns
—0——ns
— 65——ns
— 65——ns
— 65——ns
CL=15 pF — — 236 ns
— 50——ns
— 50——ns
£5.5 V, Ta=–20 to +75˚C)
DD
Note: The above values are quaranteed when TCP is protected from light.
MSM6779¡ Semiconductor
D0~D
LOAD
LOAD
CP
CP
t
t
W1
0.8 V
DD
t
DSU
0.8 V
3
t
CL1
0.2 V
DD
DD
1
f
t
W1
0.8 V
DD
0.2 V
DD
t
DHD
t
LC2
t
CL2
0.8 V
DD
0.2 V
DD
t
W2
t
r
2 38 39 40 41
0.2 V
0.2 V
DD
t
r
0.8 V
0.8 V
0.2 V
t
f
DD
DD
DD
DD
t
t
LC1
W1
0.8 V
0.8 V
0.2 V
DD
DD
DD
EIO1, EIO2 (Output)
EIO1, EIO2 (Input)
t
PHL
0.2 V
0.2 V
DD
DD
t
ESU
t
EHD
0.2 V
DD
7/9
Page 8
FUNCTIONAL DESCRIPTION
Pin Descriptions
MSM6779¡ Semiconductor
VDD, V
SS
Power supply for the device. VDD is set to 2.7 V to 5.5 V. VSS is set to 0 V.
V1L, V1R, V3L, V3R, V4L, V4R, V
EEL
, V
EER
Bias power supply for the LCD drive voltages. Power supply should be
V
DD≥V1>V3>V4>VEE
.
DISPOFF
Input for controlling the output level of O1 to O
. The V1 level is output from O1 to O
160
160
pins
during "L" level input. Refer to Truth Table.
DF
Input for LCD drive wave form AC synchronization.
O1~O
160
LCD drive outputs that correspond to each bit of the latch (II). Depending on the combination
of the contents of the latch (display data) and DF signal, one of 4 levels (V1, V3, V4, VEE) is output.
Refer to Truth Table.
CP
Clock pulse input for display data reading. Data is taken into the latch (I) at the falling edge of
the clock pulse.
Use an even number for the clock number per line (the number of the clock pulses during the
period from Load input to the next Load input).
EIO1, EIO
2
Chip Select Signal Input/Output. Input/Output are controlled by the SHL input. If the SHL
input at "L"level,EIO1 is output and EIO2 is input. If the SHL input is at "H" level,EIO1 is input
and EIO2 is output. If the SHL is at "L" level, the first EIO2 is fixed to "L"level,and the following
EIO2 is connected to the preceding EIO1. If the SHL is at "H"level,the first EIO1 is fixed to "L" level,
and the following EIO1 is connected to the preceding EIO2 as shown below.
When SHL is at "L" level
Start data
O
160
EIO
2
EIO
1
EIO
2
EIO
1
EIO
2
End data
O
1
When SHL is at "H" level
End data
O
160
EIO
1
EIO
2
EIO
1
EIO
2
Start data
O
1
EIO
1
8/9
Page 9
MSM6779¡ Semiconductor
D0, D1, D2, D
3
These are display data inputs that input data with clock synchronization. The table below shows
the relationship between the LCD output for the display data and DFs and the LCD.
Display Data DF
LCD drive output
L L OFFNon-selection level (V3)
HL ONSelection level (V1)
L H OFFNon-selection level (V4)
HH ONSelection level (VEE)
LCD
LOAD
This is an input to simultaneously output the display data of one line stored in the latch (I). At
the falling edge, the data in the latch (I) is transferred to the latch (II) end is output.
SHL
Input to select for display data reading direction. Input of "L" level at Vss level fetches data in
the direction from O
direction from O1 to O
outputs (O1 to O
EIO
SHL
160
EIO
1
InputsOutputsL
OutputsInputsH
to O1 sequentially, while input of "H" level at VDD fetches data in the
160
. The table below shows the relationship between read data and driver
160
).
2
Data
input
40 clocks 39 clocks 38 clocks
D
0
D
1
D
2
D
3
D
0
D
1
D
2
D
3
O
1
O
2
O
3
O
4
O
160
O
159
O
158
O
157
O
O
O
O
Numbers of the clock pulse
...
O
O
O
O
156
155
154
153
5
6
7
8
O
9
O
10
O
11
O
12
O
152
O
151
O
150
O
149
...
...
...
...
...
...
...
...
3 clocks 2 clocks 1 clocks
O
149
O
150
O
151
O
152
O
12
O
11
O
10
O
9
O
153
O
154
O
155
O
156
O
8
O
7
O
6
O
5
O
157
O
158
O
159
O
160
O
4
O
3
O
2
O
1
TRUTH TABLE
DF Display Data DISPOFF Driver output (01~0
LLH V
LHH V
HLH V
HHH V
XXL V
X : don't care
NOTES ON USAGE (when turning the power ON or OFF)
If a high voltage is applied to a LCD drive system while the logic supply is floating, over
destroy the device, because the voltage over the LCD drive system is high.
Follow the sequence below when turning the power ON or OFF.
Power ON : Logic system ON Æ LCD drive system ON, or both ON
Power OFF : LCD drive system OFF Æ logic system OFF, or both OFF
3
1
4
EE
1
-current may
160
)
9/9
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