Datasheet MSC23S4641E-8BS16 Datasheet (OKI)

MSC23S4641E-8BS16 (98.06.22)

Semiconductor

MSC23S4641E-8BS16

4,194,304 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (2BANK):

DESCRIPTION

The Oki MSC23S4641E-8BS16 is a fully decoded, 4,194,304 x 64bit synchronous
dynamic random access memory composed of sixteen 16Mb DRAMs(2Mx8) in TSOP
packages mounted with decoupling capacitors on a 168-pin glass epoxy Dual-in-Line
Package supports any application where high density and large capacity of storage
memory are required, like for example PCs or servers.

FEATURES

• 4-Meg Word x 64-Bit (2Bank 8 Byte) organization

• 168-pin Dual Inline Memory Module

• All DQ Pins have 10Ω Damping Resister

• Single 3.3V power supply, ±0.3V tolerance

• Input :LVTTL compatible

• Output :LVTTL compatible

• Refresh : 4,096 cycles/64 ms

• Programmable data transfer mode

• Burst length(1,2,4,8,Full)

• Data scramble(sequential,interleave)

• CBR auto-refresh, Self-refresh capability

• Serial Presence Detect (SPD) With EEPROM

• CAS latency

(2, 3)

PRODUCT ORGA NIZATION

Product Nam e Operation Access Time(Max.)

Frequency(Max.) tAC2 tAC3

MSC23S4641E -8BS16 125MHz 10.0ns 6.0ns

MSC23S4641E-8BS16 (98.06.22)

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BLOCK DIAGRAM

CKE1
CKE0

CS0

DQMB0

DQ0

DQ7
DQMB1

DQ8

DQ15

DQMB4

DQ32

DQ39
DQMB5

DQ40

DQ47

DQM CKE

DQ0

CS

1

DQ7

DQM CKE

DQ0

CS

2

DQ7

DQM CKE

DQ0

CS

5

DQ7

CS

DQM CKE

DQ0

6

DQ7

CS1

DQM CKE

DQ0

DQ7

DQM CKE

DQ0

DQ7

DQM CKE

DQ0

DQ7

DQM CKE

DQ0

DQ7

CS2

DQMB2

DQM CKE

CS

DQ16

DQ0

911

CS

DQ23

DQMB3

DQ24

DQ7

DQ0

10

CS

DQ31

DQMB6

DQ48

DQ7

DQ0

13

DQ7

DQ0

CS

DQ55

DQMB7

DQ56

14

DQ63

DQ7

CS

3

CS

DQM CKE

4

DQM CKE

CS

7

CS

DQM CKE

8

CS3

DQM CKE

DQ0

DQ7

DQM CKE

DQ0

DQ7

DQM CKE

DQ0

DQ7

DQM CKE

DQ0

DQ7

CS

CS

12

CS

15

CS

16

10K

Ω

CLK0

RAS,/CAS,/WE

A0-A11

3.3pF

1
2

5

CLK1

6

116

3.3pF

á

10
13
14

9

CLK2

Vcc

Vss

Note. The Value of all resistors is 10Ω expect WP and CKE1

MODULE OUTLINE

Serial PD

SCL

A0 A1 A2

SA0 SA1 SA2

3.3pF

0.1uF 0.33uF

17

47KΩ

3

SDA

WP

11

412

CLK3

7
8

Two Decoupling Capacitors
per SDRAM

3.3pF

15
16

109411

(Front)
(Back)

1

85

95

40

12441125

84

168

MSC23S4641E-8BS16 (98.06.22)

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PIN CONFIGURATION

Front si

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

1 VSS 85 VSS 43 VSS 127 VSS
2 DQ0 86 DQ32 44 N.C 128 CKE0
3 DQ1 87 DQ33 45 /CS2 129 /CS3
4 DQ2 88 DQ34 46 DQMB2 130 DQMB6
5 DQ3 89 DQ35 47 DQMB3 131 DQMB7
6 VCC 90 VCC 48 N.C 132 N.C
7 DQ4 91 DQ36 49 VCC 133 VCC
8 DQ5 92 DQ37 50 N.C 134 N.C

9 DQ6 93 DQ38 51 N.C 135 N.C
10 DQ7 94 DQ39 52 N.C 136 N.C
11 DQ8 95 DQ40 53 N.C 137 N.C
12 VSS 96 VSS 54 VSS 138 VSS
13 DQ9 97 DQ41 55 DQ16 139 DQ48
14 DQ10 98 DQ42 56 DQ17 140 DQ49
15 DQ11 99 DQ43 57 DQ18 141 DQ50
16 DQ12 100 DQ44 58 DQ19 142 DQ51
17 DQ13 101 DQ45 59 VCC 143 VCC
18 VCC 102 VCC 60 DQ20 144 DQ52
19 DQ14 103 DQ46 61 N.C 145 N.C
20 DQ15 104 DQ47 62 N.C 146 N.C
21 N.C 105 N.C 63 CKE1 147 N.C
22 N.C 106 N.C 64 VSS 148 VSS
23 VSS 107 VSS 65 DQ21 149 DQ53
24 N.C 108 N.C 66 DQ22 150 DQ54
25 N.C 109 N.C 67 DQ23 151 DQ55
26 VCC 110 VCC 68 VSS 152 VSS
27 /WE 111 /CAS 69 DQ24 153 DQ56
28 DQMB0 112 DQMB4 70 DQ25 154 DQ57
29 DQMB1 113 DQMB5 71 DQ26 155 DQ58
30 /CS0 114 /CS1 72 DQ27 156 DQ59
31 N.C 115 /RAS 73 VCC 157 VCC
32 VSS 116 VSS 74 DQ28 158 DQ60
33 A0 117 A1 75 DQ29 159 DQ61
34 A2 118 A3 76 DQ30 160 DQ62
35 A4 119 A5 77 DQ31 161 DQ63
36 A6 120 A7 78 VSS 162 VSS
37 A8 121 A9 79 CLK2 163 CLK3
38 A10 122 A11(BA0
39 N.C 123 N.C 81 WP 165 SA0
40 VCC 124 VCC 82 SDA 166 SA1
41 VCC 125 CLK1 83 SCL 167 SA2
42 CLK0 126 N.C 84 VCC 168 VCC

Back si

Front si

80 N.C 164 N.C

Back si

Pin Name Function Pin Name Function

VCC Power Supply (3.3V
VSS Ground (0V

CLK# System Clock DQ# Data Input/Output

/CS# Chip Select WP Write Protect

CKE# Clock Enable SDA Data I/O for SPD

A0-A10 Address SCL CLK input f or S P D

A11 Bank Select Address SA# Socket Position Address for SPD
/RAS Row Address Strobe N.C No Connection
/CAS Column Address Strobe

/WE Wri te Enable

DQMB# Data Input/Output Mask

MSC23S4641E-8BS16 (98.06.22)

,38,42,53,31,36,20,20,

SERIAL PRESENCE DET ECT

Byte

No.

0

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

36-61

62
63

64-71

72

73-90

91,92

93-125

126
127

128-255

41,45,20,20,20,20,20,20 Manufact ur er ’s JEDE C ID code

43,32,33,53,34,36,34,31,45,
2D

SPD

Remark Notes

Hex Value

80

Defines the number of by tes written int o

128 byte

SPD memory
08 Total number of by tes of SPD memory 256 byte
04 Fundamental memory type SDRAM

0B Number of rows 11 rows

09 Number of colum ns 9 columns
02 Number of module bank s 2 bank
40 Data width of this assembly 64 bits
00 ... Data width continuation 0
01 Voltage i nterface lev el LVTTL
80 Cycle time (CL=3) CL=3 tCC=8ns
60 Access time from CLK (CL=3) CL=3 tAC3=6ns
00 DIMM configuration type Non Parity
80 Refresh rate / type Normal/ Self/
08 Primary SDRAM width x8
00 Error checking SDRAM width
01 Minimum CLK delay tCCD: 1 CLK

8F Burst lengths supported 1,2,4,8,F

02 Number of banks on each SDRAM 2 banks
06 /CAS lat enc y 2,3
01 /CS latenc y 0
01 /WE latency 0
00 SDRAM module attri butes
06 SDRAM device att r ibutes : General

C0 Cycle time (CL=2) CL=2 tCC2=12ns
A0 Access time from CLK (CL= 2) CL=2 tAC2=10ns

00 Cycle time (CL=1) Not support
00 Access time fr om CLK (CL=1) Not support
14 Minimum ROW pulse width tRP=20ns
14 /RAS to /RA S bank delay tRRD=20ns
14 /RAS to /CA S delay tRCD=20ns
30 Minimum /RA S pr ec har ge time tRAS=48ns
04 Density of eac h bank on module 16MB
20
10

Command and addr ess signal input setup time

Command and addr ess signal input hold time

2ns

1ns
20 Data signal i nput setup time 2ns
10 Data signal i nput hold ti me 1ns

00-00 R.F.U

12 SPD data revision code 1.2

2D Checksum f or by te 0-62

01/06 Manufact ur ing location

Manufact ur er ’s part number C23S 4641E - 8B S 16

20
20,20 Revision code
00-00 R.F.U

64 Intel speci fication f r equenc y 100MHz

F5 Intel specification /CAS latency CLK0-3,CL=3

FF-FF Unused storage locations

MSC23S4641E-8BS16 (98.06.22)

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Rating Symbol Value Unit

Voltage on any pin relative to Vss VIN, V
Vcc supply volt age Vcc,VccQ -0.5 to 4.6 V

Storage temperature T
Power dissipation P
Short circuit current Ios 50 mA

Operating temperatur e T

OUT

stg

D*

opr

-0.5 to VCC+0.5 V

- 55 to 125 °C
16 W

0 to 70 °C

*: Ta=25

u

Recommended Operating Conditions

Parameter S ymbol Min. Typ. M ax. Unit

Power supply voltage Vcc,VccQ 3.0 3.3 3.6 V
Input high voltage VIH 2. 0 - VCC+0.3 V
Input low voltage VIL -0.3 - 0.8 V

(Voltages referenced to Vss = 0V)

Capacitance

Parameter Symbol Max. Unit

Input capaci tance(A0-A11,/RAS, /CAS ,/WE) CI N1 98 pF
Input capaci tance(/CS0,/CS1,/CS2, /CS3) CIN2 34 pF
Input capaci tance(DQMB0-DQMB7) CIN3 22 pF
Input capaci tance(CKE0,CKE 1) CIN4 58 pF
I/O capacitance(DQ0-DQ63) C
Input capaci tance(CLK0,CLK1, CLK 2,CLK3) C

(Vcc=3.3V ± 0.3V, Ta = 25°C f=1MHz)

DQ

CLK

25 pF
50 pF

MSC23S4641E-8BS16 (98.06.22)

DC CHARACTERISTICS

Parameter Symbol

Input Leakage
Current I

LI

Bank CKE O t hers Min Max

- -

Condition

(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C)

Module

Spec.

-

-160 160

Unit

uA

Note

Output Leakage
Current

Output High
Voltage

Output Low
Voltage

Average Power
Supply Current

(Operating)

Power Supply
Current

(Stand by)
Average Power

Supply Current
(Clock

Suspenson)
Average Power

Supply Current
(Active Stand by)

I

LO

V

OH

V

OL - -

ICC1 One B ank

ICC1D

I

CC2

I

CC3S

I

CC3

--

--

Active

Both
Banks
Active

Both
Banks

Precharge

Both
Banks
Active

One
Banks

Active

CKE ≥ VIH

CKE ≥ VIH

CKE ≥ VIH

CKE ≤ VIL

CKE ≥ VIH

-

I

= -2mA 2.4 -

OH

IOL = 2mA - 0.4
tCC=min

tRC=min
No Burst

tCC=min
tRC=min
tRRD=min
No Burst

tCC=min

tCC=min

tCC=min

-20 20

- 1000 mA

- 1240 mA

- 640 mA

- 344 mA

-

680

uA

V

V

mA

1,2

1,2

3

2

3

Power Supply
Current (Burst)

Power Supply
Current

(Auto-Refresh)
Average Power

Supply Current
(Self-Refresh)

Average Power
Supply Current

(Power down)

NOTE: 1. Measured with the output open.

2. The address and data can be changed once or left uncharged during one cycle.

3. The address and data can be changed once or left unchanged during two cycles.

I

CC4

ICC5

I

CC6

I

CC7

Both
Banks
A

iv

One Bank

Active CKE ≥ VIH

Both
Banks

Precharge

Both
Banks

Precharge

CKE ≥ VIH

CKE ≤ VIL

CKE ≤ VIL

tCC=min

tCC=min
tRC=min

tCC=min

tCC=min

- 1160 mA

- 960 mA

-32

-32

mA

mA

1,2

2

MSC23S4641E-8BS16 (98.06.22)

y

MODE SET ADDRESS KEYS

/CAS Latenc

A6 A5 A4 CL A3 BT A2 A1 A0 BT=0 BT=1

0 0 0 Reserved 0 Sequential 0 0 0 1 1
0 0 1 Reserved 1 Inter leav e 0 0 1 2 2
0102 0104 4
0113 0118 8
1 0 0 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved 1 0 1 Reserved Reserved
1 1 0 Reserved 1 1 0 Reserved Reserved
1 1 1 Reserved 1 1 1 Ful l Page Reserv ed

Note: A7,A8,A9, A10 and A11 should stay "L" during mode set cycle.

Burst Type Burst Length

POW ER ON SEQUE NCE

1. With inputs in NOP state, turn on the power supply and start the system clock.

2. After the VCC voltage has reached the specified level,pause for 200us or more
with the input kept in NOP state.

3. Issue the precharge all bank command.

4. Apply a CBR auto-refresh eight or more times.

5. Enter the mode register setting command.

MSC23S4641E-8BS16 (98.06.22)

AC CHARACTERISTI C

Parameter Symbol Module Spec. Unit Note

Clock Cycle Time CL=3 tCC 8 - ns

Access Time from Clock CL=3 tAC - 6 ns 3,4

Clock "H" Pulse Time tCH 3 - ns
Clock "L" Pulse Time tCL 3 - ns
Input Setup T ime(CLK,ADD,DIN) tSI 2 - ns
Input Hold T ime(CLK,ADD,DIN) tHI 1 - ns
Output Low Im pedanc e Time from Clock tOLZ 3 - ns
Output Hi gh Impedance Time from Clock tOHZ - 9 ns
Output Hol d from Clock tOH 3 - ns
/RAS Cycle Time tRC 70 - ns
/RAS Precharge Time tRP 20 - ns
/RAS Activ e Time t RA S 48 100,000 ns
/RAS to /CAS Delay Time tRCD 20 - ns
Wr ite Recovery Time tWR 8 - ns
Wr ite Command Input T ime from O utput tOWD 20 - ns
/RAS to /RA S B ank A c tive Delay Time tRRD 20 - ns
Refresh Time tREF - 64 ms
Power-down Exit Set-up Time tPDE 10 - ns
Input Level Transi tion Ti me t T - 3 ns
/CAS to /CAS Delay Time (Min) I CCD 1 Cycle
Clock Disabl e Time from CK E ICKE 1 Cycle
Data Output High Impedanc e Time from DQM IDOZ 2 Cycl e
Data Input Mask Time from DQ M B IDOD 0 Cycle
Data Input Time from Write Command IDW D 0 Cycle
Data Output High Inpedance Time IROH CL Cycle
Active Com mand Input T ime from MODE I M RD 3 Cycle

NOTE 1,2 .

CL=2 12 - ns

CL=2 - 10 ns 3,4

(VCC = 3.3 ± 0. 3V , Ta = 0 ~70°C)

Min. Max.

NOTES:

1) AC measurem ents assume that tT=1ns.

2) The r eference level for t im ing of input signals is 1.4V.

3) This parameter is m eas ur ed with a load circuit equivalent to 1 TTL load and 50pF
(R Load is 50ohm).

4) An acc es s time is measured at 1.4V.

5) If tT is longer t han 1ns , the reference level for timing of input s ignals ar e V

OUTPUT

OUTPUT LOAD

IH

and V

1.4v

IL.

50

Ω

50pF

MSC23S4641E-8BS16 (98.06.22)

FUNCTION TRUTH TABL E (Table1)(1/2)

Current State /CS /RAS /CAS /WE BA ADDR Action

Idle H X X X X X NOP

LHHHXXNOP
L H H L BA X ILLEGAL
L H L X BA CA ILLEGAL
L L H H BA RA Row Active
L L H L BA A10 NOP
L L L H X X Auto-Refresh or Self-Refresh
L L L L L OP Code Mode Register write

Row Active H X X X X X NOP

LHHXXXNOP
L H L H BA CA,A10 Re ad
LHLLBACA,A10Write
L L H H BA RA ILLEGAL
L L H L BA A10 Precharge
LLLXXXILLEGAL

Read H X X X X X NOP(Continue Row Active after Burst ends)

L H H H X X NOP(Continue Row Active after Burst ends)
L H H L BA X Reserved
L H L H BA CA,A10 Term Burst,sta rt n ew Burst Read
L H L L BA CA ,A 1 0 Term Burst,s ta rt n ew Burst Write
L L H H BA RA ILLEGAL
L L H L BA A10 Term Burst,execute Row Precharge
LLLXXXILLEGAL

Write H X X X X X NOP(Contin u e Row Active a fter Burst ends)

L H H H X X NOP(Continue Row Active after Burst ends)
L H H L BA X ILLEGAL
L H L H BA CA,A10 Term Burst,sta rt n ew Burst Read
L H L L BA CA ,A 1 0 Term Burst,s ta rt n ew Burst Write
L L H H BA RA ILLEGAL
L L H L BA A10 Term Burst,execute Row Precharge

LLLXXXILLEGAL
Read with H X X X X X
Auto Precharge L H H H X X

NOP(Continue Burst to End and enter Ro w Pre charge )
NOP(Continue Burst to End and enter Ro w Pre charge )

L H H L BA X ILLEGAL

L H L H BA CA,A10 ILLEGAL

L H L L X X ILLEGAL

L L H X BA RA,A10 ILLEGAL

LLLXXXILLEGAL
Wri te with H X X X X X
Auto Precharge L H H H X X

NOP(Continue Burst to End and enter Ro w Pre charge )
NOP(Continue Burst to End and enter Ro w Pre charge )

L H H L BA X ILLEGAL

L H L H BA CA,A10 ILLEGAL

L H L L X X ILLEGAL

L L H X BA RA,A10 ILLEGAL

LLLXXXILLEGAL

2
2

4

5

2

2

2

2

2
2

2

2
2

2

MSC23S4641E-8BS16 (98.06.22)

FUNCTION TRUTH TABL E (Table1)(2/2)

Current State /CS /RAS /CAS /WE BA ADDR Action

Æ

Precharge H X X X X X NOP

LHHHXXNOP

L H H L BA X ILLEGAL

L H L X BA CA ILLEGAL

L L H H BA RA ILLEGAL

L L H L BA A10 NOP

LLLXXXILLEGAL
Write H X X X X X NOP
Recovery L H H H X X NOP

L H H L BA X ILLEGAL

L H L X BA CA ILLEGAL

L L H H BA RA ILLEGAL

L L H L BA A10 ILLEGAL

LLLXXXILLEGAL
Row Active H X X X X X NOP Row Active after tRCD

L H H H X X NOP Row Active after tRCD

L H H L BA X ILLEGAL

L H L X BA CA ILLEGAL

L L H H BA RA ILLEGAL

L L H L BA A10 ILLEGAL

LLLXXXILLEGAL
Refresh H X X X X X NOP Æ Idle after tRC

LHHXXXNOP

L H L X X X ILLEGAL

L L H X X X ILLEGAL

LLLXXXILLEGAL
Mode Re sister H X X X X X NOP
Access L H H H X X NOP

L H H L X X ILLEGAL

L H L X X X ILLEGAL

L L X X X X ILLEGAL

Idle after tRP

Æ

Idle after tRP

2
2
2

4

2
2
2
2

2
2
2
2

Æ

Idle after tRC

ABBREVIATIONS

RA=Row Addres s BA=Bank Address NOP=No Operation c omm and
CA=Column Address AP=Auto Precharge

Notes:

1.

All inputs will be enabled when CKE i s set hi gh for at least 1 cycl e pri or to the inputs.

2.

Illegal to bank i n spec ified st ate,but may be l egal i n som e c ases dependi ng on the s tate of bank
selection.

3.

Satisfy the timing of tCCD and tWR to prevent bus contention.

4.

NOP to bank prechar ging or i n idl e s tate. Pr echar ges ac ti vated bank by BA or A10.

5.

Illegal if any bank i s not i dl e.

MSC23S4641E-8BS16 (98.06.22)

FUNCTION TRUTH TABL E (CKE) (Table2)

Current State(n) CKEn-1 CKEn /CS /RAS /CAS /WE ADDR Action

Self R efresh H X X X X X X INVALID

L H H X X X X Exit Self Refresh Æ ABI
L H L H H H X Exit Se lf Refresh Æ ABI
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP(Maintain Self Refresh)

Power Down H X X X X X X INVALID

L H H X X X X Exit Power Down Æ ABI
L H L H H H X Exit Power Down Æ ABI
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L X X X X ILLEGAL

All Ban k s idle
(ABI) H L H X X X X Enter Power Down

Any State H H X X X X X Refer to Operations in Table 1
Other than H L X X X X X Begin Clock Suspend Next Cycle
Listed Above L H X X X X X Enable Clock of Next Cycle

6

L L X X X X X NOP(Continue power down mode)

H H X X X X X Refer to Table 1

H L L H H H X Enter Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L H L X ILLEGAL
H L L L L H X Enter Self Re fresh
H L L L L L X ILLEGAL

LLXXXXXNOP

L L X X X X X Continue Clock Suspension

6

Notes:

6.

Power-down and s el f refresh can be enter ed onl y when al l the bank s ar e i n an i dle s tate.