Datasheet MSC5301B-01GS-BK Datasheet (OKI)

E2B0017-27-Y2

¡ Semiconductor

This version: Nov. 1997

Previous version: Mar. 1996

MSC5301B-01¡ Semiconductor

MSC5301B-01

LCD COMMON/SEGMENT DRIVER WITH RAM

GENERAL DESCRIPTION

The MSC5301B-01 is an LCD driver LSI with built-in RAM. The device’s bit mapping method
offers greater flexibility because each bit of the RAM for display controls each section on the LCD
panel. It can form a graphic display system of 64 x 16 dots in one chip. In addition, the display
can be expanded by using additional LSIs.

FEATURES

• LCD driving voltage range : 6 to 16V

• Operating power supply voltage range : 5V ±10%

• Display duty : 1/16 (1/5 bias)

• Common output : 16 outputs

• Segment output : 64 outputs

• RAM capacity : 16 x 64 = 1024 bits

• Serial transfer clock frequency (f

• Multichip configuration available

• Blanking available

• Built-in RC oscillation circuit

• Package:
100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name: MSC5301B-01GS-BK)

) : 500 kHz Max.

SCK

1/15

BLOCK DIAGRAM

MSC5301B-01¡ Semiconductor

V4V1C0 C15 V

16-DOT COM DRV

(4-LEVEL DRV)

4-16 DECODER 64-BIT LATCH

4-BIT LATCH

READ (4-BIT)
ADDRESS COUNTER

DSP

S63 S0 V2V

64-DOT SEG DRV

(4-LEVEL DRV)

RAM

RA3
RA2

RA1

RA0

64x16
=1024 BITS

WA3
WA2

WA1

WA0

WE

3

V

DSP

GND

V

CC

GND

OSC

TIMING
GENERATOR

BLK

CTL

POR

CTL

64-BIT LATCH

INPUT

CTL

φ

64-BIT SHIFT REGISTER

LATCH

A/D

CHIP CTL

SI

6-BIT LATCH

SCK

FRAM
IN/OUT

CSO

8-BIT SHIFT REGISTER

CS1

OS1 OS2 φ BLK POR FRAM V

GND

CC

2/15

PIN CONFIGURATION (TOP VIEW)

S47

S48

S49

S50

S51

S52

95

96

97

98

99

100

S46

94

S45

93

NC

92

S44

91

S43

90

S42

89

S41

88

S40

87

S39

86

S38

85

S37

84

S36

83

S35

82

MSC5301B-01¡ Semiconductor

S34

81

S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63

C0
C1
C2
C3
C4
C5
C6
C7
C8

C9
C10
C11
C12
C13
C14
C15

V
V

CS0

1

2

3

4

5

6

7

8

9

10

11

12

13
14

15

16
17

18

19

20
21

22

23

24

25

26
27

28

4

29

1

30

80

79

78

77

76

75

74

73

72

71

70

69

68
67

66

65
64

63

62

61
60

59

58

57

56

55
54

53

52

51

S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4

31

CS1

33

32

A/D

LATCH

40

39

38

37

36

35

34

SI

SCK

POR

BLK

OS1

FRAM

OS2

NC: No connection

100-Pin Plastic QFP

41

φ

42

V

43

CC

GND

V

DSP

3V2

V

S0

S1

S2

S3

50

49

48

47

46

45

44

3/15

ABSOLUTE MAXIMUM RATINGS

MSC5301B-01¡ Semiconductor

Parameter

Power Supply Voltage

Power Supply Voltage

Input Voltage

Input Voltage

Power Dissipation

Storage Temperature

*1 V

DSP>V1>V2>V3>V4

Symbol

V

CC

V

DSP

V

IN

V

INDP

P

D

T

STG

>GND

Condition

Ta = 25°C

Ta = 25°C

Ta = 25°C

Ta = 25°C

Ta = 85°C

—

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage

Power Supply Voltage

Operating Temperature

Shift Frequency

Oscillation Frequency

Frame Frequency

Symbol

V

CC

V

DSP

T

op

f

SCK

f

φ

f

FR

Condition

GND = 0V

GND = 0V

—

—

—

—

Rating

–0.3 to +6.5

–0.3 to +18.0

–0.3V£V

–0.3£V

–55 to +125

6.0 to 16.0

–40 to +85

3.84 to 16.0

IN£VCC

INDP£VDSP

275

Range

4.5 to 5.5

25 to 500

60 to 250

+0.3

+0.3

*1

*1

Unit

V

V

V

V

mW

°C

Unit

V

V

°C

kHz

kHz

Hz

*1 V

DSP>V1>V2>V3>V4

>GND

4/15

ELECTRICAL CHARACTERISTICS

DC Characteristics

Parameter

"H" Input Voltage

"L" Input Voltage

Hysteresis Voltage 1

Hysteresis Voltage 2

Pull-up Resistance

Pull-up Voltage

"H" Input Current

"L" Input Current

"H" Output Voltage

"L" Output Voltage

Common Driver

Output Voltage

Segment Driver

Output Voltage

Supply Current 1

Supply Current 2

Symbol

V

IH

V

IL

V

HS1

V

HS2

R

PU

V

PH

I

IH

I

IL

V

OH

V

OL

V

DP

V

1

V

4

V

SS

V

DP

V

2

V

3

V

SS

I

CC

I

DSP

V

= 0V

I

< 1mA

I

I

= 5.5V, VIH = 5.5V

V

CC

= 5.5V, VIL = 0V

V

CC

= –0.4mA

I

O

= 1.6mA

I

O

= 10V

V

DSP

*5

= 10V

V

DSP

*6

= 5.0V

V

CC

= 5.0V

V

CC

Condition

—

—

—

—

I = –10mA

I = ±10mA

I = ±10mA

I = +10mA

I = –10mA

I = ±10mA

I = ±10mA

I = +10mA

*1

*1

*2

*9

*2

*2

*3

*3

*4

*4

*7

*8

Min.

V

DSP

V

V

V

DSP

V

V

3.5

0

0.3

0.2

10

4.9

—

—

4.6

—

–0.4

1

–0.4

4

—

–0.4

2

–0.4

3

—

—

—

–0.4

–0.4

MSC5301B-01¡ Semiconductor

(VCC = 5V, Ta=–40 to +85°C)

Typ.

—

—

0.8

0.4

35

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Max.

V

CC

1.5

1.4

0.8

60

—

±10

±10

—

0.4

—

+0.4

V

1

+0.4

V

4

0.4

—

+0.4

V

2

+0.4

V

3

0.4

6.0

0.5

Unit

V

V

V

V

kW

V

mA

mA

V

V

V

V

V

V

V

V

V

V

mA

mA

*1 Applicable to all input pins
*2 Applicable to LATCH, A/D, SI, SCK, BLK and POR pins
*3 Applicable to CS0, CS1, OS1 and FRAM pins
*4 Applicable to FRAM and f pins
*5 Applicable to C0 - C15 pins
*6 Applicable to S0 - S63 pins
*7 ff = 6.4 kHz, f

V

= 16V, Current flows into VCC pin

DSP

*8 ff = 6.4 kHz, f

V

= 16V, Current flows into V

DSP

= 200 kHz, no load, display pattern = checkers

SCK

= 200 kHz, no load, display pattern = checkers

SCK

pin

DSP

*9 Applicable to OS1 pin

5/15

AC Characteristics

(VCC = 5V, Ta = –40 to +85°C)

Symbol Condition Min. Typ. Max. UnitParameter

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

f

FR

—2——msSCK Clock Period

—1——msSI Data Setup Time

—1——msSI Data Hold Time

—1——msSCK-LATCH Time

— 15——msLATCH Pulse Width
—1——msA/D Setup Time
—1——msA/D Hold Time
—1——msA/D-SCK Time

— ——20msPOR, BLK Fall Time

CL = 50 pF — — 0.3 msf, FRAM Rise Time

CL = 50 pF — — 0.3 msf, FRAM Fall Time

*1 85 100 115 HzFrame Frequency

*1 The dispersion of external resistors and capacitors is not included.

R

= 1kΩ, RT = 16kΩ, C

S

= 4700pF, VCC = 4.5V to 5.5V

T

MSC5301B-01¡ Semiconductor

SCK

SI

LATCH

t

6

t

1

t

t

2

3

t

t5t

4

7

t

8

A/D

6/15

POR, BLK

MSC5301B-01¡ Semiconductor

V

CC

90%

10%

GND

t

9

V

CC

90%

f, FRAM

C0

10%

GND

t

11

V

DSP

V

1

V

4

t

10

GND

1/f

FR

1/f

FR

Frame A Frame B

7/15

MSC5301B-01¡ Semiconductor

FUNCTIONAL DESCRIPTION

Pin Functional Description

• OS1 (Pin 39), OS2 (Pin 40), f (Pin 41)

These are pins for the RC oscillation circuit. Connect external resistors and a capacitor as shown
below. When inputting the external clock pulse, input it to OS1 pin. OS2 and f pins should
be left open.

OS1 OS2 f

R

S

C

T

R

T

The relationship between the frame frequency fFR and internal clock frequency ff is expressed
by the following equation:
(RC oscillation frequency = internal clock frequency)

ff = 4 x 16 x f

FR

In addition, the relationship between the frame frequence fFR and frame synchronizing signal
frequency f

is expressed by the following equation.

FRAM

f

FRAM

= fFR/2

• CS0 (Pin 30), CS1 (Pin 31)
Chip select input pins. Master or slave mode is selected by CS0 and CS1 as shown in the table
below. A maximum of 4 chips can be connected in this manner. Use the master mode when
using a single device.

CS0 CS1 Operation mode

L L Master mode

H L Slave mode

L H Slave mode

H H Slave mode

CC

level

H : V

L : GND level

8/15

MSC5301B-01¡ Semiconductor

• FRAM (Pin 38)

This is an input and output pin for the frame synchronizing signal to be used for master/slave
configuration. This is used as an output pin in master mode and as an input pin in slave mode.

• SI (Pin 34)

This is a serial data input of address data (8 bits) and segment data (64 bits). A pull-up resistor
(10 kW - 60 kW) and a Schmitt circuit are contained.

• SCK (Pin 35)

This is a shift clock input of address data (8 bits) and segment data (64 bits). The serial data is
shifted at the rising edge of SCK pulse. A pull-up resistor (10 kW - 60 kW) and a Schmitt circuit
are contained.

• LATCH (Pin 32)

This is a latch pulse input of address data (8 bits) and segment data (64 bits). The latch data
comes through at "H" level of LATCH and the data just before "H" level is latched at "L" level.
A pull-up resistor (10 kW - 60 kW) and a Schmitt circuit are contained.

•A/D (Pin 33)

This is a data select signal input of address data (8 bits) and segment data (64 bits). "H" level
is set in the case of address 8-bit input and "L" level is set in the case of segment data 64-bit input.
A pull-up resistor (10 kW - 60 kW) and a Schmitt circuit are contained.

•V

(Pin 44), V1 (Pin 29), V2 (Pin 45), V3 (Pin 46), V4 (Pin 28), VCC (Pin 42), GND (Pin 43)

DSP

These are power supply pins for this LSI and bias power supply pins for LCD driving.
V

which is a power supply pin, is from 4.5V to 5.5V and GND, which is a ground pin, is 0V.

CC,

V

which is an LCD driving power supply pin, is usually used in the range between 6V and

DSP,

16V. V1, V2, V3 and V4 are bias power supply pins for LCD driving and are usually used with
the bias voltage supplied from an external source.

9/15

MSC5301B-01¡ Semiconductor

• BLK (Pin 37)

This is an input pin to control the LCD panel display.
When a "H" level is input (or when this pin is open), the segment output pins S0 - S63 come to
the levels V2 - V3 and the LCD panel is turned off. In addition, during this period, reading of
data from display RAM stops but writing into the display RAM of address and segment data
input from the SI pin is enabled.
When this pin is changed from "H" to "L" level, the frame synchronizing signal FRAM is output
within 2 cycles of an internal clock ff, and multiple chips are synchronized. Then, the display
RAM address is set to "0000". After 1/16 frame cycle from FRAM signal generation, the output
is applied from the "0001" data of the display RAM address to the segment driver. When the
power supply is turned on, keep this pin to "H" level (or leave open) until writing data to the
RAM is completed, because the display RAM contents are undefined at power-on. A pull-up
resistor (10 kW - 60 kW) and a Schmitt circuit are contained.

• POR (Pin 36)

This is a power-on-reset input pin. When a "H" level is input (or when this pin is open), the
common and segment outputs come to the static display-off state regardless of the BLK pin and
the segment output pins S0 - S63 become V3 level and the common output pins C0 - C15 become
V4 level.
When this pin changes from "H" to "L" level, the frame synchronizing signal FRAM is output
within 2 cycles of an internal clock ff, synchronized at multichip, and is moreover dynamic­operated from the frame B . The display RAM address is set to "0000."
After 1/16 frame cycle from FRAM signal generation, the data at display RAM address "0001"
is output to the segment driver. However, because the BLK pin is usually at "H" level when
the power-on-reset is released, reading data from the display RAM stops and display-off
segment data is forcibly transferred to the segment output.
A pull-up resistor (10 kW - 60 kW) and a Schmitt are contained.

• C0 (Pin 12) - C15 (Pin 27)

These are 16-output pins of common driver which are used for LCD panel driving. The outputs
have 4 levels. V

and GND levels are select levels. The V1 and V4 levels are non-select levels.

DSP

• S0 (Pin 47) - S63 (Pin 11)

These are 64-output pins of segment driver which are used for LCD panel driving. The outputs
have 4 levels. V

and GND levels are used as display-on ones, which correspond to "1" of

DSP

the display RAM data. V2 and V3 levels are used as display-off ones, which correspond to "0"
of the display RAM data.

NOTES ON USE

Note the following when turning power on and off:
The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied
to the LCD drivers with the logic power supply floating, excess current flows. This may
damage the IC. Be sure to carry out the following power-on and power-off sequences:

When turning power on:
First turn VCC ON, next V
When turning power off:
First turn V

, V4, V3, V2, V1 OFF, next VCC OFF. Or both OFF at the same time.

DSP

, V4, V3, V2, V1 ON. Or both ON at the same time.

DSP

10/15

MSC5301B-01¡ Semiconductor

Relationship Between LCD Screen Size and Display RAM

This LCD driver has built-in RAM for the display of 16 x 64 = 1024 bits and each address
corresponds to each 1/16 duty of the LCD.
The data corresponds to the number of dots in the X direction. The relation between the LCD
screen size and the display RAM is shown below.

Address

Data

A3

A2

A1

A0

S63 S0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

C

0

C

1

C

2

C

3

C

4

C

5

C

6

C

7

C

8

C

9

C

10

C

11

C

12

C

13

C

14

C

15

1/16 duty

Number of dots in X direction (64)

Relationship Between Frame Cycle and Display RAM Data

The output of the display RAM data corresponds to the segment output.
The relationship between the frame cycle and the display RAM data is as follows:

First line address

Segment output
(Contents of RAM)

0000 0001 0010 0011 1110 1111 0000 0001

1 frame cycle

11/15

MSC5301B-01¡ Semiconductor

Multiple Configuration

This LCD driver can form multiple configuration.
It is possible to form a maximum of 4 devices (a panel of up to 256 ¥ 16 dots in size can be formed)
by using chip select signals CS0 and CS1. The devices in multiple configuration must be
synchronized with one another. In this configuration, one device in the master mode and the
other devices in the slave mode are used in combination. In the master mode, the original
oscillation signal f and the synchronous signal FRAM are output; in the slave mode, the
original oscillation signal f and the synchronous signal FRAM are input.
Refer to items CS0 and CS1 of pin description on the mode setting method.
The original oscillation signal output pin f of the master mode device is connected to the OS1
pin of the slave mode device and the synchronizing signal pin FRAM is also connected to the
FRAM pin of the slave mode device.
Connect SI, SCK, LATCH, A/D, POR and BLK of the master mode device to SI, SCK, LATCH,
A/D, POR and BLK of each of the slave mode devices and connect them to CPU for control.
In addition, connect the devices so that V

, V1, V2, V3, V4 and GND are shared between the

DSP

devices, and connect them to each voltage level divided by external resistors.

Address Data Configuration

(MSB) (LSB)

7

Dummy data Upper address Lower address

DM6DM5CS14CS03A32A21A10A0

2 bits 2 bits

4 bits

The lower address, which is the display RAM address, corresponds to the common sides C0

- C15 of the LCD panel.
The upper address corresponds to the logical state of chip select pins CS0 and CS1 and the lower
address is set to the device.
For the device to output the common signal (f, FRAM), set both of the upper address 2 bits to
"L". The 2 bits of dummy data can be set to either "L" or "H".

12/15

Serial Signal to be Input From CPU

The following signals are input from an external CPU to this LCD driver.

- Serial transfer clock Æ SCK

- Serial transfer data Æ SI

- Serial transfer latch Æ LATCH

- Serial data select Æ A/D
The operations are shown in the following table.

Mode A/D SCK LATCH SI

MSC5301B-01¡ Semiconductor

Address data

input mode

Segment data

input mode

H

L

Shifts at

the rising edge

Shifts at

the rising edge

8-bit address latch at falling

edge (level sensitive)

64-bit segment data latch at

falling edge (level sensitive)

Timing Chart of Serial Signal Transferred From CPU

A/D

SCK

SI

"H" at address data setting "L" at segment data setting

12345678 12 3 6364

A0 A1 A2 A3 CS0 CS1 Dummy Dummy S63 S62 S61 S1 S0

LSB

MSB

8-bit address data

Serial input from LSB side

64-bit segment data

Serial input from S63 corresponding data

"1" : Display-on data, "0" : Display-off data

Address data (8 bits) Segment data (64 bits)

LATCH

Address latch

signal

RAM write

signal

Notes:

1. Make sure to set the address before writing the segment data to RAM. Then, write the segment

data to RAM.

2. While the POR pin is "H" (upon power-on reset), neither the address data nor the segment

data can be entered.

13/15

MSC5301B-01¡ Semiconductor

14/15

Operation upon Power ON (When Single Device Used)

Dynamic operation (normal operation)Dynamic light-out state

Frame B Frame B Frame A Frame AFrame BFrame BFrame A

RAM address 0 - F

Frame A

0 - F 0 - 0 0 - F 0 - F 0 - F 0 - F

Segment signal
output

Common signal output

FRAM

f

(External R and C)

BLK

POR

V

CC

PACKAGE DIMENSIONS

QFP100-P-1420-0.65-BK

Mirror finish

MSC5301B-01¡ Semiconductor

(Unit : mm)

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

1.29 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

15/15