Page 1
Preliminary
MSC23CV43257A-xxBS8¡ Semiconductor
¡ Semiconductor
MSC23CV43257A-xxBS8
4,194,304-Word ¥ 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The Oki MSC23CV43257A-xxBS8 is a fully decoded 4,194,304-word ¥ 32-bit CMOS dynamic
random access memory composed of eight 16-Mb DRAMs (4M ¥ 4) in TSOP packages mounted
with decoupling capacitors on a 72-pin glass epoxy Small Outline DIMM Package supports any
application where high density and large capacity of storage memory are required.
FEATURES
• 4,194,304-word ¥ 32-bit organization
• 72-pin Small Outline DIMM
• Single 3.3 V supply ±0.3 V tolerance
• Input : LVTTL compatible
• Output : LVTTL compatible, 3-state
• Refresh : 2048 cycles/32 ms
• CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability
• Multi-bit test mode capability
• Fast Page Mode with EDO capability
PRODUCT FAMILY
Family
MSC23CV43257A-60BS8
MSC23CV43257A-70BS8
Access Time (Max.)
RAC
60 ns
70 ns
t
AA
30 ns
35 ns
t
CAC
15 ns
20 ns
Cycle Time
(Min.)
110 ns
130 ns
Power Dissipation
Operating (Max.)
3456 mW
3168 mW
Standby (Max.)t
28.8 mW
345
Page 2
MSC23CV43257A-xxBS8 ¡ Semiconductor
PIN CONFIGURATION
MSC23CV43257A-xxBS8
(Unit : mm)
3.80 Max.
25.4 ±0.13
3.18 ±0.13
2.0 ±0.13
R2.0
17.78 ±0.13
1.8 ±0.1
2 – φ1.8
3.03
2.62 Typ.
*1
44.45 ±0.1
59.69 ±0.2
44.45 ±0.1
51.66 ±0.1
711
272
3.25 Typ.
5.00
R2.0
5.5 Min.
1.00 ±0.1
1.0 ±0.1
0.25 Max.
0.23 Min.
1.27 ±0.1
346
*1 The common size difference of the board width 19.78 mm of its height is
specified as ±0.2. The value above 19.78 mm is specified as ±0.5.
Page 3
Pin Configuration
MSC23CV43257A-xxBS8¡ Semiconductor
Pin No.
Pin Name
11631
2 173247
3 183348
4 193449
5 203550
6 213651
7 223752
8 233853
9 243954
10 25 40 55
11 26 41 56
12 27 42 57
13 28 43 58
14 29 44 59
15 30 45 60
V
SS
DQ0 A5 A9 WE
DQ1 A6 NC NC
DQ2 A10
DQ3 NC DQ15 DQ19
DQ4 DQ8 NC DQ20
DQ5 DQ9 DQ16 DQ21
DQ6 DQ10 DQ17 DQ22
DQ7 DQ11 V
V
CC
PD1 DQ13 CAS2 DQ24
A0 DQ14 CAS3 DQ25
A1 A7 CAS1 DQ26
A2 NC RAS0 DQ27
A3 V
Pin No.
Pin Name
A4 A8 NC
Pin No.
Pin Name
Pin No.
46
RAS2 DQ18
SS
DQ12 CAS0 NC
CC
NC DQ28
Pin Name
DQ23
Presence Detect Pins
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
Pin Name
V
CC
DQ29
DQ30
DQ31
NC
PD2
PD3
PD4
PD5
PD6
PD7
V
SS
Pin No.
67 PD3
Pin Name
MSC23CV43257A
-60BS8
V
SS
NC69 PD5
MSC23CV43257A
-70BS8
NCNC11 PD1
NCNC66 PD2
V
SS
NCNC68 PD4
V
SS
NCNC70 PD6
NCNC71 PD7
347
Page 4
MSC23CV43257A-xxBS8 ¡ Semiconductor
BLOCK DIAGRAM
A0 - A10
RAS0
CAS0
WE
A0 - A10
RAS
CAS
WE
V
CC
A0 - A10
RAS
CAS
WE
V
CC
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
V
DQ0
DQ1
DQ2
DQ3
OE
SS
DQ4
DQ5
DQ6
DQ7
OE
SS
RAS2
CAS2
A0 - A10
RAS
CAS
WE
V
CC
A0 - A10
RAS
CAS
WE
V
CC
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
V
DQ16
DQ17
DQ18
DQ19
OE
SS
DQ20
DQ21
DQ22
DQ23
OE
SS
CAS1
V
V
CC
C1 C8
SS
A0 - A10
RAS
CAS
WE
V
CC
A0 - A10
RAS
CAS
WE
V
CC
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
V
OE
OE
DQ8
DQ9
DQ10
DQ11
A0 - A10
RAS
CAS
WE
SS
DQ12
DQ13
DQ14
DQ15
V
A0 - A10
RAS
CAS
WE
SS
V
DQ
DQ24
DQ
DQ25
DQ
DQ26
DQ
DQ27
OE
CC
V
SS
DQ
DQ28
DQ
DQ29
DQ
DQ30
DQ
DQ31
OE
CC
V
SS
CAS3
348
Page 5
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
MSC23CV43257A-xxBS8¡ Semiconductor
Parameter
Voltage on Any Pin Relative to V
Voltage VCC Supply Relative to V
SS
SS
Symbol
V
IN
V
Short Circuit Output Current I
Power Dissipation P
Operating Temperature T
Storage Temperature T
, V
OS
opr
OUT
CC
D
stg
Rating Unit
–0.5 to 4.6 V
–0.5 to 4.6 V
50 mA
8W
0 to 70 °C
–40 to 125 °C
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min.
Typ.
3.0 3.3 3.6 V
000V
2.0 — VCC + 0.3 V
–0.3 — 0.8 V
Max.
Unit
Capacitance
Parameter
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ
Typ.
Note : Capacitance measured with Boonton Meter.
(Ta = 25°C, f = 1 MHz)
Max.
—57
Unit
pFInput Capacitance (A0 - A10)
pFInput Capacitance (WE)—65
pFInput Capacitance (RAS0, RAS2)—35
pFInput Capacitance (CAS0 - CAS3)—20
pFI/O Capacitance (DQ0 - DQ31) — 16
349
Page 6
MSC23CV43257A-xxBS8 ¡ Semiconductor
DC Characteristics
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Average Power
Supply Current
(Operating)
Power Supply
Current (Standby)
Average Power
Supply Current
(RAS-only Refresh)
Average Power
Supply Current
(CAS before RAS Refresh)
Average Power
Supply Current
(Fast Page Mode)
Symbol
I
LI
I
LO
V
OH
V
OL
I
CC1
I
CC2
I
CC3
I
CC6
I
CC7
Condition
0 V £ VI £ VCC + 0.3 V;
All other pins not
under test = 0 V
disable
D
OUT
0 V £ V
I
OH
I
OL
£ 3.6 V
O
= –2.0 mA
= 2.0 mA
RAS, CAS cycling,
= Min.
t
RC
RAS, CAS = V
IH
RAS, CAS
≥ V
–0.2 V
CC
RAS cycling,
= Min.
,
IH
CAS = V
t
RC
RAS cycling,
CAS before RAS,
= Min.
t
RC
RAS = V
,
IL
CAS cycling,
= Min.
t
HPC
(VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C)
MSC23CV43257A MSC23CV43257A
-60BS8 -70BS8
Min.
–80
Max.
80
CC
Min.
–80
2.4 V
Max.
80
CC
Unit
µA
µA–10 10 –10 10
V2.4 V
V0 0.4 0 0.4
mA— 960 — 880
mA—16—16
mA—8—8
mA— 960 — 880
mA— 960 — 880
mA— 1120 — 1040
Note
1, 2
1
1
1, 2
1, 2
1, 3
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. Address can be changed once or less while RAS=VIL.
3. Address can be changed once or less while CAS=VIH.
350
Page 7
MSC23CV43257A-xxBS8¡ Semiconductor
AC Characteristics (1/2)
Parameter
Random Read or Write Cycle Time
Fast Page Mode Cycle Time t
Access Time from RAS t
Access Time from CAS t
Access Time from Column Address t
Access Time from CAS Precharge t
Output Low Impedance Time from CAS t
Output Hold Time from CAS Low t
CAS to Data Output Buffer Turn-off Delay Time
RAS to Data Output Buffer Turn-off Delay Time
WE to Data Output Buffer Turn-off Delay Time
Transition Time t
Refresh Period t
RAS Precharge Time t
RAS Pulse Width t
RAS Pulse Width (Fast Page Mode) t
RAS Hold Time t
CAS Precharge Time t
CAS Pulse Width t
RAS Low to CAS High Delay Time t
CAS High to RAS Low Delay Time t
RAS Hold Time from CAS Precharge t
RAS to CAS Delay Time t
RAS to Column Address Delay Time t
RAS to Second CAS Delay Time t
Row Address Set-up Time t
Row Address Hold Time t
Column Address Set-up Time t
Column Address Hold Time t
Column Address Hold Time from RAS t
Column Address to RAS Lead Time t
Symbol
t
RC
HPC
RAC
CAC
AA
CPA
CLZ
DOH
t
CEZ
t
REZ
t
WEZ
T
REF
RP
RAS
RASP
RSH
CP
CAS
CSH
CRP
RHCP
RCD
RAD
RSCD
ASR
RAH
ASC
CAH
AR
RAL
(V
= 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1,2,3,10,11
CC
MSC23CV43257A
-60BS8
Min.
110
25
—
—
—
—
0
0
2
—
40
60
60
15
10
10
40
10
35
20
15
0
10
0
10
40
30
Max.
—
—
60
15
30
35
—
15
50
32
—
10k
100k
—
—
10k
—
—
—
45
30
—
—
—
—
—
—
MSC23CV43257A
-70BS8
Min.
130
30
—
—
—
—
0
0
2
—
50
70
70
20
10
10
45
10
40
20
15
0
10
0
15
45
35
Max.
—
—
70
20
35
40
—
20
50
32
—
10k
100k
—
—
10k
—
—
—
50
35
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns5—5—
ns
ns 7, 8020015
ns 7020015
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns70 —60 —
ns
ns
ns
ns
ns
ns
Note
4, 5, 6
4, 5
4, 6
4
4
7, 8
3
5
6
351
Page 8
MSC23CV43257A-xxBS8 ¡ Semiconductor
AC Characteristics (2/2)
(V
= 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1,2,3,10,11
CC
MSC23CV43257A
Min.
0
0
0
0
10
45
10
15
15
0
15
40
10
10
20
-60BS8
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Parameter
Read Command Set-up Time
Read Command Hold Time
Read Command Hold Time referenced to RAS
Write Command Set-up Time
Write Command Hold Time
Write Command Hold Time from RAS
Write Command Pulse Width
Write Command Pulse Width (Output Disable)
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
Data-in Hold Time
Data-in Hold Time from RAS
CAS Active Delay Time from RAS Precharge
RAS to CAS Set-up Time (CAS before RAS)
RAS to CAS Hold Time (CAS before RAS)ns
WE to RAS Precharge Time (CAS before RAS)
WE Hold Time from RAS (CAS before RAS)
RAS to WE Set-up Time (Test Mode)
RAS to WE Hold Time (Test Mode)
Symbol
RCS
t
RCH
t
RRH
t
WCS
t
WCH
t
WCR
t
WP
t
WPE
t
RWL
t
CWL
t
DS
t
DH
t
DHR
t
RPC
t
CSR
t
CHR
t
WRP
t
WRH
t
WTS
t
WTH
MSC23CV43257A
-70BS8
Min.
0
0
0
0
15
50
10
20
20
0
15
45
10
10
20
Max.
—t
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns10 —5—
ns
ns
ns
ns
ns
ns
ns
ns10 —10 —
ns10 —10 —
ns10 —10 —
ns20 —20 —
Note
9
9
352
Page 9
MSC23CV43257A-xxBS8¡ Semiconductor
Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
t
(Max.) is specified as a reference point only. If t
RCD
t
(Max.) limit, access time is controlled by t
RCD
6. Operation within the t
t
(Max.) is specified as a reference point only. If t
RAD
t
(Max.) limit, access time is controlled by tAA.
RAD
7. t
CEZ
(Max.), t
(Max.) and t
REZ
(Max.) limit ensures that t
RCD
(Max.) limit ensures that t
RAD
(Max.) define the time at which the output achieves
WEZ
CAC
(Max.) can be met.
RAC
is greater than the specified
RCD
.
(Max.) can be met.
RAC
is greater than the specified
RAD
the open circuit condition and are not referenced to output voltage levels.
8. t
9. t
CEZ
RCH
and t
or t
must be satisfied for open circuit condition.
REZ
must be satisfied for a read cycle.
RRH
10. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is an 8-bit parallel test function. CA0, CA1 and
CA10 are not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate
a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The
test mode is cleared and the memory device returned to its normal operating state by
performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
The 4M ¥ 32 module can be tested as a 512K ¥ 32 module in this test mode.
11. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test
mode parameters are obtained by adding 5 ns to the normal read cycle values.
See ADDENDUM I for AC Timing Waveforms
353
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