2,097,152-Word ¥ 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The Oki MSC23CV23257A-xxBS4 is a fully decoded 2,097,152-word ¥ 32-bit CMOS dynamic
random access memory composed of four 16-Mb DRAMs (2M ¥ 8) in TSOP packages mounted
with decoupling capacitors on a 72-pin glass epoxy Small Outline DIMM Package supports any
application where high density and large capacity of storage memory are required.
FEATURES
• 2,097,152-word ¥ 32-bit organization
• 72-pin Small Outline DIMM
• Single 3.3 V supply ±0.3 V tolerance
• Input: LVTTL compatible
• Output : LVTTL compatible, 3-state
• Refresh : 2048 cycles/32 ms
• CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability
• Multi-bit test mode capability
• Fast Page Mode with EDO capability
PRODUCT FAMILY
Family
MSC23CV23257A-60BS4
MSC23CV23257A-70BS4
Access Time (Max.)
RAC
60 ns
70 ns
t
AA
30 ns
35 ns
t
CAC
15 ns
20 ns
Cycle Time
(Min.)
110 ns
130 ns
Power Dissipation
Operating (Max.)
2160 mW
1872 mW
Standby (Max.)t
14.4 mW
315
Page 2
MSC23CV23257A-xxBS4¡ Semiconductor
PIN CONFIGURATION
MSC23CV23257A-xxBS4
(Unit : mm)
2.4 Max.
25.4 ±0.13
3.18 ±0.13
2.0 ±0.13
R2.0
17.78 ±0.13
1.8 ±0.1
2 – φ1.8
3.03
2.62 Typ.
*1
44.45 ±0.1
59.69 ±0.2
44.45 ±0.1
51.66 ±0.1
711
272
3.25 Typ.
5.00
R2.0
5.5 Min.
1.00 ±0.1
1.0 ±0.1
0.25 Max.
0.23 Min.
1.27 ±0.1
316
*1 The common size difference of the board width 19.78 mm of its height is
specified as ±0.2. The value above 19.78 mm is specified as ±0.5.
Page 3
Pin Configuration
MSC23CV23257A-xxBS4¡ Semiconductor
Pin No.
Pin Name
11631
2 173247
3 183348
4 193449
5 203550
6 213651
7 223752
8 233853
9 243954
10254055
11264156
12274257
13284358
14294459
15304560
V
SS
DQ0A5A9WE
DQ1A6NCNC
DQ2A10
DQ3NCDQ15DQ19
DQ4DQ8NCDQ20
DQ5DQ9DQ16DQ21
DQ6DQ10DQ17DQ22
DQ7DQ11V
V
CC
PD1DQ13CAS2DQ24
A0DQ14CAS3DQ25
A1A7CAS1DQ26
A2NCRAS0DQ27
A3V
Pin No.
Pin Name
A4A8NC
Pin No.
Pin Name
Pin No.
46
RAS2DQ18
SS
DQ12CAS0NC
CC
NCDQ28
Pin Name
DQ23
Presence Detect Pins
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
Pin Name
V
CC
DQ29
DQ30
DQ31
NC
PD2
PD3
PD4
PD5
PD6
PD7
V
SS
Pin No.
11PD1
67PD3
Pin Name
MSC23CV23257A
-60BS4
V
SS
V
SS
NC69PD5
MSC23CV23257A
-70BS4
V
SS
NCNC66PD2
V
SS
NCNC68PD4
V
SS
NCNC70PD6
NCNC71PD7
317
Page 4
MSC23CV23257A-xxBS4¡ Semiconductor
BLOCK DIAGRAM
DQ0
A0 - A10
RAS0
CAS0
WE
CAS1
A0 - A10R
RAS
CAS
WE
V
A0 - A10R
RAS
CAS
WE
V
DQ
DQ
DQ1
DQ2
DQ
DQ3
DQ
DQ4
DQ
DQ5
DQ
DQ6
DQ
DQ7
DQ
OE
CC
V
SS
DQ
DQ8
DQ9
DQ
DQ10
DQ
DQ11
DQ
DQ12
DQ
DQ13
DQ
DQ14
DQ
DQ15
DQ
OE
CC
V
SS
RAS2
CAS2
CAS3
V
CC
C1C4
V
SS
A0 - A10R
RAS
CAS
WE
V
CC
A0 - A10R
RAS
CAS
WE
V
CC
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
OE
SS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
OE
SS
318
Page 5
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
MSC23CV23257A-xxBS4¡ Semiconductor
Parameter
Voltage on Any Pin Relative to V
Voltage VCC Supply Relative to V
SS
SS
Symbol
V
IN
V
Short Circuit Output CurrentI
Power DissipationP
Operating TemperatureT
Storage TemperatureT
, V
OS
opr
OUT
CC
D
stg
RatingUnit
–0.5 to 4.6V
–0.5 to 4.6V
50mA
4W
0 to 70°C
–40 to 125°C
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. Address can be changed once or less while RAS=VIL.
3. Address can be changed once or less while CAS=VIH.
320
Page 7
MSC23CV23257A-xxBS4¡ Semiconductor
AC Characteristics (1/2)
Parameter
Random Read or Write Cycle Time
Fast Page Mode Cycle Timet
Access Time from RASt
Access Time from CASt
Access Time from Column Addresst
Access Time from CAS Precharget
Output Low Impedance Time from CASt
Output Hold Time from CAS Lowt
CAS to Data Output Buffer Turn-off Delay Time
RAS to Data Output Buffer Turn-off Delay Time
WE to Data Output Buffer Turn-off Delay Time
Transition Timet
Refresh Periodt
RAS Precharge Timet
RAS Pulse Widtht
RAS Pulse Width (Fast Page Mode)t
RAS Hold Timet
CAS Precharge Timet
CAS Pulse Widtht
RAS Low to CAS High Delay Timet
CAS High to RAS Low Delay Timet
RAS Hold Time from CAS Precharget
RAS to CAS Delay Timet
RAS to Column Address Delay Timet
RAS to Second CAS Delay Timet
Row Address Set-up Timet
Row Address Hold Timet
Column Address Set-up Timet
Column Address Hold Timet
Column Address Hold Time from RASt
Column Address to RAS Lead Timet
Symbol
t
RC
HPC
RAC
CAC
AA
CPA
CLZ
DOH
t
CEZ
t
REZ
t
WEZ
T
REF
RP
RAS
RASP
RSH
CP
CAS
CSH
CRP
RHCP
RCD
RAD
RSCD
ASR
RAH
ASC
CAH
AR
RAL
(V
= 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1,2,3,10,11
CC
MSC23CV23257A
-60BS4
Min.
110
25
—
—
—
—
0
0
3
—
40
60
60
15
10
10
40
5
35
20
15
0
10
0
15
40
30
Max.
—
—
60
15
30
35
—
15
50
32
—
10k
100k
—
—
10k
—
—
—
45
30
—
—
—
—
—
—
MSC23CV23257A
-70BS4
Min.
130
30
—
—
—
—
0
0
3
—
50
70
70
20
10
10
45
5
40
20
15
0
10
0
15
45
35
Max.
—
—
70
20
35
40
—
15
50
32
—
10k
100k
—
—
10k
—
—
—
50
35
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns5—5—
ns
ns7, 8015015
ns7015015
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns70—60—
ns
ns
ns
ns
ns
ns
Note
4, 5, 6
4, 5
4, 6
4
4
7, 8
3
5
6
321
Page 8
MSC23CV23257A-xxBS4¡ Semiconductor
AC Characteristics (2/2)
(V
= 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1,2,3,10,11
CC
MSC23CV23257A
Min.
0
0
0
0
10
40
10
15
15
0
15
40
5
5
10
-60BS4
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Parameter
Read Command Set-up Time
Read Command Hold Time
Read Command Hold Time referenced to RAS
Write Command Set-up Time
Write Command Hold Time
Write Command Hold Time from RAS
Write Command Pulse Width
Write Command Pulse Width (Output Disable)
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
Data-in Hold Time
Data-in Hold Time from RAS
CAS Active Delay Time from RAS Precharge
RAS to CAS Set-up Time (CAS before RAS)
RAS to CAS Hold Time (CAS before RAS)ns
WE to RAS Precharge Time (CAS before RAS)
WE Hold Time from RAS (CAS before RAS)
RAS to WE Set-up Time (Test Mode)ns
RAS to WE Hold Time (Test Mode)ns
Symbol
RCS
t
RCH
t
RRH
t
WCS
t
WCH
t
WCR
t
WP
t
WPE
t
RWL
t
CWL
t
DS
t
DH
t
DHR
t
RPC
t
CSR
t
CHR
t
WRP
t
WRH
t
WTS
t
WTH
MSC23CV23257A
-70BS4
Min.
0
0
0
0
15
45
15
20
20
0
15
45
5
5
15
Max.
—t
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10—10—
10—10—
Unit
ns
ns
ns
ns
ns
ns
ns
ns10—5—
ns
ns
ns
ns
ns
ns
ns
ns10—10—
ns10—10—
Note
9
9
322
Page 9
MSC23CV23257A-xxBS4¡ Semiconductor
Notes:1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
t
(Max.) is specified as a reference point only. If t
RCD
t
(Max.) limit, access time is controlled by t
RCD
6. Operation within the t
t
(Max.) is specified as a reference point only. If t
RAD
t
(Max.) limit, access time is controlled by tAA.
RAD
7. t
CEZ
(Max.), t
(Max.) and t
REZ
(Max.) limit ensures that t
RCD
(Max.) limit ensures that t
RAD
(Max.) define the time at which the output achieves
WEZ
CAC
(Max.) can be met.
RAC
is greater than the specified
RCD
.
(Max.) can be met.
RAC
is greater than the specified
RAD
the open circuit condition and are not referenced to output voltage levels.
8. t
9. t
10. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
and t
CEZ
or t
RCH
This mode is latched and remains in effect until the exit cycle is generated.
must be satisfied for open circuit condition.
REZ
must be satisfied for a read cycle.
RRH
The test mode specified in this data sheet is a 2-bit parallel test function. CA9 is not
used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high
level. If any internal bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating
state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
11. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specified value. These parameters should be specified in test mode cycle by adding the above
value to the specified value in this data sheet.
See ADDENDUM I for AC Timing Waveforms
323
Page 10
MSC23CV23257A-xxBS4¡ Semiconductor
324
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