Datasheet ML4827IP-2, ML4827IS-1, ML4827IS-2, ML4827CS-2, ML4827CP-1 Datasheet (Micro Linear Corporation)

November 1998

VEAO IEAO

V

FB

I

AC

V

RMS

I

SENSE

RAMP 1

OSCILLATOR

OVP

PFC I

LIMIT

UVLO

V

REF

PULSE WIDTH MODULATOR

POWER FACTOR CORRECTOR

BROKEN WIRE

COMPARATOR

2.5V

+
–

–
+

7.5V

REFERENCE

V

CC

V

CCZV

REF

VEA

+
–

IEA

+
–

+
–

+
–

PFC OUT

SRQ

Q

SRQ

Q

2.7V

–1V

0.5V

2µA

RAMP 2

PWM OUT

SRQ

Q

V

DC

SS

DC I

LIMIT

V

CC

DUTY CYCLE

LIMIT

–
+

1V

–
+

2.5V

V

FB

–
+

8V

8V

VIN OK

GAIN

MODULATOR

V

CCZ

3.5kΩ

3.5kΩ

1.25V

50µA

–
+

13.5V

DC I

LIMIT

14

12

11

GND

10

15

2

4

3

7

8

6

5

9

16 1 13

PRELIMINARY

ML4827*

Fault-Protected PFC and PWM Controller Combo

GENERAL DESCRIPTION

The ML4827 is a controller for power factor corrected,
switched mode power supplies, that includes circuitry
necessary for conformance to the safety requirements of
UL1950. A direct descendent of the industry-standard
ML4824-1, the ML4827 adds a TriFault Detect™ function
to guarantee that no unsafe conditions may result from
single component failure in the PFC. Power Factor
Correction (PFC) allows the use of smaller, lower cost
bulk capacitors, reduces power line loading and stress on
the switching FETs, and results in a power supply that
fully complies with IEC1000-3-2 specification. The
ML4827 includes circuits for the implementation of a
leading edge, average current, “boost” type power factor
correction and a trailing edge, pulse width modulator
(PWM). The device is available in two versions; the
ML4827-1 (Duty Cycle
(Duty Cycle

= 74%). The higher maximum duty cycle

MAX

of the -2 allows enhanced utilization of a given
transformer core’s power handling capacity. An over­voltage comparator shuts down the PFC section in the
event of a sudden decrease in load. The PFC section also
includes peak current limiting and input voltage brown­out protection. The PWM section can be operated in
current or voltage mode, and includes a duty cycle limit
to prevent transformer saturation.

= 50%) and the ML4827-2

MAX

FEATURES

■ Pin-compatible with industry-standard ML4824-1

■ TriFault Detect™ to conform to UL1950™ requirements

■ Available in 50% or 74% max duty cycle versions

■ Low total harmonic distortion

■ Reduces ripple current in the storage capacitor

between the PFC and PWM sections

■ Average current, continuous boost leading edge PFC

■ High efficiency trailing-edge PWM can be configured

for current mode or voltage mode operation

■ Average line voltage compensation with brown-out

control

■ PFC overvoltage comparator eliminates output

“runaway” due to load removal

■ Current fed gain modulator for improved noise immunity

■ Overvoltage protection, UVLO, and soft start

BLOCK DIAGRAM * Some Packages Are End Of Life

1

ML4827

PIN CONFIGURATION

PIN DESCRIPTION

ML4827

16-Pin PDIP (P16)

16-Pin Wide SOIC (S16W)

IEAO

I

AC

I

SENSE

V

RMS

V

DC

RAMP 1

RAMP 2

SS

1

2

3

4

5

6

7

8

TOP VIEW

16

VEAO

15

V

FB

14

V

REF

13

V

CC

12

PFC OUT

11

PWM OUT

10

GND

9

DC I

LIMIT

PIN NAME FUNCTION

1 IEAO PFC transconductance current error

amplifier output

2I

AC

3I

SENSE

PFC gain control reference input
Current sense input to the PFC current

limit comparator

4V

RMS

Input for PFC RMS line voltage
compensation

5 SS Connection point for the PWM soft start

capacitor

6V

DC

7 RAMP 1 PFC (master) oscillator input; f

PWM voltage feedback input

by RTC

T

OSC

set

8 RAMP 2 When in current mode, this pin

functions as as the current sense input;
when in voltage mode, it is the PWM
(slave) oscillator input.

PIN NAME FUNCTION

9 DC I

LIMIT

PWM current limit comparator input
10 GND Ground
11 PWM OUT PWM driver output
1 2 PFC OUT PFC driver output
13 V

CC

Positive supply (connected to an

internal shunt regulator)
14 V

REF

Buffered output for the internal 7.5V

reference
15 V

FB

PFC transconductance voltage error

amplifier input, and TriFault Detect

input
16 VEAO PFC transconductance voltage error

amplifier output

2

ABSOLUTE MAXIMUM RATINGS

ML4827

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.

Junction T emperature..............................................150°C

Storage Temperature Range ..................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) .....................260°C

Thermal Resistance (θJA)

Plastic DIP .......................................................80°C/W

VCC Shunt Regulator Current .................................. 55mA

I

Voltage..................................................–3V to 5V

SENSE

Voltage on Any Other Pin ... GND – 0.3V to V
I

............................................................................................20mA

REF

CCZ

+ 0.3V

Plastic SOIC .................................................. 105°C/W

OPERATING CONDITIONS

IAC Input Current ....................................................10mA

Peak PFC OUT Current, Source or Sink ................ 500mA

Peak PWM OUT Current, Source or Sink.............. 500mA

PFC OUT, PWM OUT Energy Per Cycle .................. 1.5µJ

Temperature Range

ML4827CX................................................. 0°C to 70°C

ML4827IX .............................................. –40°C to 85°C

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, ICC = 25mA, RT = 21.8kΩ, CT = 1000pF, TA = Operating Temperature Range (Note 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOLTAGE ERROR AMPLIFIER

Input Voltage Range 0 7 V
Transconductance V
Feedback Reference Voltage 2.48 2.55 2.62 V

NON INV

= V

, VEAO = 3.75V 50 85 120 µ

INV

Ω

Input Bias Current Note 2 –1 –2 µA
Output High Voltage 6.0 6.7 V
Output Low Voltage 0.6 1.0 V
Source Current ∆VIN = ±0.5V, V
Sink Current ∆VIN = ±0.5V, V
Open Loop Gain 60 7 5 dB
Power Supply Rejection Ratio V

CURRENT ERROR AMPLIFIER

Input Voltage Range –1.5 2 V
Transconductance V
Input Offset Voltage 2 10 17 mV
Input Bias Current –0.5 –1.0 µA
Output High Voltage 6.0 6.7 V
Output Low Voltage 0.6 1.0 V
Source Current ∆VIN = ±0.5V, V
Sink Current ∆VIN = ±0.5V, V
Open Loop Gain 60 7 5 dB
Power Supply Rejection Ratio V

OVP COMPARATOR

Threshold Voltage 2.6 2.7 2.8 V

- 3V < VCC < V

CCZ

NON INV

CCZ

= V

- 3V < VCC < V

= 6V –40 –80 µA

OUT

= 1.5V 40 80 µA

OUT

- 0.5V 60 75 dB

CCZ

, VEAO = 3.75V 130 195 310 µ

INV

= 6V –40 –90 µA

OUT

= 1.5V 40 90 µA

OUT

- 0.5V 60 75 dB

CCZ

Ω

Hysteresis 80 115 150 mV

3

ML4827

ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

TRI-FAULT DETECT

Fault Detect HIGH 2.6 2.7 2.8 V
Time to Fault Detect HIGH V

Fault Detect LOW 0.4 0.5 0.6 V

PFC I

COMPARATOR

LIMIT

Threshold Voltage –0.8 –1.0 –1.15 V
∆(PFC I

LIMIT VTH

Delay to Output 150 300 ns

DC I

COMPARATOR

LIMIT

Threshold Voltage 0.9 1.0 1.1 V
Input Bias Current ±0.3 ±1 µA
Delay to Output 150 300 ns

VIN OK COMPARATOR

Threshold Voltage 2.45 2.55 2.65 V
Hysteresis 0.8 1.0 1.2 V

GAIN MODULATOR

Gain (Note 3) IAC = 100µA, V

Bandwidth IAC = 100µA 10 MHz
Output Voltage IAC = 250µA, V

OSCILLATOR

= V

FB

FAULT DETECT LOW

to VFB =OPEN

1nF from VFB to GND 1 2 ms

- Gain Modulator Output) 100 190 mV

= VFB = 0V 0.36 0.55 0.66

RMS

IAC = 50µA, V
IAC = 50µA, V
IAC = 100µA, V

= 1.2V, VFB = 0V 1.20 1.80 2.24

RMS

= 1.8V, VFB = 0V 0.55 0.80 1.01

RMS

= 3.3V, VFB = 0V 0.14 0.20 0.26

RMS

= 1.15V, 0.74 0.82 0.90 V

RMS

VFB = 0V

Initial Accuracy TA = 25°C 75 80 85 kHz
Voltage Stability V

- 3V < VCC < V

CCZ

- 0.5V 1 %

CCZ

Temperature Stability 2%
Total Variation Line, Temp 72 88 kHz
Ramp Valley to Peak Voltage 2.5 V
Dead Time PFC Only 450 600 750 ns
CT Discharge Current V

RAMP 2

= 0V, V

= 2.5V 4.5 7.5 9.5 mA

RAMP 1

4

ML4827

ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

REFERENCE

PFC

PWM

SUPPLY

Output Voltage TA = 25°C, I(V
Line Regulation V

- 3V < VCC < V

CCZ

Load Regulation 1mA < I(V

) = 1mA 7.4 7.5 7.6 V

REF

- 0.5V 2 10 mV

CCZ

) < 20mA 2 15 mV

REF

Temperature Stability 0.4 %
Total Variation Line, Load, Temp 7.35 7.65 V
Long Term Stability TJ = 125°C, 1000 Hours 5 25 mV

Minimum Duty Cycle V
Maximum Duty Cycle V
Output Low Voltage I

Output High Voltage I

> 4.0V 0 %

IEAO

< 1.2V 90 95 %

IEAO

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.8 2.0 V

OUT

I

= 10mA, VCC = 8V 0.7 1.5 V

OUT

= 20mA 10 10.5 V

OUT

I

= 100mA 9.5 10 V

OUT

Rise/Fall Time CL = 1000pF 50 n s

Duty Cycle Range ML4827-1 0-44 0-47 0-50 %

ML4827-2 0-64 0-70 0-74 %

Output Low Voltage I

Output High Voltage I

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.8 2.0 V

OUT

I

= 10mA, VCC = 8V 0.7 1.5 V

OUT

= 20mA 10 10.5 V

OUT

I

= 100mA 9.5 10 V

OUT

Rise/Fall Time CL = 1000pF 50 n s

Shunt Regulator Voltage (V
V

Load Regulation 25mA < ICC < 55mA ±100 ±300 mV

CCZ

V

Total Variation Load, Temp 12.4 14.6 V

CCZ

) 12.8 13.5 14.2 V

CCZ

Start-up Current VCC = 11.8V, CL = 0 0.7 1.0 mA
Operating Current VCC < V

- 0.5V, CL = 0 16 19 mA

CCZ

Undervoltage Lockout Threshold 12 1 3 14 V
Undervoltage Lockout Hysteresis 2.7 3.0 3.3 V

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Includes all bias currents to other circuits connected to the V
Note 3: Gain = K x 5.3V; K = (I

GAINMOD

- I

) x IAC x (VEAO - 1.5V)-1.

OFFSET

pin.

FB

5

ML4827

TYPICAL PERFORMANCE CHARACTERISTICS

250

200

Ω

150

100

TRANSCONDUCTANCE (µ )

50

0

053

142

VFB (V)

250

200

Ω

150

100

TRANSCONDUCTANCE (µ )

50

0

–500 5000

IEA INPUT VOLTAGE (mV)

Voltage Error Amplifier (VEA) Transconductance (gm) Current Error Amplifier (IEA) Transconductance (gm)

400

300

15

2

4

3

7

V

FB

2.5V

I

AC

V

RMS

I

SENSE

RAMP 1

16 1 13

VEAO IEAO

VEA

–
+

MODULATOR

3.5kΩ

GAIN

3.5kΩ

200

100

VARIABLE GAIN BLOCK CONSTANT - K

0

053142

V

(mV)

RMS

Gain Modulator Transfer Characteristic (K)

POWER FACTOR CORRECTOR

IEA

+

–

1V

+
–

OSCILLATOR

BROKEN WIRE

COMPARATOR

+

–

2.7V

–1V

+
–

+
–

PFC I

OVP

LIMIT

2µA

V

SRQ

SRQ

CC

REFERENCE

Q

Q

7.5V

V

REF

PFC OUT

14

12

V

V

CCZ

REF

13.5V

Figure 1. PFC Section Block Diagram.

6

FUNCTIONAL DESCRIPTION

ML4827

The ML4827 consists of an average current controlled,
continuous boost Power Factor Corrector (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM can be used in either current or voltage
mode. In voltage mode, feedforward from the PFC output
buss can be used to improve the PWM’s line regulation. In
either mode, the PWM stage uses conventional trailing­edge duty cycle modulation, while the PFC uses leading­edge modulation. This patented leading/trailing edge
modulation technique results in a higher useable PFC
error amplifier bandwidth, and can significantly reduce
the size of the PFC DC buss capacitor.

The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the controlled ripple on
the PFC output capacitor (the PWM input capacitor). The
PWM section of both the ML4827-1 and the ML4827-2 run
at the same frequency as the PFC.

A number of protection features have been built into the
ML4827 to insure the final power supply will be as
reliable as possible. These include TriFault Detect, soft­start, PFC over-voltage protection, peak current limiting,
brown-out protection, duty cycle limit, and under-voltage
lockout.

TRI-FAULT DETECT PROTECTION

Many power supplies manufactured for sale in the US
must meet Underwriter’s Laboratories (UL) standards. UL’s
specification UL1950 requires that no unsafe condition
may result from the failure of any single circuit
component. Typical system designs include external
active and passive circuitry to meet this requirement.
TriFault Detect is an on-chip feature of the ML4827 that
monitors the VFB pin for overvoltage, undervoltage, or
floating conditions which indicate that a component of
the feedback path may have failed. In such an event, the
PFC supply output will be disabled. These integrated
redundant protections assure system compliance with
UL1950 requirements.

POWER FACTOR CORRECTION

Power factor correction makes a nonlinear load look like
a resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with and proportional to
the line voltage, so the power factor is unity (one). A
common class of nonlinear load is the input of most
power supplies, which use a bridge rectifier and
capacitive input filter fed from the line. The peak­charging effect which occurs on the input filter capacitor
in these supplies causes brief high-amplitude pulses of
current to flow from the power line, rather than a
sinusoidal current in phase with the line voltage. Such
supplies present a power factor to the line of less than one
(i.e. they cause significant current harmonics of the power
line frequency to appear at their input). If the input
current drawn by such a supply (or any other nonlinear
load) can be made to follow the input voltage in

instantaneous amplitude, it will appear resistive to the AC
line and a unity power factor will be achieved.

To hold the input current draw of a device dra wing power
from the AC line in phase with and proportional to the
input voltage, a way must be found to prevent that device
from loading the line except in proportion to the
instantaneous line voltage. The PFC section of the
ML4827 uses a boost-mode DC-DC converter to
accomplish this. The input to the converter is the full
wave rectified AC line voltage. No bulk filtering is
applied following the bridge rectifier, so the input voltage
to the boost converter ranges (at twice line frequency)
from zero volts to the peak value of the AC input and
back to zero. By forcing the boost converter to meet two
simultaneous conditions, it is possible to ensure that the
current which the converter draws from the power line
agrees with the instantaneous line voltage. One of these
conditions is that the output voltage of the boost converter
must be set higher than the peak value of the line
voltage. A commonly used value is 385VDC, to allow for
a high line of 270VAC
current which the converter is allowed to draw from the
line at any given instant must be proportional to the line
voltage. The first of these requirements is satisfied by
establishing a suitable voltage control loop for the
converter, which in turn drives a current error amplifier
and switching output driver. The second requirement is
met by using the rectified AC line voltage to modulate
the output of the voltage control loop. Such modulation
causes the current error amplifier to command a power
stage current which varies directly with the input voltage.
In order to prevent ripple which will necessarily appear at
the output of the boost circuit (typically about 10VAC on
a 385V DC level) from introducing distortion back through
the voltage error amplifier, the bandwidth of the voltage
loop is deliberately kept low. A final refinement is to
adjust the overall gain of the PFC such to be proportional
to 1/V
system as the AC input voltage varies.

Since the boost converter topology in the ML4827 PFC is
of the current-averaging type, no slope compensation is
required.

PFC SECTION

Gain Modulator

Figure 1 shows a block diagram of the PFC section of the
ML4827. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the
current loop to line voltage waveform and frequency,
RMS line voltage, and PFC output voltage. There are three
inputs to the gain modulator. These are:

1) A current representing the instantaneous input voltage

2

, which linearizes the transfer function of the

IN

(amplitude and waveshape) to the PFC. The rectified
AC input sine wave is converted to a proportional
current via a resistor and is then fed into the gain

. The other condition is that the

rms

7

ML4827

FUNCTIONAL DESCRIPTION (Continued)

modulator at IAC. Sampling current in this way
minimizes ground noise, as is required in high power
switching power conversion en vironments. T he gain
modulator responds linearly to this current.

V

REF

2) A voltage proportional to the long-term RMS AC line

voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the gain
modulator at V
inversely proportional to V
low values of V

. The gain modulator’s output is

RMS

where special gain contouring

RMS

2

(except at unusually

RMS

takes over, to limit power dissipation of the circuit
components under heavy brownout conditions). T he
relationship between V

and gain is termed K, and is

RMS

illustrated in the Typical Performance Characteristics.

3) The output of the voltage error amplifier, VEAO. The

gain modulator responds linearly to variations in this
voltage.

The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way
the gain modulator forms the reference for the current
error loop, and ultimately controls the instantaneous
current draw of the PFC from the power line. The general
form for the output of the gain modulator is:

I

GAINMOD

=

V

RMS

´

V

1

2

(1)

´

IVEAO

AC

More exactly, the output current of the gain modulator is
given by:

PFC

OUTPUT

V

FB

15

2.5V

I

AC

2

V

4

I

SENSE

3

–
+

RMS

VEAO

VEA

MODULATOR

16

GAIN

1

IEAO

IEA

+
–

+
–

Figure 2. Compensation Network Connections for the

Voltage and Current Error Amplifiers

arrangement of the duty cycle modulator polarities
internal to the PFC, an increase in positive current from
the gain modulator will cause the output stage to increase
its duty cycle until the voltage on I

is adequately

SENSE

negative to cancel this increased current. Similarly, if the
gain modulator’s output decreases, the output duty cycle
will decrease, to achieve a less negative voltage on the
I

pin.

SENSE

I K VEAO V I

GAINMOD AC

=´ - ´(.)15

where K is in units of V-1.
Note that the output current of the gain modulator is

limited to ≅ 200µA.

Current Error Amplifier

The current error amplifier’s output controls the PFC duty
cycle to keep the average current through the boost
inductor a linear function of the line voltage. At the
inverting input to the current error amplifier, the output
current of the gain modulator is summed with a current
which results from a negative voltage being impressed
upon the I
The negative voltage on I

pin (current into I

SENSE

≅ V

SENSE

represents the sum of all

SENSE

SENSE

/3.5kΩ).

currents flowing in the PFC circuit, and is typically
derived from a current sense resistor in series with the
negative terminal of the input bridge rectifier. In higher
power applications, two current transformers are
sometimes used, one to monitor the ID of the boost
MOSFET(s) and one to monitor the IF of the boost diode.
As stated above, the inverting input of the current error
amplifier is a virtual ground. Given this fact, and the

Cycle-By-Cycle Current Limiter

The I

pin, as well as being a part of the current

SENSE

feedback loop, is a direct input to the cycle-by-cycle
current limiter for the PFC section. Should the input
voltage at this pin ever be more negative than -1V, the
output of the PFC will be disabled until the protection
flip-flop is reset by the clock pulse at the start of the next
PFC power cycle.

Overvoltage Protection

The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load
should suddenly change. A resistor divider from the high
voltage DC output of the PFC is fed to VFB. When the
voltage on VFB exceeds 2.7V, the PFC output driver is shut
down. The PWM section will continue to operate. The
OVP comparator has 125mV of hysteresis, and the PFC
will not restart until the voltage at VFB drops below 2.58V.
The VFB should be set at a level where the active and
passive external power components and the ML4827 are
within their safe operating voltages, but not so low as to
interfere with the boost voltage regulation loop.

8

FUNCTIONAL DESCRIPTION (Continued)

ML4827

Error Amplifier Compensation

The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the
types of compensation networks most commonly used for
the voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to V
the PFC: as the reference voltage comes up from zero
volts, it creates a differentiated voltage on IEAO which
prevents the PFC from immediately demanding a full duty
cycle on its boost converter.

There are two major concerns when compensating the
voltage loop error amplifier; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest
anticipated international power frequency). The gain vs.
input voltage of the ML4827’s voltage error amplifier has
a specially shaped nonlinearity such that under steady­state operating conditions the transconductance of the
error amplifier is at a local minimum. Rapid perturbations
in line or load conditions will cause the input to the
voltage error amplifier (VFB) to deviate from its 2.5V
(nominal) value. If this happens, the transconductance of
the voltage error amplifier will increase significantly, as
shown in the Typical Performance Characteristics. This
raises the gain-bandwidth product of the voltage loop,
resulting in a much more rapid voltage loop response to
such perturbations than would occur with a conventional
linear gain characteristic.

The current amplifier compensation is similar to that of
the voltage error amplifier with the exception of the
choice of crossover frequency. The crossover frequency of
the current amplifier should be at least 10 times that of
the voltage amplifier, to prevent interaction with the
voltage loop. It should also be limited to less than 1/6th
that of the switching frequency, e.g. 16.7kHz for a
100kHz switching frequency.

There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be
the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier.

to produce a soft-start characteristic on

REF

Oscillator (RAMP 1)

The oscillator frequency is determined by the values of R
and CT, which determine the ramp and off-time of the
oscillator output clock:

=

f

OSC

tt

RAMP DEADTIME

The deadtime of the oscillator is derived from the
following equation:

=´´

tCRIn

RAMP T T

at V

= 7.5V:

REF

=´´

tCR

RAMP T T

The deadtime of the oscillator may be determined using:

t

DEADTIME T T

The deadtime is so small (t
operating frequency can typically be approximated by:

=

f

OSC

t

RAMP

EXAMPLE:
For the application circuit sho wn in the data sheet, with
the oscillator running at:

==100

fkHz

OSC

=´´ =´

tCR

RAMP T T

Solving for RT x CT yields 2 x 10-4. Selecting standard
components values, CT = 470pF, and RT = 41.2kΩ.

The deadtime of the oscillator adds to the Maximum
PWM Duty Cycle (it is an input to the Duty Cycle
Limiter). With zero oscillator deadtime, the Maximum
PWM Duty Cycle is typically 45% for the ML4827-1. In
many applications of the ML4827-1, care should be taken
that CT not be made so large as to extend the Maximum
Duty Cycle beyond 50%. This can be accomplished by
using a stable 470pF capacitor for CT.

1

+

F

V

REF

G

V

H

REF

051.

V

25

.

=´=´

51

.

1

CC

mA

t

RAMP

490

RAMP

1

051110

.

125

-

375..

-

>> t

I

J

K

DEADTIME

-

5

(2)

(3)

(4)

) that the

(5)

T

For more information on compensating the current and
voltage control loops, see Application Notes 33 and 34.
Application Note 16 also contains valuable information
for the design of this class of PFC.

9

ML4827

FUNCTIONAL DESCRIPTION (Continued)

PWM SECTION

Pulse Width Modulator

The PWM section of the ML4827 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing. The PWM is capable of current-mode or voltage
mode operation. In current-mode applications, the PWM
ramp (RAMP 2) is usually derived directly from a current
sensing resistor or current transformer in the primary of the
output stage, and is thereby representative of the current
flowing in the converter’s output stage. DC I
provides cycle-by-cycle current limiting, is typically
connected to RAMP 2 in such applications. For voltage­mode operation or certain specialized applications,
RAMP 2 can be connected to a separate RC timing
network to generate a voltage ramp against which VDC
will be compared. Under these conditions, the use of
voltage feedforward from the PFC buss can assist in line
regulation accuracy and response. As in current mode
operation, the DC I
stage overcurrent protection.

No voltage error amplifier is included in the PWM stage
of the ML4827, as this function is generally performed on
the output side of the PWM’s isolation boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into the PWM’s RAMP 2 input which
allows VDC to command a zero percent duty cycle for
input voltages below 1.25V.

Maximum Duty Cycle

In the ML4827-1, the maximum duty cycle of the PWM
section is limited to 50% for ease of use and design. In
the case of the ML4827-2, the maximum duty cycle of
the PWM section is extended to 70% (typical) for
enhanced utilization of the inductor. Operation at 70%
duty cycle requires special care in circuit design to avoid
volt-second imbalances, and/or high-voltage damage to
the PWM switch transistor(s).

Using the ML4827-2

The ML4827-2’s higher PWM duty cycle offers several
design advantages that skilled power supply and
magnetics engineers can take advantage of, including:

• Reduced RMS and peak PWM switch currents

• Reduced RMS and peak PWM transformer
currents

• Easier RFI/EMI filtering due to lower peak
currents

These reduced currents can result in cost savings by
allowing smaller PWM transformer primary windings and

input would is used for output

LIMIT

LIMIT

, which

fewer turns on forward converter reset windings. Long
duty cycles, by allowing greater utilization of the PFC’s
stored charge, can also lower the cost of PFC bus
capacitors while still offering long “hold-up” times.

NOTE: during the time when the PWM switch is off (the
reset or flyback periods), increasing duty cycles will result
in rapidly increasing peak voltages across the switch.
This result of high PWM duty cycles requires greater care
be used in circuit design. Relevant design issues include:

• Higher voltage (>1000V) PWM switches

• More carefully designed and tested PWM
transformers

• Clamps and/or snubbers when needed

Also, slope compensation will be required in most current
mode PWM designs.

For those who want to approach the limits of attainable
performance (most commonly high-volume, low-cost
supplies), the ML4827-2’s 70% maximum PWM duty
cycle offers several desirable design capabilities. Using a
70% duty cycle makes it essential to perform a careful
magnetics design and component stress analysis before
finalizing designs with the ML4827-2.

THE ML4827-2: SPECIAL CONSIDERATIONS FOR HIGH
DUTY CYCLES

The use of the ML4827-1, especially with the type of
PWM output stage shown in the Application Circuit of
Figure 6, is straightforward due to the limitation of the
PWM duty cyle to 50% maximum. In fact, one of the
advantages of the “two-transistor single-ended forward
converter” shown in Figure 6 is that it will necessarily
reset the core, with no additional winding required, as
long as the core does not go into saturation during the
topology's maximum permissible 50% duty cycle.

For the “-2” version of the ML4827, the maximum duty
cycle (δ) of the PWM is nominally 70%. As the two­transistor single-ended forward converter cannot be used
at duty cycles greater than 50%, high-δ applications
require the use of either a single-transistor forward
converter (with a transformer reset winding), or a flyback
output stage. In either case, special concerns arise
regarding the peak voltage appearing on the PWM switch
transistor, the PWM output transformer , and associated
power components as the duty cycle increases. For any
output stage topology, the available on-time (core “set”
time) is (1/f
the PWM output transformer is (1/f
means that the magnetizing inductance of the core
charges for a period of (1/f
completely discharged during a period of (1/f
(1–δ). The ratio of these two periods, multiplied by the
maximum value of the PFC’s V

) x δ, while the reset time for the core of

PWM

) x δ, and must be

PWM

BUSS

) x (1–δ). This

PWM

PWM

, yields the minimum

) x

10

FUNCTIONAL DESCRIPTION (Continued)

ML4827

voltage for which the PWM output transistor must be
rated. Frequently, the design of the tranformer’s reset
winding, and/or of the output transistor’ s snubbers or
clamps, require an additional voltage margin of 100V to
200V.

To put some numbers into the discussion, with a given
V

BUSS(MAX)

1. For δ = 50%: V

of 400V:

RESET

= {[(1/f

PWM

) x δ]/[(1/f

PWM

) x

(1–δ)]} x 400V = 0.50/0.50 x 400V = 400V

2. For δ = 55%: V

3. For δ = 60%: V

4. For δ = 64% (Data Sheet Lower Limit Value): V

= 0.55/0.45 x 400V = 489V

RESET

= 0.60/0.40 x 400V = 600V

RESET

RESET

0.64/0.36 x 400V = 711V

5. For δ = 70%: V

6. For δ = 74% (Data Sheet Upper Limit Value): V

= 0.70/0.30 x 400V = 933V

RESET

RESET

0.74/0.26 x 400V = 1138V

It is economically desirable to design for the lowest
meaningful voltage on the output MOSFET. It is
simultaneously necessary to design the circuit to operate

=

=

at the lowest guaranteed value for δ, to ensure that the
magnetics will deliver full output power with any
individual ML4827. In actual operation, the choice of

δ

= 60% will allow some tolerance for the timing

MIN

capacitors and resistors. A tolerance on (R
C

) of ±2% is the simplest “brute force” way to

RAMP2

RAMP2

x

achieve the desired result. This should be combined with
an external duty cycle clamp. This protects the PWM
circuitry against the condition in which the output has
been shorted, and the error amplifier output (VDC) would
otherwise be driven to its upper rail. One method which
works well when the PWM is used in voltage mode is to
limit the maximum input to the PWM feedback voltage
(VDC). If the voltage available to this pin is derived from
the ML4827’s 7.5V V

, it will be in close ratio to the

REF

charging time of the RAMP2 capacitor. This will be true
whether the RAMP2 capacitor is charged from V

REF

, or, as
is more commonly done in voltage-mode applications,
from the output of the PFC Stage (the “feedforward”
configuration). Figure 3 shows such a duty cycle clamp.

If the ML4827-2’s PWM is to be used in a current-mode
design, the PWM stage will require slope compensation.
This can be done by any of the standard industry
techniques. Note that the ramp to use for this slope
compensation is the voltage on RAMP1.

PWM

ERROR

AMP

R

RAMP2

C

RAMP2

R1

PFC V

BUSS

R

FB1

V

FB

R

FB2

RAMP2

V

REF

V

DC

R2

R2 V

δ

MAX

REF

= V

R1 + R

2

RAMP2 (PEAK)

Figure 3. ML4827- PWM Duty Cycle Clamp for Voltage-Made Operation

11

ML4827

FUNCTIONAL DESCRIPTION (Continued)

FUNCTIONAL DESCRIPTION (Continued)

Using the recommended values of δ

= 60% and δ

MIN

MAX

= 64% for a high-δ application, a MOSFET switch with a
Drain-Source breakdown voltage of 900V, or in some
cases as low as 800V, can reliably be used. Such parts are
readily and inexpensively available from a number of
vendors.

VIN OK Comparator

The V

OK comparator monitors the DC output of the

IN

PFC and inhibits the PWM if this voltage on VFB is less
than its nominal 2.5V. Once this voltage reaches 2.5V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start begins.

PWM Control (RAMP 2)

When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
timing components (R

RAMP2

, C

), which will have a

RAMP2

minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,
feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.

Soft Start

It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.

Solving for the minimum value of CSS:

50

A

CC

125

.

µ

V

220

nF

=× ≅5

Cms

SS

Generating V

The ML4827 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the
voltage internal to the part at 13.5V. This allows a low
power dissipation while at the same time delivering 10V
of gate drive at the PWM OUT and PFC OUT outputs. It is
important to limit the current through the part to avoid
overheating or destroying it. This can be easily done with
a single resistor in series with the VCC pin, returned to a
bias supply of typically 18V to 20V. The resistor’s value
must be chosen to meet the operating current requirement
of the ML4827 itself (19mA max) plus the current required
by the two gate driver outputs.

EXAMPLE:
With a V

of 20V, a VCC limit of 14.6V (max) and the

BIAS

ML4827 driving a total gate charge of 110nC at 100kHz
(e.g., 1 IRF840 MOSFET and 2 IRF830 MOSFETs), the
gate driver current required is:

Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA
supplies the charging current for the capacitor, and start­up of the PWM begins at 1.25V. Start-up delay can be
programmed by the following equation:

A

=´

Ct

SS DELAY

50
125µ.

V

(6)

where CSS is the required soft start capacitance, and
t

is the desired start-up delay.

DELAY

V

BIAS

R

BIAS

V

CC

ML4827

GND

IkHznCmA

GATEDRIVE

R

BIAS

=´=100 100 11

-

VV

20 146

=

mA mA

19 11

.

+

=

180

Ω

To check the maximum dissipation in the ML4827, find
the current at the minimum VCC (12.4V):

=

I

CC

180

=

mA

Ω

422..

-

VV

20 124

The maximum allowable ICC is 55mA, so this is an
acceptable design.

10nF

CERAMIC

1µF

CERAMIC

(7)

(8)

(9)

12

Figure 4. External Component Connections to V

CC

FUNCTIONAL DESCRIPTION (Continued)

ML4827

The ML4827 should be locally b ypassed with a 10nF and
a 1µF ceramic capacitor. In most applications, an
electrolytic capacitor of between 100µF and 330µF is also
required across the part, both for filtering and as part of
the start-up bootstrap circuitry.

LEADING/TRAILING MODULATION

Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the

SW2

SW1

+
–

U1

I2 I3

I4

C1

R

D

+

DC

VIN

L1
I1

REF

OSC

U4

U3

+

EA

–

RAMP

CLK

trailing edge modulation is determined during the ON
time of the switch. Figure 5 shows a typical trailing edge
control scheme.

In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 6
shows a leading edge control scheme.

One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With

DFF

U2

CLK

RL

Q

Q

RAMP

VSW1

VEAO

TIME

+

DC

VIN

Figure 5. Typical Trailing Edge Control Scheme.

SW2

SW1

+
–

CMP

U1

I2 I3

I4

C1

R
D

DFF

U2

CLK

RL

Q

Q

L1
I1

REF

OSC

U4

U3

+

EA

–

RAMP

CLK

VEAO

Figure 6. Typical Leading Edge Control Scheme.

TIME

RAMP

VEAO

TIME

VSW1

TIME

13

ML4827

LEADING/TRAILING MOD. (Continued)

such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC’s output
ripple voltage can be reduced by as much as 30% using
this method.

AC INPUT

85 TO 265VAC

C3

470nF

C2

470nF

F1

3.15A

R2A

357kΩ

R2B

357kΩ

D12

1N5401

D13

1N5401

C19
1µF

R1A

499kΩ

499kΩ

R3

75kΩ

R4

13kΩ

R1B

R27

39kΩ

2W

C30

330µF

470pF

1

2

3

4

5

6

7

8

C18

3.1mH

Q1

IRF840

R12

27kΩ

IEAO

I

AC

I

SENSE

V

RMS

SS

V

DC

RAMP 1

RAMP 2

L1

R21
22Ω

C7

220pF

PWM OUT

DC I

ML4827-1

41.2kΩ

D1

8A, 600V,

"FRED" Diode

C4

10nF

R28

180Ω

C12

10µF

C6

1nF

16

VEAO

15

V

FB

14

V

REF

13

V

CC

12

PFC OUT

11

10

GND

LIMIT

R6

9

BYV26C

R10

6.2kΩ

BR1

4A, 600V

R5

300mΩ

1W

C1

470nF

D3

R7A

178kΩ

R7B

178kΩ

TYPICAL APPLICATIONS

Figure 7 is the application circuit for a complete 100W
power factor corrected power supply. This circuit was
designed using the methods and topology detailed in
Application Note 33.

Q2

IRF830

C25

R14
33Ω

220Ω

T1

R19

C15

10nF

R17

33Ω

R30

4.7kΩ

D10

1N5818

Q3

IRF830

C16
1µF

D7

15V

BYV26C

R20

1.1Ω

100nF

C13

D6

D5

BYV26C

10kΩ

10kΩ

TL431

R26

C31

1nF

L2

33µH

C21

1800µF

D11

MBR2545CT

T2

R23

1.5kΩ

MOC
8102

R8

C14

2.37kΩ

1µF

L1: Premier Magnetics #TSD-734
L2: 33µH, 10A DC
T1: Premier Magnetics #TSD-736
T2: Premier Magnetics #TSD-735

Premier Magnetics: [phone]

C5

100µF

D8

1N5818

C17

220pF

100nF

R15

3Ω

C20
1µF

C22

4.7µF

C23

100nF

R11

750kΩ

C8

82nF

C24

1.2kΩ

R18

220Ω

9W

1µF

R24

C9

8.2nF

12VDC

RTN

R22

8.66kΩ

R25

2.26kΩ

14

C11

10nF

Figure 7. 100W Power Factor Corrected Power Supply, Designed Using Micro Linear Application Note 33.

PHYSICAL DIMENSIONS inches (millimeters)

Package: P16

16-Pin PDIP

0.740 - 0.760

(18.79 - 19.31)

16

ML4827

0.02 MIN
(0.50 MIN)
(4 PLACES)

0.170 MAX

(4.32 MAX)

0.125 MIN
(3.18 MIN)

16

PIN 1 ID

1

0.055 - 0.065
(1.40 - 1.65)

0.016 - 0.022
(0.40 - 0.56)

0.386 - 0.396
(9.80 - 10.06)

0.240 - 0.260
(6.09 - 6.61)

0.100 BSC
(2.54 BSC)

0.015 MIN
(0.38 MIN)

SEATING PLANE

Package: S16N

16-Pin Narrow SOIC

0.295 - 0.325
(7.49 - 8.26)

0º - 15º

0.008 - 0.012
(0.20 - 0.31)

0.017 - 0.027
(0.43 - 0.69)

(4 PLACES)

0.055 - 0.061
(1.40 - 1.55)

1

PIN 1 ID

0.050 BSC
(1.27 BSC)

0.012 - 0.020
(0.30 - 0.51)

0.148 - 0.158
(3.76 - 4.01)

0.059 - 0.069
(1.49 - 1.75)

SEATING PLANE

0.228 - 0.244
(5.79 - 6.20)

0.004 - 0.010
(0.10 - 0.26)

0º - 8º

0.015 - 0.035
(0.38 - 0.89)

0.006 - 0.010
(0.15 - 0.26)

15

ML4827

ORDERING INFORMATION

PART NUMBER MAX DUTY CYCLE TEMPERATURE RANGE PACKAGE

ML4827CP-1 50% 0°C to 70°C 16-Pin PDIP (P16)
ML4827CP-2 74 % 0°C to 70°C 16-Pin PDIP (P16)
ML4827CS-1 50% 0°C to 70°C 16-Pin Narrow SOIC (S16N)
ML4827CS-2 74% 0°C to 70°C 16-Pin Narrow SOIC (S16N)

ML4827IP-150%–40°C to 85°C16-Pin PDIP (P16) (EOL)

ML4827IP-2 74% –40°C to 85°C 16-Pin PDIP (P16)

ML4827IS-150%–40°C to 85°C16-Pin Narrow SOIC (S16N) (EOL)

ML4827IS-2 74% –40°C to 85°C 16-Pin Narrow SOIC (S16N)

© Micro Linear 1998. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502;

5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897;
5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669;
5,825,165; 5,825,223; 5,838,723. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability
arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits
contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits
infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult
with appropriate legal counsel before deciding on a particular application.

16

2092 Concourse Drive

San Jose, CA 95131

T el: [phone]

Fax: [phone]

www .microlinear .com

DS4827-01