Datasheet ML4824CS1 Datasheet (Fairchild Semiconductor)

December 2000

ML4824

P ow er F actor Correction and PWM Contr oller Combo

GENERAL DESCRIPTION

The ML4824 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching
FETs, and results in a power supply that fully complies
with IEC1000-2-3 specification. The ML4824 includes
circuits for the implementation of a leading edge, average
current, “boost” type power factor correction and a trailing
edge, pulse width modulator (PWM).

The device is available in two versions; the ML4824-1

= f

(f

PWM

) and the ML4824-2 (f

PFC

PWM

= 2 x f

PFC

).
Doubling the switching frequency of the PWM allows the
user to design with smaller output components while
maintaining the best operating frequency for the PFC. An
over-voltage comparator shuts down the PFC section in the
event of a sudden decrease in load. The PFC section also
includes peak current limiting and input voltage brown­out protection. The PWM section can be operated in
current or voltage mode at up to 250kHz and includes a
duty cycle limit to prevent transformer saturation.

BLOCK DIAGRAM

15

2

4

3

7

8

6

5

9

V

FB

2.5V

I

AC

V

RMS

I

SENSE

RAMP 1

RAMP 2

V

DC

V

SS

DC I

LIMIT

CC

VEA

–
+

8V

50µA

8V

16

VEAO

GAIN

MODULATOR

1.25V

3.5kΩ

IEA

+
–

3.5kΩ

–
+

1

IEAO

+
–

OSCILLATOR

(-2 VERSION ONLY)

–
+

POWER FACTOR CORRECTOR

x 2

V

–

FB

2.5V

+

PULSE WIDTH MODULATOR

FEATURES

■ Internally synchronized PFC and PWM in one IC

■ Low total harmonic distortion

■ Reduces ripple current in the storage capacitor between

the PFC and PWM sections

■ Average current, continuous boost leading edge PFC

■ Fast transconductance error amp for voltage loop

■ High efficiency trailing edge PWM can be configured

for current mode or voltage mode operation

■ Average line voltage compensation with brownout

control

■ PFC overvoltage comparator eliminates output

“runaway” due to load removal

■ Current fed gain modulator for improved noise immunity

■ Overvoltage protection, UVLO, and soft start

13

V

CC

7.5V

PFC OUT

PWM OUT

DUTY CYCLE

VIN OK

LIMIT

2.7V

–1V

1V

OVP

+
–

+
–

PFC I

–
+

LIMIT

DC I

LIMIT

V

CCZ

V

CCZ

13.5V
REFERENCE

SRQ

Q

SRQ

Q

SRQ

Q

UVLO

V

REF

14

12

11

REV. 1.01 12/7/2000

ML4824

PIN CONFIGURATION

PIN DESCRIPTION

ML4824

16-Pin PDIP (P16)

16-Pin Wide SOIC (S16W)

IEAO

I

AC

I

SENSE

V

RMS

V

DC

RAMP 1

RAMP 2

SS

1

2

3

4

5

6

7

8

TOP VIEW

16

VEAO

15

V

FB

14

V

REF

13

V

CC

12

PFC OUT

11

PWM OUT

10

GND

9

DC I

LIMIT

PIN NAME FUNCTION

1 IEAO PFC transconductance current error

amplifier output

2I

AC

3I

SENSE

PFC gain control reference input

Current sense input to the PFC current
limit comparator

4V

RMS

Input for PFC RMS line voltage
compensation

5 SS Connection point for the PWM soft start

capacitor

6V

DC

PWM voltage feedback input

7 RAMP 1 Oscillator timing node; timing set

by R

TCT

8 RAMP 2 When in current mode, this pin

functions as as the current sense input;
when in voltage mode, it is the PWM
input from PFC output (feed forward
ramp).

PIN NAME FUNCTION

9 DC I

LIMIT

PWM current limit comparator input

10 GND Ground

11 PWM OUT PWM driver output

12 PFC OUT PFC driver output

13 V

CC

Positive supply (connected to an
internal shunt regulator)

14 V

REF

Buffered output for the internal 7.5V
reference

15 V

FB

PFC transconductance voltage error
amplifier input

16 VEAO PFC transconductance voltage error

amplifier output

2 REV. 1.01 12/7/2000

ABSOLUTE MAXIMUM RATINGS

ML4824

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.

Junction Temperature.............................................. 150°C

Storage Temperature Range ..................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ..................... 260°C

Thermal Resistance (θ

)

JA

Plastic DIP ....................................................... 80°C/W

V

Shunt Regulator Current .................................. 55mA

CC

Voltage.................................................. –3V to 5V

I

SENSE

Voltage on Any Other Pin ... GND – 0.3V to V

............................................................................................

I

REF

I

Input Current .................................................... 10mA

AC

CCZ

+ 0.3V

20mA

Peak PFC OUT Current, Source or Sink ................ 500mA

Peak PWM OUT Current, Source or Sink .............. 500mA

PFC OUT, PWM OUT Energy Per Cycle .................. 1.5µJ

Plastic SOIC ................................................... 105°C/W

OPERATING CONDITIONS

Temperature Range

ML4824CX................................................. 0°C to 70°C

ML4824IX .............................................. –40°C to 85°C

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, ICC = 25mA, R

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOLTAGE ERROR AMPLIFIER

Input Voltage Range 0 7 V

Transconductance V

Feedback Reference Voltage 2.46 2.53 2.60 V

= 52.3kΩ, C

T

= 470pF, TA = Operating Temperature Range (Note 1)

T

= V

NON INV

, VEAO = 3.75V 50 85 120 µ

INV

Ω

Input Bias Current Note 2 -0.3 –1.0 µA

Output High Voltage 6.0 6.7 V

Output Low Voltage 0.6 1.0 V
Source Current ∆VIN = ±0.5V, V
Sink Current ∆VIN = ±0.5V, V

Open Loop Gain 60 75 dB

Power Supply Rejection Ratio V

CURRENT ERROR AMPLIFIER

Input Voltage Range –1.5 2 V

Transconductance V

Input Offset Voltage 0 8 15 mV

Input Bias Current –0.5 –1.0 µA

Output High Voltage 6.0 6.7 V

Output Low Voltage 0.6 1.0 V
Source Current ∆VIN = ±0.5V, V
Sink Current ∆VIN = ±0.5V, V

Open Loop Gain 60 75 dB

Power Supply Rejection Ratio V

- 3V < VCC < V

CCZ

NON INV

CCZ

= V

- 3V < VCC < V

= 6V –40 –80 µA

OUT

= 1.5V 40 80 µA

OUT

- 0.5V 60 75 dB

CCZ

, VEAO = 3.75V 130 195 310 µ

INV

= 6V –40 –90 µA

OUT

= 1.5V 40 90 µA

OUT

- 0.5V 60 75 dB

CCZ

Ω

REV. 1.01 12/7/2000 3

ML4824

ELECTRICAL CHARACTERISTICS (Continued)

SMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

OVP COMPARATOR

Threshold Voltage 2.6 2.7 2.8 V

Hysteresis 80 115 150 mV

PFC I

COMPARATOR

LIMIT

Threshold Voltage –0.8 –1.0 –1.15 V
∆(PFC I

LIMIT VTH

Delay to Output 150 300 ns

DC I

COMPARATOR

LIMIT

Threshold Voltage 0.97 1.02 1.07 V

Input Bias Current ±0.3 ±1 µA

Delay to Output 150 300 ns

VIN OK COMPARATOR

Threshold Voltage 2.4 2.5 2.6 V

Hysteresis 0.8 1.0 1.2 V

GAIN MODULATOR

Gain (Note 3) IAC = 100µA, V

Bandwidth IAC = 100µA 10 MHz

Output Voltage I

OSCILLATOR

- Gain Modulator Output) 100 190 mV

= VFB = 0V 0.36 0.55 0.66

RMS

IAC = 50µA, V

IAC = 50µA, V

IAC = 100µA, V

= 250µA, V

AC

= 1.2V, VFB = 0V 1.20 1.80 2.24

RMS

= 1.8V, VFB = 0V 0.55 0.80 1.01

RMS

= 3.3V, VFB = 0V 0.14 0.20 0.26

RMS

= 1.15V, 0.74 0.82 0.90 V

RMS

VFB = 0V

Initial Accuracy TA = 25°C 71 76 81 kHz

Voltage Stability V

- 3V < VCC < V

CCZ

- 0.5V 1 %

CCZ

Temperature Stability 2%

Total Variation Line, Temp 68 84 kHz

Ramp Valley to Peak Voltage 2.5 V

Dead Time PFC Only 270 370 470 ns

CT Discharge Current V

RAMP 2

= 0V, V

= 2.5V 4.5 7.5 9.5 mA

RAMP 1

REFERENCE

Output Voltage TA = 25°C, I(V

Line Regulation V

- 3V < VCC < V

CCZ

Load Regulation 1mA < I(V

) = 1mA 7.4 7.5 7.6 V

REF

- 0.5V 2 10 mV

CCZ

) < 20mA 2 15 mV

REF

Temperature Stability 0.4 %

Total Variation Line, Load, Temp 7.35 7.65 V

Long Term Stability TJ = 125°C, 1000 Hours 5 25 mV

4 REV. 1.01 12/7/2000

ML4824

ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PFC

PWM

SUPPLY

Minimum Duty Cycle V

Maximum Duty Cycle V

Output Low Voltage I

Output High Voltage I

> 4.0V 0 %

IEAO

< 1.2V 90 95 %

IEAO

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.8 2.0 V

OUT

I

= 10mA, VCC = 8V 0.7 1.5 V

OUT

= 20mA 10 10.5 V

OUT

I

= 100mA 9.5 10 V

OUT

Rise/Fall Time CL = 1000pF 50 ns

Duty Cycle Range ML4824-1 0-44 0-47 0-50 %

ML4824-2 0-37 0-40 0-45 %

Output Low Voltage I

Output High Voltage I

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.8 2.0 V

OUT

I

= 10mA, VCC = 8V 0.7 1.5 V

OUT

= 20mA 10 10.5 V

OUT

I

= 100mA 9.5 10 V

OUT

Rise/Fall Time CL = 1000pF 50 ns

Shunt Regulator Voltage (V

V

Load Regulation 25mA < ICC < 55mA ±100 ±300 mV

CCZ

V

Total Variation Load, Temp 12.4 14.6 V

CCZ

) 12.8 13.5 14.2 V

CCZ

Start-up Current VCC = 11.8V, CL = 0 0.7 1.0 mA

Operating Current VCC < V

- 0.5V, CL = 0 16 19 mA

CCZ

Undervoltage Lockout Threshold 12 13 14 V

Undervoltage Lockout Hysteresis 2.7 3.0 3.3 V

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Includes all bias currents to other circuits connected to the V
Note 3: Gain = K x 5.3V; K = (I

GAINMOD

- I

) x IAC x (VEAO - 1.5V)-1.

OFFSET

pin.

FB

REV. 1.01 12/7/2000 5

ML4824

TYPICAL PERFORMANCE CHARACTERISTICS

250

200

Ω

150

100

TRANSCONDUCTANCE (µ )

50

0

053

142

VFB (V)

250

200

Ω

150

100

TRANSCONDUCTANCE (µ )

50

0
–500 5000

IEA INPUT VOLTAGE (mV)

V oltage Err or Amplifier (VEA) Transconductance (gm) Current Error Amplifier (IEA) Tr ansconductance (gm)

400

300

15

2

4

3

7

V

FB

2.5V

I

AC

V

RMS

I

SENSE

RAMP 1

VEAO

VEA

–
+

MODULATOR

16

GAIN

3.5kΩ

200

100

VARIABLE GAIN BLOCK CONSTANT - K

0

053142

V

(mV)

RMS

Gain Modulator Transfer Char acteristic (K)

1

IEAO

IEA

+

–

3.5kΩ

+
–

OSCILLATOR

2.7V

–1V

OVP

+
–

+
–

PFC I

LIMIT

SRQ

SRQ

Q

PFC OUT

12

Q

Figure 1. PFC Section Block Diagram.

6 REV. 1.01 12/7/2000

FUNCTIONAL DESCRIPTION

ML4824

The ML4824 consists of an average current controlled,
continuous boost Power Factor Corrector (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM can be used in either current or voltage
mode. In voltage mode, feedforward from the PFC output
buss can be used to improve the PWM’s line regulation. In
either mode, the PWM stage uses conventional trailing­edge duty cycle modulation, while the PFC uses leading­edge modulation. This patented leading/trailing edge
modulation technique results in a higher useable PFC error
amplifier bandwidth, and can significantly reduce the size
of the PFC DC buss capacitor.

The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the controlled ripple on
the PFC output capacitor (the PWM input capacitor). The
PWM section of the ML4824-1 runs at the same frequency
as the PFC. The PWM section of the ML4824-2 runs at
twice the frequency of the PFC, which allows the use of
smaller PWM output magnetics and filter capacitors while
holding down the losses in the PFC stage power
components.

In addition to power factor correction, a number of
protection features have been built into the ML4824. These
include soft-start, PFC over-voltage protection, peak
current limiting, brown-out protection, duty cycle limit,
and under-voltage lockout.

POWER FACTOR CORRECTION

converter to meet two simultaneous conditions, it is
possible to ensure that the current which the converter
draws from the power line agrees with the instantaneous
line voltage. One of these conditions is that the output
voltage of the boost converter must be set higher than the
peak value of the line voltage. A commonly used value is
385VDC, to allow for a high line of 270VAC

. The other

rms

condition is that the current which the converter is
allowed to draw from the line at any given instant must be
proportional to the line voltage. The first of these
requirements is satisfied by establishing a suitable voltage
control loop for the converter, which in turn drives a
current error amplifier and switching output driver. The
second requirement is met by using the rectified AC line
voltage to modulate the output of the voltage control loop.
Such modulation causes the current error amplifier to
command a power stage current which varies directly with
the input voltage. In order to prevent ripple which will
necessarily appear at the output of the boost circuit
(typically about 10VAC on a 385V DC level) from
introducing distortion back through the voltage error
amplifier, the bandwidth of the voltage loop is deliberately
kept low. A final refinement is to adjust the overall gain of
the PFC such to be proportional to 1/V

2

, which linearizes

IN

the transfer function of the system as the AC input voltage
varies.

Since the boost converter topology in the ML4824 PFC is
of the current-averaging type, no slope compensation is
required.

Power factor correction makes a non-linear load look like
a resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with and proportional to
the line voltage, so the power factor is unity (one). A
common class of non-linear load is the input of most
power supplies, which use a bridge rectifier and capacitive
input filter fed from the line. The peak-charging effect
which occurs on the input filter capacitor in these supplies
causes brief high-amplitude pulses of current to flow from
the power line, rather than a sinusoidal current in phase
with the line voltage. Such supplies present a power factor
to the line of less than one (i.e. they cause significant
current harmonics of the power line frequency to appear
at their input). If the input current drawn by such a supply
(or any other non-linear load) can be made to follow the
input voltage in instantaneous amplitude, it will appear
resistive to the AC line and a unity power factor will be
achieved.

To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the
input voltage, a way must be found to prevent that device
from loading the line except in proportion to the
instantaneous line voltage. The PFC section of the ML4824
uses a boost-mode DC-DC converter to accomplish this.
The input to the converter is the full wave rectified AC line
voltage. No bulk filtering is applied following the bridge
rectifier, so the input voltage to the boost converter ranges
(at twice line frequency) from zero volts to the peak value
of the AC input and back to zero. By forcing the boost

PFC SECTION
Gain Modulator

Figure 1 shows a block diagram of the PFC section of the
ML4824. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the
current loop to line voltage waveform and frequency, rms
line voltage, and PFC output voltage. There are three
inputs to the gain modulator. These are:

1) A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectified AC
input sine wave is converted to a proportional current
via a resistor and is then fed into the gain modulator at

. Sampling current in this way minimizes ground

I

AC

noise, as is required in high power switching power
conversion environments. The gain modulator responds
linearly to this current.

2) A voltage proportional to the long-term rms AC line
voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the gain
modulator at V
inversely proportional to V
low values of V

. The gain modulator’s output is

RMS

where special gain contouring takes

RMS

2

(except at unusually

RMS

over, to limit power dissipation of the circuit
components under heavy brownout conditions). The
relationship between V

and gain is called K, and is

RMS

illustrated in the Typical Performance Characteristics.

REV. 1.01 12/7/2000 7

ML4824

FUNCTIONAL DESCRIPTION (Continued)

3) The output of the voltage error amplifier, VEAO. The
gain modulator responds linearly to variations in this
voltage.

V

REF

The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way
the gain modulator forms the reference for the current
error loop, and ultimately controls the instantaneous
current draw of the PFC from the power line. The general
form for the output of the gain modulator is:

IVEAO

×

I

GAI NMOD

AC

=

2

V

RMS

×

1

V

(1)

More exactly, the output current of the gain modulator is
given by:

I K VEAO V I

GAINMOD AC

=× − ×(.)15

where K is in units of V-1.

Note that the output current of the gain modulator is
limited to ≅ 200µA.

Current Error Amplifier

The current error amplifier’s output controls the PFC duty
cycle to keep the average current through the boost
inductor a linear function of the line voltage. At the
inverting input to the current error amplifier, the output
current of the gain modulator is summed with a current
which results from a negative voltage being impressed
upon the I
The negative voltage on I

pin (current into I

SENSE

≅ V

SENSE

represents the sum of all

SENSE

SENSE

/3.5kΩ).

currents flowing in the PFC circuit, and is typically derived
from a current sense resistor in series with the negative
terminal of the input bridge rectifier. In higher power
applications, two current transformers are sometimes used,
one to monitor the I
monitor the I

of the boost diode. As stated above, the

F

of the boost MOSFET(s) and one to

D

inverting input of the current error amplifier is a virtual
ground. Given this fact, and the arrangement of the duty
cycle modulator polarities internal to the PFC, an increase
in positive current from the gain modulator will cause the
output stage to increase its duty cycle until the voltage on

is adequately negative to cancel this increased

I

SENSE

current. Similarly, if the gain modulator’s output decreases,
the output duty cycle will decrease, to achieve a less
negative voltage on the I

SENSE

pin.

Cycle-By-Cycle Current Limiter

The I

pin, as well as being a part of the current

SENSE

feedback loop, is a direct input to the cycle-by-cycle
current limiter for the PFC section. Should the input
voltage at this pin ever be more negative than -1V, the
output of the PFC will be disabled until the protection flip­flop is reset by the clock pulse at the start of the next PFC
power cycle.

PFC

OUTPUT

15

2

4

3

V

FB

2.5V

I

AC

V

RMS

I

SENSE

–
+

VEAO

VEA

MODULATOR

16

GAIN

1

IEAO

IEA

+
–

+
–

Figure 2. Compensation Network Connections for the

V oltage and Curr ent Err or Amplifiers

Overvoltage Protection

The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load
should suddenly change. A resistor divider from the high
voltage DC output of the PFC is fed to V
voltage on V

exceeds 2.7V, the PFC output driver is shut

FB

. When the

FB

down. The PWM section will continue to operate. The
OVP comparator has 125mV of hysteresis, and the PFC
will not restart until the voltage at V
The V

should be set at a level where the active and

FB

drops below 2.58V.

FB

passive external power components and the ML4824 are
within their safe operating voltages, but not so low as to
interfere with the boost voltage regulation loop.

Error Amplifier Compensation

The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the
types of compensation networks most commonly used for
the voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to V

to produce a soft-start characteristic on

REF

the PFC: as the reference voltage comes up from zero
volts, it creates a differentiated voltage on IEAO which
prevents the PFC from immediately demanding a full duty
cycle on its boost converter.

There are two major concerns when compensating the
voltage loop error amplifier; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s

8 REV. 1.01 12/7/2000

FUNCTIONAL DESCRIPTION (Continued)

ML4824

open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest
anticipated international power frequency). The gain vs.
input voltage of the ML4824’s voltage error amplifier has a
specially shaped nonlinearity such that under steady-state
operating conditions the transconductance of the error
amplifier is at a local minimum. Rapid perturbations in
line or load conditions will cause the input to the voltage
error amplifier (V
value. If this happens, the transconductance of the voltage
error amplifier will increase significantly, as shown in the
Typical Performance Characteristics. This raises the gain­bandwidth product of the voltage loop, resulting in a
much more rapid voltage loop response to such
perturbations than would occur with a conventional linear
gain characteristic.

The current amplifier compensation is similar to that of
the voltage error amplifier with the exception of the
choice of crossover frequency. The crossover frequency of
the current amplifier should be at least 10 times that of
the voltage amplifier, to prevent interaction with the
voltage loop. It should also be limited to less than 1/6th
that of the switching frequency, e.g. 16.7kHz for a
100kHz switching frequency.

There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be
the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier. This is illustrated in the
Typical Performance Characteristics.

) to deviate from its 2.5V (nominal)

FB

The deadtime of the oscillator may be determined using:

V

25

t

DEADTIME T T

The deadtime is so small (t
operating frequency can typically be approximated by:

f

=

OSC

EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:

fkHz

==100

OSC

=×× =×

tCR

RAMP T T

Solving for RT x CT yields 2 x 10-4. Selecting standard
components values, C

The deadtime of the oscillator adds to the Maximum PWM
Duty Cycle (it is an input to the Duty Cycle Limiter). With
zero oscillator deadtime, the Maximum PWM Duty Cycle
is typically 45%. In many applications, care should be
taken that CT not be made so large as to extend the
Maximum Duty Cycle beyond 50%. This can be
accomplished by using a stable 470pF capacitor for C

PWM SECTION
Pulse Width Modulator

.

CC

RAMP

490

>> t

=×=×

mA

51

.

1

t

RAMP

1

t

RAMP

−

051 1 10

.

= 470pF, and R

T

5

DEADTIME

= 41.2kΩ.

T

) that the

T

(4)

(5)

.

For more information on compensating the current and
voltage control loops, see Application Notes 33 and 34.
Application Note 16 also contains valuable information for
the design of this class of PFC.

Oscillator (RAMP 1)

The oscillator frequency is determined by the values of R
and CT, which determine the ramp and off-time of the
oscillator output clock:

f

=

OSC

tt

RAMP DEADTIME

The deadtime of the oscillator is derived from the
following equation:

tCRIn

=××

RAMP T T

at V

= 7.5V:

REF

tCR

=××051.

RAMP T T

+

1

F

−

V

REF

G

V

−

H

REF

125

375..

I

J

K

T

(2)

(3)

The PWM section of the ML4824 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing (at the PFC frequency in the ML4824-1, and at
twice the PFC frequency in the ML4824-2). The PWM is
capable of current-mode or voltage mode operation. In
current-mode applications, the PWM ramp (RAMP 2) is
usually derived directly from a current sensing resistor or
current transformer in the primary of the output stage, and
is thereby representative of the current flowing in the
converter’s output stage. DC I
by-cycle current limiting, is typically connected to RAMP
2 in such applications. For voltage-mode operation or
certain specialized applications, RAMP 2 can be
connected to a separate RC timing network to generate a
voltage ramp against which V
these conditions, the use of voltage feedforward from the
PFC buss can assist in line regulation accuracy and
response. As in current mode operation, the DC I
input is used for output stage overcurrent protection.

, which provides cycle-

LIMIT

DC will be compared. Under

LIMIT

REV. 1.01 12/7/2000 9

ML4824

FUNCTIONAL DESCRIPTION (Continued)

No voltage error amplifier is included in the PWM stage
of the ML4824, as this function is generally performed on
the output side of the PWM’s isolation boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into the PWM’s RAMP 2 input which
allows V

to command a zero percent duty cycle for

DC

input voltages below 1.25V.

PWM Current Limit

The DC I

pin is a direct input to the cycle-by-cycle

LIMIT

current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output of the PWM
will be disabled until the output flip-flop is reset by the
clock pulse at the start of the next PWM power cycle.

VIN OK Comparator

The V
and inhibits the PWM if this voltage on V

OK comparator monitors the DC output of the PFC

IN

is less than its

FB

nominal 2.5V. Once this voltage reaches 2.5V, which
corresponds to the PFC output capacitor being charged to
its rated boost voltage, the soft-start begins.

PWM Control (RAMP 2)

When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
timing components (R

RAMP2

, C

), which will have a

RAMP2

minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,
feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.

Soft Start

Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed
by the following equation:

A

50

Ct

=×

SS DELAY

where C
t

DELAY

is the required soft start capacitance, and

SS

is the desired start-up delay.

.

125

µ

V

(6)

It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.

Solving for the minimum value of C

A

50

Cms

=× =5

SS

125

.

µ

V

200

nF

:

SS

Caution should be exercised when using this minimum
soft start capacitance value because premature charging
of the SS capacitor and activation of the PWM section
can result if V
comparator at start-up. The magnitude of V

is in the hysteresis band of the VIN OK

FB

at start-up is

FB

related both to line voltage and nominal PFC output
voltage. Typically, a 1.0µF soft start capacitor will allow
time for V

and PFC out to reach their nominal values

FB

prior to activation of the PWM section at line voltages
between 90Vrms and 265Vrms.

Generating V

CC

The ML4824 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the voltage
internal to the part at 13.5V. This allows a low power
dissipation while at the same time delivering 10V of gate
drive at the PWM OUT and PFC OUT outputs. It is
important to limit the current through the part to avoid
overheating or destroying it. This can be easily done with a
single resistor in series with the Vcc pin, returned to a bias
supply of typically 18V to 20V. The resistor’s value must be
chosen to meet the operating current requirement of the
ML4824 itself (19mA max) plus the current required by the
two gate driver outputs.

EXAMPLE:
With a V

of 20V, a VCC limit of 14.6V (max) and the

BIAS

ML4824 driving a total gate charge of 110nC at 100kHz
(e.g., 1 IRF840 MOSFET and 2 IRF830 MOSFETs), the gate
driver current required is:

IkHznCmA

GATEDRIVE

R

BIAS

=×=100 100 11

VV

20 146

=

mA mA

19 11

.

−
+

=

180

(7)

Ω

(8)

To check the maximum dissipation in the ML4824, find
the current at the minimum V

VV

20 12 4

I

=

CC

−

180

=

Ω

The maximum allowable I

(12.4V):

CC

mA

422..

is 55mA, so this is an

CC

(9)

acceptable design.

The ML4824 should be locally bypassed with a 10nF and
a 1µF ceramic capacitor. In most applications, an
electrolytic capacitor of between 100µF and 330µF is also
required across the part, both for filtering and as part of
the start-up bootstrap circuitry.

10 REV. 1.01 12/7/2000

ML4824

V

BIAS

R

BIAS

V

CC

ML4824

GND

Figure 3. External Component Connections to V

10nF

CERAMIC

1µF

CERAMIC

CC

LEADING/TRAILING MODULATION

Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock. The
error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplifier output voltage, the switch will
be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 4 shows a typical trailing edge
control scheme.

In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 5
shows a leading edge control scheme.

One of the advantages of this control teccnique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the first
stage is reduced. Calculation and evaluation have shown
that the 120Hz component of the PFC’s output ripple
voltage can be reduced by as much as 30% using this
method.

TYPICAL APPLICATIONS

Figure 6 is the application circuit for a complete 100W
power factor corrected power supply, designed using the
methods and general topology detailed in Application
Note 33.

+

DC

VIN

L1
I1

REF

OSC

U4

SW2

I2 I3

I4

RL

RAMP

DFF

R

Q

U2

D

Q

CLK

VSW1

U3

+

EA

–

RAMP
CLK

SW1

+
–

C1

U1

Figure 4. Typical Trailing Edge Control Scheme.

VEAO

TIME

TIME

REV. 1.01 12/7/2000 11

ML4824

+

DC

VIN

SW2

SW1

I2 I3

I4

RL

L1
I1

C1

U3

+

EA

–

REF

OSC

U4

RAMP
CLK

VEAO

+
–

CMP
U1

DFF

R

Q

D

U2

Q

CLK

Figure 5. Typical Leading Edge Control Scheme.

RAMP

VEAO

TIME

VSW1

TIME

12 REV. 1.01 12/7/2000

AC INPUT

85 TO 265VAC

ML4824

BR1

4A, 600V

R5

300mΩ

1W

C1

470nF

C3

470nF

C2

470nF

F1

3.15A

R2A

357kΩ

R2B

357kΩ

D12

1A, 50V

D13

1A, 50V

C19
1µF

R1A

499kΩ

R1B

499kΩ

R3

75kΩ

R4

13kΩ

R27

39kΩ

C30

330µF

470pF

1
2
3
4
5
6
7
8

C18

3.1mH

Q1

IRF840

R12

27kΩ

IEAO
I

AC

I

SENSE

V

RMS

SS
V

DC

RAMP 1
RAMP 2

L1

R21
22Ω

C7

220pF

ML4824

8A, 600V

R28

180Ω

C12

10µF

C6

1nF

VEAO

V

V

V

PFC OUT

PWM OUT

GND

DC I

LIMIT

R6

41.2kΩ

D1

C4

10nF

FB

REF

CC

16
15
14
13
12
11
10

9

R10

6.2kΩ

D3

50V

178kΩ

178kΩ

C5

100µF

R7A

R7B

D8

1A, 20V

C17

220pF

C25

100nF

R15

3Ω

C20

1µF

R14

33Ω

T1

R19

220Ω

C15

10nF

R17
33Ω

R30

4.7kΩ

D10

1A, 20V

Q2

IRF830

Q3

IRF830

C16

1µF

D7

15V

R20

1.1Ω

D6

600V

C13

100nF

D5

600V

R26

10kΩ

TL431

C31
1nF

L2

33µH

C21

1800µF

C22

4.7µF

C23

100nF

R11

750kΩ

C8

82nF

D11

MBR2545CT

T2

R23

1.5kΩ

MOC
8102

R8

C14

2.37kΩ

1µF

L1: Premier Magnetics #TSD-734
L2: 33µH, 10A DC
T1: Premier Magnetics #TSD-736
T2: Premier Magnetics #TSD-735

Premier Magnetics: [phone]

R24

1.2kΩ

C24
1µF

R18

220Ω

C9

8.2nF

12VDC

RTN

R22

8.66kΩ

R25

2.26kΩ

C11

10nF

Figure 6. 100W Power Factor Corrected Power Supply, Designed Using Micro Linear Application Note 33.

REV. 1.01 12/7/2000 13

ML4824

PHYSICAL DIMENSIONS inches (millimeters)

0.740 - 0.760

(18.79 - 19.31)

16

Package: P16

16-Pin PDIP

0.02 MIN
(0.50 MIN)
(4 PLACES)

0.170 MAX
(4.32 MAX)

0.125 MIN
(3.18 MIN)

PIN 1 ID

1

0.055 - 0.065
(1.40 - 1.65)

0.016 - 0.022
(0.40 - 0.56)

0.100 BSC
(2.54 BSC)

SEATING PLANE

0.240 - 0.260
(6.09 - 6.61)

0.015 MIN
(0.38 MIN)

0.295 - 0.325
(7.49 - 8.26)

0º - 15º

0.008 - 0.012
(0.20 - 0.31)

14 REV. 1.01 12/7/2000

PHYSICAL DIMENSIONS inches (millimeters)

Package: S16W

16-Pin Wide SOIC

0.400 - 0.414

16

(10.16 - 10.52)

ML4824

0.024 - 0.034
(0.61 - 0.86)

(4 PLACES)

0.090 - 0.094
(2.28 - 2.39)

1

PIN 1 ID

0.050 BSC

(1.27 BSC)

0.012 - 0.020
(0.30 - 0.51)

0.291 - 0.301
(7.39 - 7.65)

0.095 - 0.107
(2.41 - 2.72)

SEATING PLANE

0.398 - 0.412

(10.11 - 10.47)

0.005 - 0.013
(0.13 - 0.33)

0º - 8º

0.022 - 0.042
(0.56 - 1.07)

0.009 - 0.013
(0.22 - 0.33)

REV. 1.01 12/7/2000 15

ML4824

ORDERING INFORMATION

PART NUMBER PWM FREQUENCY TEMPERATURE RANGE PACKAGE

ML4824CP-1 1 x PFC 0°C to 70°C 16-Pin PDIP (P16)
ML4824CP-2 2 x PFC 0°C to 70°C 16-Pin PDIP (P16)
ML4824CS-1 1 x PFC 0°C to 70°C 16-Pin Wide SOIC (S16W)
ML4824CS-2 2 x PFC 0°C to 70°C 16-Pin Wide SOIC (S16W)

ML4824IP-1 1 x PFC –40°C to 85°C 16-Pin PDIP (P16)
ML4824IP-2 2 x PFC –40°C to 85°C 16-Pin PDIP (P16)

ML4824IS-1 1 x PFC –40°C to 85°C 16-Pin Wide SOIC (S16W)
ML4824IS-2 2 x PFC –40°C to 85°C 16-Pin Wide SOIC (S16W)

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

www.fairchildsemi.com © 2000 Fairchild Semiconductor Corporation

2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

16 REV. 1.01 12/7/2000