Page 1
May 1997
ML4819*
Power Factor and PWM Controller “Combo”
GENERAL DESCRIPTION
The ML4819 is a complete boost mode Power factor
Controller (PFC) which also contains a PWM controller.
The PFC circuit is similar to the ML4812 while the PWM
controller can be used for current or voltage mode control
for a second stage converter. Since the PWM and PFC
circuits share the same oscillator, synchronization of the
two stages is inherent. The outputs of the controller IC
provide high current (>1A peak) and high slew rate to
quickly charge and discharge MOSFET gates. Special care
has been taken in the design of the ML4819 to increase
system noise immunity.
The PFC section is of the peak current sensing boost type,
using a current sense transformer or current sensing
FEATURES
■ Two 1A peak current totem-pole output drivers
■ Precision buffered 5V reference (±1%)
■ Large oscillator amplitude for better noise immunity
■ Precision duty cycle limit for PWM section
■ Current input gain modulator improves noise immunity
■ Programmable Ramp Compensation circuit
■ Over-Voltage comparator helps prevent output
“runaway”
■ Wide common mode range in current sense
compensators for better noise immunity
■ Under-Voltage Lockout circuit with 6V hysteresis
MOSFETs to non-dissipatively sense switch current. This
gives the system overall efficiency over average current
sensing control method.
The PWM section includes cycle by cycle current limiting, * Some Packages Are Obsolete
precise duty cycle limiting for single ended converters,
and slope compensation.
BLOCK DIAGRAM
R
T
10
C
T
Please See Ml4824 for New Designs
20
RAMP COMP
12
I
SENSE
1
GM OUT
3
OVP
2
EA OUT A
4
INV A
5
I
SINE
6
GND
19
A
5V
5V
GAIN MODULATOR
OSC
SLOPE
COMPENSATION
5V
+
–
+
–
ERROR
AMP
I
POWER FACTOR
CONTROLLER
+
–
–
I
EA
MULT
PWM
CONTROLLER
R
Q
S
R
Q
S
–
+
DUTY CYCLE
–
+
1V
–
+
V
CC
UNDER
VOLTAGE
LOCKOUT
V
CC
I
SENSE
0.7V
PWM B
OUT B
PGND B
OUT A
PGND A
I
LIM
V
7
11
B
9
8
14
13
REF
18
V
CC
15
16
17
1
Page 2
ML4819
PIN CONFIGURATION
I
SENSE
A
OVP
ML4819
20-Pin PDIP
1
2
20
19
C
T
GND
GM OUT
EA OUT A
INV A
I
SINE
DUTY CYCLE
PWM B
I
SENSE
3
4
5
6
7
8
B
9
R
10
T
TOP VIEW
18
17
16
15
14
13
12
11
V
REF
PGND A
OUT A
V
CC
OUT B
PGND B
RAMP COMP
I
LIM
PIN DESCRIPTION
PIN NAME FUNCTION PIN NAME FUNCTION
1 I
2 OVP Input to Over-Voltage comparator.
3 GM OUT Output of Gain Modulator. A resistor
4 EA OUT A Output of error amplifier.
5 INV A Inverting input to error amplifier.
6I
7 DUTY CYCLE PWM controller duty cycle is limited
8 PWM B Error voltage feedback input.
9I
10 R
A Input form the PFC current sense
SENSE
transformer to the PWM comparator
(+). Current Limit occurs when this
point reaches 5V.
to ground on this pin converts the
current to a voltage.
SINE
Current Multiplier input.
by setting this pin to a fixed voltage.
B Input for Current Sense resistor for
SENSE
current mode operation or for
Oscillator ramp for voltage mode
operation.
T
Oscillator timing resistor pin. A 5V
source across this resistor sets the
charging current for C
T
11 I
LIM
Cycle by cycle PWM current limit.
Exceeding 1V threshold on this pin
terminates the PWM cycle.
12 RAMP COMP Buffered output from the Oscillator
Ramp (CT). A resistor to ground sets a
current, 1/2 of which is sourced on
pins 9 and 11.
13 GND B Return for the high current totem pole
output of the PWM controller.
14 OUT B PWM controller totem pole output.
15 V
CC
Positive Supply for the IC.
16 OUT A PFC controller totem pole output.
17 GND A Return for the high current totem pole
output of the PFC controller.
18 V
REF
Buffered output for the 5V voltage
reference
19 GND Analog signal ground.
20 C
T
Timing Capacitor for the Oscillator.
2
Page 3
ABSOLUTE MAXIMUM RATINGS
ML4819
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Analog Inputs (ISENSE A, EA OUT A, INV A)
...............................................................–0.3V to 5.5V
Junction Temperature ............................................ 150×C
Storage Temperature Range ..................... –65×C to 150×C
Lead Temperature (soldering 10 sec.) ..................... 260×C
Supply Voltage (VCC) ................................................. 35V
Output Current, Source or Sink (RAMP COMP)
Thermal Resistance (qJA)
Plastic DIP or SOIC .......................................... 60×C/W
DC ....................................................................... 1.0A
Output Energy (capacitive load per cycle)................... 5mJ
Multiplier I
SINE
Input (I
) ................................... 1.2mA
SINE
Error Amp Sink Current (GM OUT) ......................... 10mA
Oscillator Charge Current ......................................... 2mA
OPERATING CONDITIONS
Temperature Range
ML4819C .................................................. 0×C to 70×C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, RT = 14kW, CT = 1000pF, TA = Operating Temperature Range, VCC = 15V (Notes 1, 2).
PARAMETER CONDITIONS MIN TYP MAX UNITS
OSCILLATOR
Initial Accuracy TJ = 25×C 90 97 104 kHz
Voltage Stability 12V < VCC < 18V 0.2 %
Temperature Stability 2%
Total Variation Line, temp. 88 106 kHz
Ramp Valley 0.9 V
Ramp Peak 4.3 V
RT Voltage 4.8 5.0 5.2 V
Discharge Current (PWM B open) TJ = 25×C, V
V
= 2V 7.2 8.4 9.5 mA
OUT A
DUTY CYCLE LIMIT COMPARATOR
Input Offset Voltage –15 15 mV
Input Bias Current –2 –10 mA
Duty Cycle V
REFERENCE
Output Voltage TJ = 25×C, IO = 1mA 4.95 5.00 5.05 V
Line Regulation 12V < VCC < 25V 2 20 mV
Load Regulation 1mA < IO < 20mA 8 25 mV
Temperature Stability 0.4 %
Total Variation Line, load, temperature 4.9 5.1 V
Output Noise Voltage 10Hz to 10kHz 50 mV
Long Term Stability TJ = 125×C, 1000 hours, (Note 1) 5 25 mV
Short Circuit Current V
ERROR AMPLIFIER
Input Offset Voltage –15 15 mV
Input Bias Current –0.1 –1.0 mA
Open Loop Gain 1 < V
PSRR 12V < VCC < 25V 60 90 dB
Output Sink Current V
Output Source Current V
DUTY CYCLE
= 0V –30 –85 –180 mA
REF
EA OUT A
EA OUT A
EA OUT A
= 1.1V, V
= 5.0V, V
= 2V 7.5 8.4 9.3 mA
OUT A
= V
REF/2
< 5V 60 75 dB
= 5.2V 2 12 mA
INV A
= 4.8V –0.5 –1.0 mA
INV A
43 45 49 %
3
Page 4
ML4819
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER CONDITIONS MIN TYP MAX UNITS
ERROR AMPLIFIER (continued)
Output High voltage I
Output Low Voltage I
EA OUT A
EA OUT A
= –0.5mA, V
= 2mA, V
INV A
= 4.8V 6.5 7.0 V
INV A
= 5.2V 0.7 1.0 V
Unity Gain Bandwidth 1.0 MHz
GAIN MODULATOR
I
Input Voltage I
SINE
Output Current (GM OUT) I
= 500mA 0.4 0.7 0.9 V
SINE
= 500mA, INV A = V
SINE
I
= 500mA, INV A = V
SINE
I
= 1mA, INV A = V
SINE
–20mV 460 495 505 mA
REF
+ 20mV 0 10 mA
REF
– 20mV 900 990 1005 mA
REF
Bandwidth 200 kHz
PSRR 12V < VCC < 25V 70 dB
SLOPE COMPENSATION CIRCUIT
RAMP COMP Voltage V
I
(I
OUT
SENSE
A or I
B) I
SENSE
RAMP COMP
= 100mA (Note 3) 45 48 51 mA
– 1 V
C(T)
OVP COMPARATOR
Input Offset Voltage Output Off –15 15 mV
Hysteresis Output On 100 120 140 mV
Input Bias Current –0.3 –3 mA
Propagation Delay 150 ns
I
COMPARATORS
SENSE
Input Common Mode Range –0.2 5.5 V
Input Offset Voltage I
A –15 15 mV
SENSE
I
B 0.4 0.7 0.9 V
SENSE
Input Bias Current –3 –10 mA
Input Offset Current –3 0 3 mA
Propagation Delay 150 ns
I
(A) Trip Point V
LIMIT
I
COMPARATOR
LIM
I
Trip Point .95 1.0 1.05 V
LIMIT
= 5.5V 4.8 5 5.2 V
OVP
Input Bias Current –2 –10 mA
Propagation Delay 150 ns
OUTPUT DRIVERS
Output Voltage Low I
Output Voltage High I
Output Voltage Low in UVLO I
= –20mA 0.1 0.4 V
OUT
I
= –200mA 1.6 2.2 V
OUT
= 20mA 13 13.5 V
OUT
I
= 200mA 12 13.4 V
OUT
= –1mA, VCC = 8V 0.1 0.8 V
OUT
Output Rise/Fall Time CL = 1000pF 50 ns
4
Page 5
ML4819
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER CONDITIONS MIN TYP MAX UNITS
UNDER-VOLTAGE LOCKOUT
Start-Up Threshold 15 16 17 V
Shut-Down Threshold 9 10 11 V
V
Good Threshold 4.4 V
REF
SUPPLY
Supply Current Start-Up, VCC = 14V 0.6 1.2 mA
Operating, TJ = 25×C2535mA
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: V
Note 3: PWM comparator bias currents are subtracted from this reading.
is raised above the Start-Up Threshold first to activate the IC, then returned to 15V.
CC
FUNCTIONAL DESCRIPTION
OSCILLATOR
The ML4819 oscillator charges the external capacitor (CT)
with a current (I
voltage reaches the upper threshold, the comparator
changes state and the capacitor discharges to the lower
threshold through Q1. While the capacitor is discharging,
the clock provides a high pulse.
The oscillator period can be described by the following
relationship:
t
= t
OSC
where:
t=
C(Ramp Valley to Peak)
RAMP
and:
t
DEADTIME
The maximum duty cycle of the PWM section can be
limited by setting a threshold on pin 7. when the CT ramp
is above the threshold at pin 7, the PWM output is held
off and the PWM flip-flop is set:
D
≅
LIMIT
where:
D
= Desired duty cycle limit
LIMIT
D
= Oscillator duty cycle
OSC
) equal to 5/R
SET
+ t
RAMP
=
D (V -0.9)
DEADTIME
I
SET
C(Ramp Valley to Peak)
8.4mA - I
×
OSC PIN7
SET
3.4
. When the capacitor
SET
+5V
DUTY CYCLE
RAMP PEAK
RAMP VALLEY
I
SET
R
T
C
T
CLOCK
7
5V
10
I
SET
20
8.4mA
Q1
t
C
T
+
–
V
REF
CLOCK
+
–
D
Figure 1. Oscillator Block Diagram
TO PWM
LATCH B
TO PWM
LATCHES
5
Page 6
ML4819
95%
100pF
200pF
500pF
, TIMING RESISTOR (kΩ)
T
R
50
30
20
10
8
5
3
20
VCC = 15V
= 25 C
T
A
1nF
2nF
5nF
10nF
30 50 100 200 300 500
f
, OSCILLATOR FREQUENCY (kHz)
OSC
MAX DUTY CYCLE
Figure 2. Oscillator Timing Resistance vs. Frequency
–1.0
–2.0
0
V
CC
SOURCE SATURATION
(LOAD TO GROUND)
TA = 25 C
V
= 15V
CC
80µs PULSED LOAD
120 Hz RATE
90%
85%
100
80
60
40
20
0
, OPEN-LOOP VOLTAGE GAIN (dB)
VOL
–20
A
10 100 1.0k 10k 100k 1.0M 10M
GAIN
f, FREQUENCY (Hz)
VCC = 15V
= 1.0V TO 5.0V
V
O
= 100kΩ
R
L
= 25 C
T
A
PHASE
Figure 5. Error Amplifier Open-Loop Gain and
Phase vs Frequency
GAIN MODULATOR
The ML4819 gain modulator is a linear current input
multiplier to provide high immunity to the disturbances
caused by high power switching. The rectified line input
sine wave is converted to a current via a dropping resistor.
In this way, small amounts of ground noise produce an
insignificant effect on the reference to the PWM
comparator.
0
–30
60
90
120
150
φ, EXCESS PHASE (DEGREES)
180
3.0
2.0
1.0
, OUTPUT SATURATION VOLTAGE (V)
SAT
V
0
0 200 400 600 800
I
, OUTPUT LOAD CURRENT (mA)
O
TA = 25 C
SINK SATURATION
(LOAD TO V
CC
)
GND
Figure 3. Output Saturation Voltage vs. Output Current
ERROR AMPLIFIER
The ML4819 error amplifier is a high open loop gain, wide
bandwidth amplifier.
+5V
+
INV
4
–
+8V
0.5mA
The output of the gain modulator is a current of the form:
I
OUT
where I
is proportional to I
is the current in the dropping resistor, and I
SINE
SINE
¥ I
EA
is a current proportional to the output of the error
amplifier. When the error amplifier is saturated high, the
output of the gain modulator is approximately equal to
the I
input current.
SINE
The gain modulator output current is converted into the
reference voltage for the PWM comparator through a
resistor to ground on the gain modulator output. The gain
modulator output is clamped to 5V to provide current
limiting.
I
SINE
I
6
ERR
ERROR
VOLTAGE
9V
I
SINE
GAIN MODULATOR
3I
ERR
EA
EA OUT
3
Figure 4. Error Amplifier Configuration
MULTIPLIER
3
Figure 6. Gain Modulator Block Diagram
6
Page 7
SLOPE COMPENSATION
Slope compensation is accomplished by adding 1/2 of the
current flowing out of pin 12 to pin 1 (for the PFC section
and pin 9 (for the PWM section). The amount of slope
compensation is equal to (I
RAMP COMP
/2) ¥ RL where RL is
the impedance to GND on pin 1 or pin 9. Since most of
the PWM applications will be limited to 50% duty cycle,
slope compensation should not be needed for the PWM
section. This can be defeated by using a low impedance
load to the current sense on pin 9.
R
20
RAMP COMP
12
R
SC
T
C
T
I
OSC10
V
REF
R(SC)
Q1
SLOPE
COMPENSATION
9V
I
R(SC)
I
R(SC)
42
TO PIN 9
TO PIN 1
42
ML4819
ENABLE
V
REF
V
REF
GEN.
9V
–
+
INTERNAL
BIAS
Figure 9. Under-Voltage Lockout Block Diagram
40
30
20
5V V
V
CC
REF
Figure 7. Slope Compensation Circuit
500
400
300
200
100
MULTIPLIER OUTPUT CURRENT (µA)
0
0 100 200 300 400 500
SINE INPUT CURRENT (µA)
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
1. 5V
Figure 8. Gain Modulator Linearity
UNDER VOLTAGE LOCKOUT
On power-up the ML4819 remains in the UVLO condition;
output low and quiescent current low. The IC becomes
operational when VCC reaches 16V. When VCC drops
below 10V, the UVLO condition is imposed. During the
UVLO condition, the 5V V
pin is “off”, making it
REF
usable as a status flag.
SUPPLY CURRENT (mA)
10
CC,
I
0
0 10203040
Figure 10a. Total Supply Current vs. Supply Voltage
E/A OUTPUT VOLTAGE (V)
35
30
25
20
15
— SUPPLY CURRENT
10
CC
I
5
0
0 10203040506070
SUPPLY VOLTAGE (V)
V
CC,
OPERATING
CURRENT
START-UP
TA = 25 C
TEMPERATURE ( C)
Figure 10b. Supply Current (ICC) vs. Temperature
7
Page 8
ML4819
0
VCC = 15V
–4.0
–8.0
–12
–16
–20
, REFERENCE VOLTAGE CHANGE (mV)
REF
∆V
–24
0 20 40 60 80 100 120
I
, REFERENCE SOURCE CURRENT (mA)
REF
TA = 25 C
Figure 11. Reference Load Regulation
APPLICATIONS
POWER FACTOR SECTION
The power factor section in the ML4819 is similar to the
power factor section in the ML4812 with the exception of
the operation of the slope compensation circuit. Please
refer to the ML4812 data sheet for more information.
The following calculations refer to Figure 12 in this data
sheet. The component designators in the equations below
refer to the following components in Figure 12:
RT = R16, CT = C6.
Where DON is the duty cycle [TON/(TON + T
OFF
)]. The
input boost inductor will dry out when the following
condition is satisfied:
Vt V D
()
<×−
IN OUT ON MAX
1
[]
()
(2)
or
VDV
V
INDRY
V
OUT
=−
INDRY ON MAX OUT
[]
×1
()
: Voltage where the inductor dries out.
: Output dc voltage.
(3)
Effectively, the above relationship shows that the resetting
volt-seconds are more than setting volt-seconds. In energy
transfer terms this means that less energy is stored in the
inductor during the ON time than it is asked to deliver during
the OFF time. The net result is that the inductor dries out.
The recommended maximum duty cycle is 95% at
100KHz to allow time for the input inductor to dump its
energy to the output capacitors.
For example:
if: V
then substituting in (3) yields V
OUT
D
ON(MAX)
= 380V and
= 0.95
= 20V. The effect of
INDRY
drying out is an increase in distortion at low input voltages.
For a given output power, the instantaneous value of the
input current is a function of the input sinusoidal voltage
waveform. As the input voltage sweeps from zero volts to
its maximum value and back, so does the current.
INPUT INDUCTOR (L1) SELECTION
The central component in the regulator is the input boost
inductor. The value of this inductor controls various
critical operational aspects of the regulator. If the value is
too low, the input current distortion will be high and will
result in low power factor and increased noise at the
input. This will require more input filtering. In addition,
when the value of the inductor is low the inductor dries
out (runs out of current) at low currents. Thus the power
factor will decrease at lower power levels and/or higher
line voltages. If the inductor value is too high, then for a
given operating current the required size of the inductor
core will be large and/or the required number of turns will
be high. So a balance must be reached between distortion
and core size.
One more condition where the inductor can dry out is
analyzed below where it is shown to be maximum duty
cycle dependent.
For the boost converter at steady state:
V
V
OUT
IN
=
D
−1
ON
(1)
The load of the power factor regulator is usually a
switching power supply which is essentially a constant
power load. As a result, an increase in the input voltage
will be offset by a decrease in the input current.
By combining the ideas set forth above, some ground
rules can be obtained for the selection and design of the
input inductor:
Step 1: Find minimum operating current.
.
×1 414
P
IN MIN
IN MAX
()
()
(4)
I
IN
MIN PEAK
()
V
IN(MAX)
P
IN(MIN)
=
= 260V
= 50W
V
then:
I
IN(MIN)PEAK
= 0.272A
Step 2: Choose a minimum current at which point the
inductor current will be on the verge of drying
out. For this example 40% of the peak current
found in step 1 was chosen.
8
Page 9
ML4819
V
REF
OUT
CIRCUIT
STARTUP
IN
D5
POWER FACTOR CORRECTION
1N5406
L1
D6
MUR850
D7
B+ 380 VDC
P
N
1N4148
+12V
D13
C18
C16
D83
1500µF
1µF
–004
–
OUT
V
R27
C19
R28
8.66kΩ
C20
0.1µF
U3
TL431
R29
2.26kΩ
1.2kΩ
R26
1.5kΩ
U2
4.7µF
8102
MOC
C2
C3
+
IN
V
DC
C10
330µF
25V
+
DC
330µF
400V
D9
MUR110
T3
0.62µF
T3
Q3
Q3
IRF840
C4
6800pF
R20
7.5Ω
Q1
T1
IRF840
C11
1µF
R21
D12
3kΩ
MUR150
IRF840
R24
R25
1Ω
1Ω
R23, 100Ω
D11
R12
10Ω
R11
91Ω
V
REF
D10
1N4148
R19, 3kΩ
C11
MUR150
R22
1µF
10Ω
C14
2200pF
T2
+
D1 - D4
R2
510kΩ
1N5406
C1
0.6µF
F1
–
B+ 380V
PFC
ENHANCEMENT
PGND
R10
R7
R5
REF
V
R1
R17, 3Ω
C5
C6
1000pF
1000pF
UI
33kΩ
357kΩ
357kΩ
330kΩ
R8
R6
Q4
2N2222
ML4819
4.53kΩ
4.75kΩ
R4
C9 0.1µF
201918171615141312
T
C
REF
V
GND
A
SENSE
I
OVP
GM OUT
1
2
345
C8 1
R9
27kΩ
D8
3V
R3
5.6kΩ
35V
REF
V
C7
12kΩ
10µF
OUT A
PGND A
EA OUT A
INV A
R13
C13 1µF
CC
V
OUT B
SINE
DUTY CYCLE
I
6
7
4.7kΩ
R18
65kΩ
PGND B
RAMP COMP
B
SENSE
PWM B
I
8
9
C12
1µF
R14
4.7kΩ
11
I
10
R
CC
V
LIM
T
D14
R16
15kΩ
R15
D13
PWM REGULATOR
4.3kΩ
REF
V
Figure 12. Typical Application, 180W Power Factor Corrected 12V Output Power Supply
9
Page 10
ML4819
then: I
LDRY
= 100mA
Step 3: The value of the inductance can now be found
using previously calculated data.
VD
L
1
=
=
100 100
×
INDRY ON MAX
If
L DRY OSC
()
V
20 0 95
mA kHz
×
×
()
×
.
(5)
mH
=
2
The inductor can be allowed to decrease in value when
the current sweeps from minimum to maximum value.
This allows the use of smaller core sizes. The only
requirement is that the ramp compensation must be
adequate for the lower inductance value of the core so
that there is adequate compensation at high current.
Step 4: The presence of the ramp compensation will
change the dry out point, but the value found
above can be considered a good starting point.
Based on the amount of power factor correction
the value of L1 can be optimized after a few
iterations.
Gapped Ferrites, Molypermalloy, and Powdered Iron cores
are typical choices for core material. The core material
selected should have a high saturation point and
acceptable losses at the operating frequency.
One ferrite core that is suitable at around 200W is the
#4229PL00-3C8 made by Ferroxcube. This ungapped core
will require a total gap of 0.180" for this application.
OSCILLATOR COMPONENT SELECTION
The oscillator timing components can be calculated by
using the following expression:
f
OSC
136.
=
RC
×
TT
(6)
For example:
Step 1: At 100kHz with 95% duty cycle T
= 500ns
OFF
calculate CT using the following formula:
CURRENT SENSE AND SLOPE (RAMP) COMPENSATION
COMPONENT SELECTION
Slope compensation in the ML4819 is provided internally.
A current equal to VCT/2(R18) is added to I
SENSE
A (pin 1).
this is converted to a voltage by R10, adding slope to the
sensed current through T1. The amount of slope
compensation should be at least 50% of the downslope of
the inductor current during the off time as reflected on pin
1. Note that slope compensation is a requirement only if
the inductor current is continuous and the duty cycle is
more than 50%. The highest inductor downslope is found
at the point of inductor discontinuity:
−
VV
di
dt
L
=
BINDRY
L
VV
380 20
=
2
−
mH
As
=µ
018./
(9)
The downslope as reflected to the input of the PWM
comparator is given by:
S
PWM
−
BINDRY
=
L
1
R
11
×
N
C
(10)
VV
Where NC is the turns ratio of the current transformer (T1)
used. In general, current transformers simplify the sensing of
switch currents, especially at high power levels where the
use of sense resistors is complicated by the amount of
power they have to dissipate. Normally the primary side
of the transformer consists of a single turn and the
secondary consists of several turns of either enameled
magnet wire or insulated wire. The diameter of the ferrite
core used in this example is 0.5" (SPANG/Magnetics
F41206-TC). The rectifying diode at the output of the
current transformer can be a 1N4148 for secondary
currents up to 75mA average.
Current-sensing MOSFETs or resistive sensing can also be
used to sense the switch current. In these cases, the
sensed signal has to be amplified to the proper level
before it is applied to the ML4819.
The value of the ramp compensation (SC
) as seen at
PWM
pin 1 is:
.
R
×
25
SC
PWM
=
RCR
16 6 18
9
××
(11)
tI
×
OFF DIS
C
=
T
V
OSC
=1000
pF
Step 2: Calculate the required value of the timing
resistor.
136 136
R
T
. . .
..
=
f C kHz pF
OSC T
=Ω =Ω
13 6 14
=
×
100 1000
k ChooseR k
×
T
10
(7)
(8)
The required value for R18 can therefore be found by
equating:
SC A S
=×
PWM SC PWM
where ASC is the amount of slope compensation and
solving for R18.
Page 11
ML4819
The value of R9 (pin 3) depends on the selection of R
2
(pin 6).
V
IN MAX PEAK
R
R
()
2
ImA
SINE PEAK
()
CLAMP
()
×
2
VR
9
V
IN MIN PEAK
×
260 1 414
072
.
×
4 8 510
.
=
×
80 1 414
.
=
Ω
k
=
.
k
510==
22>
Ω
k
Ω
(12)
(13)
Choose R9 = 27kW
The peak of the inductor current can be found
approximately by:
I
LPEAK
.
=
V
IN MIN RMS
OUT
()
=
×
1 414 200
.
90
=
314
.
A
(14)
P
×
1 414
Next select NC, which depends on the maximum switch
current. Assume 4A for this example. NC is 80 turns.
VN
R
11
Where R11 is the sense resistor, and V
×
CLAMP C
I
LPEAK
49 80
.
=
×
4
100=
=Ω
is the current
CLAMP
(15)
clamp at the inverting input of the PWM comparator. This
clamp is internally set to 5V. In actual application it is a
good idea to assume a value less than 5V to avoid
unwanted current limiting action due to component
tolerances. In this application V
Having calculated R11 the value S
was chosen as 4.8V.
CLAMP
and of R18 can
PWM
now be calculated:
V
−
S
PWM
380 202100
=
mH
×= µ
80
Vs
0 225./
VOLTAGE REGULATION COMPONENTS
The values of the voltage regulation loop components are
calculated based on the operating output voltage. Note
that voltage safety regulations require the use of sense
resistors that have adequate voltage rating. As a rule of
thumb if 1/4W through-hole resistors are used, two of
them should be put in series. The input bias current of the
error amplifier is approximately 0.5µA, therefore the
current available from the voltage sense resistors should
be significantly higher than this value. Since two 1/4W
resistors have to be used the total power rating is 1/2W.
The operating power is set to be 0.4W then with 380V
output voltage the value can be calculated as follows:
RVWk
5
2
380 0 4 360==()/. Ω
(17)
Choose two 178kW, 1% connected in series.
Then R6 can be calculated using the formula below:
VR
R
6
×
REF
VV
−
B REF
Vk
5 356
×
5
=
380 5
Ω
VV
−
=
Ω.
(18)
k
4 747=
Choose 4.75kW, 1%. One more critical component in the
voltage regulation loop is the feedback capacitor for the
error amplifier. The voltage loop bandwidth should be set
such that it rejects the 120Hz ripple which is present at
the output. If this ripple is not adequately attenuated it
will cause distortion on the input current waveform.
Typical bandwidths range anywhere from a few Hertz to
15Hz. The main compromise is between transient
response and distortion. The feedback capacitor can be
calculated using the following formula:
C
=
8
3 142
C
=
8
3 142 356 2
1
RBW
××
.
5
1
.
kHz
××
Ω
044
.
=µ
F
(19)
25
×
.
R
=
R
18
R
18
×××
AS RC
SC PWM T T
=
0 7 0 225 10 14 1
××××
.(. ) Ω
9
2 5 28 8
×
..
k
6
≅
knF
30
Ω
k
Choose R18 = 33kW
The following values were used in the calculation:
R9 = 27kW ASC = 0.7
RT = 14kW CT = 1nF
(16)
11
Page 12
ML4819
OVERVOLTAGE PROTECTION (OVP) COMPONENTS
The OVP loop should be set so that there is no interaction
with the voltage control loop. Typically it should be set to
a level where the power components are safe to operate.
Ten to fifteen volts above V
seems to be adequate.
OUT
This sets the maximum transient output voltage to about
395V.
By choosing the high voltage side resistor of the OVP
circuit the same way as above i.e. R7 = 356K then R8 can
be calculated as:
VR
R
8
VV
OVP REF
REF
×
−
7
5 356
=
Vk
×
Ω
VV
395 5
=
−
k
4 564=
Ω.
(20)
Choose 4.53kW, 1%.
Note that R5, R6, R7 and R8 should be tight tolerance
resistors such as 1% or better.
OFF-LINE START-UP AND BIAS SUPPLY GENERATION
The Start-Up circuit in Figure 12 can be either a “bleed
resistor” (39kW, 2W) or the circuit shown in Figure 13. The
bleed resistor method offers advantage of simplicity and
lowest cost, but may yield excessive turn-on delay at low
line.
When the voltage on pin 15 (VCC) exceeds 16V, the IC
starts up. The energy stored on the C21 supplies the IC
with running power until the supplemental winding on T3
can provide the power to sustain operation.
IN
START-UP
CIRCUIT
R33
V
REF
2kΩ
R32
2kΩ
Q5
2N2222
R31
510kΩ
C21
0.1
D16
22V
R30
4.3kΩ
Q6
IRF821
D15
1N4001
OUT
TO V
CC
PWM SECTION
The PWM section in Figure 12 is a two switch forward
converter, shown in Figure 14 below for clarity. This fully
clamped circuit eliminates the need for very high
voltage MOSFETs. Flyback topology is also possible with
the ML4819.
385VDC
Q2
T2
D12
ML4819
D11
T2
T3
Q3
Figure 14. Two-Switch Forward Converter
This regulator (Figure 12) uses current mode control.
Current is sensed through R24 and filtered for high
frequency noise and leading edge transient through T23
and C14. The main regulation loop is through PWM B. The
TL431 (U3) in the secondary serves as both the voltage
reference and error amplifier. Galvanic isolation is
provided by an optocoupler (U2) which provides a current
command signal on pin 8. Loop compensation is provided
by R29 and C20. The output voltage is set by:
V
=+
OUT
25 1
.
R
29
R
28
(21)
The control loop is compensated using standard
compensation techniques.
Current is limited to a threshold of 2A (1V on R24). The duty
cycle is limited in this circuit to below 50% to prevent
transformer (T3) core saturation. The maximum duty cycle
limit of 45% is set using a threshold of V
/2 on pin 7.
REF
Figure 13. Start-Up Circuit
ENHANCEMENT CIRCUIT
The power factor enhancement circuit (inside the dotted
lines) in Figure 11 is described in Application Note 11. It
improves the power factor and lowers the input current
harmonics. Note that the circuit meets IEC1000-3-2
specifications (with the enhancement circuit installed) on
the harmonics by a large margin while correcting the
input power factor to better than 0.99 under most steady
state operating conditions.
12
the circuit in Figure 12 can be modified for voltage mode
operation by utilizing the slope current which appears on
pin 9 as show in figure 15 below.
The ramp amplitude appearing on pin 9 will be:
I
18
R
V
=×
R
()
RV
2
(22)
where R18 is the slope compensation resistor. Since this
circuit operates with a constant input voltage (as supplied
by the PFC section) voltage feed-forward is unnecessary.
Page 13
V
SLOPE
COMP.
I
RSC
2
+
–
+
–
+
–
OSC
OSC
DUTY CYCLE
I
1V
I
SENSE
–
0.7V
+
PWM B
20
7
11
9
8
C6
FROM
R23, C14
FROM U2, R15
C
T
LIM
BR
REF
R13
R14
V
Figure 15. Voltage Mode Configuration
CONSTRUCTION AND LAYOUT TIPS
High frequency power circuits require special care during
breadboard construction and layout. Double sided printed
circuit boards with ground plane on one side are highly
recommended. All critical switching leads (power FET,
output diode, IC output and ground leads, bypass
capacitors) should be kept as small as possible. This is to
minimize both the transmission and pickup of switching
noise.
ML4819
There are two kinds of noise coupling; inductive and
capacitive. As the name implies inductive coupling is
due to fast changing (high di/dt) circulating switching
currents. The main source is the loop formed by Q1, D6,
and
C3–C4. Therefore this loop should be as small as possible,
and the above capacitors should be good, high frequency
types.
The second form of noise coupling is due to fast changing
voltages (high dv/dt). The main source in this case is the
drain of the power FET. The radiated noise in this case can
be minimized by insulating the drain of the FET from the
heatsink and then tying the heatsink to the source of the
FET with a high frequency capacitor.
The IC has two ground pins named PWR GND and Signal
GND. These two pins should be connected together with a
very short lead at the printed circuit board exit point. In
general grounding is very important and ground loops
should be avoided. Star grounding schemes are preferred.
13
Page 14
ML4819
Component Values/Bill of Materials for Figure 12
Reference Description
C1, C3 0.6µF, 630V Film (250 VAC)
C2 330µF 25V Electrolytic
C4 6800pF 1KV Ceramic
C5, C6 1000pF
C7 10µF 35V
C8, C11, C13, C15, C16 1µF Ceramic
C9, C20, C21 0.1µF Ceramic
C10 1500µF 25V Electrolytic
C12, C17 1µF Ceramic
C14 2200 pF
C18 1500µF 16V Electrolytic
C19 4.7µF
D1- D5 1N5406
D6 MUR850
D7, D10 1N4148
D8 3V Zener diode or 4 x 1N4148
in series
D9 MUR110
D11, D12 MUR150
D13 D83-004K
D15 1N4001
D16, D14 1N5818 or 1N5819
F1 5A, 250V, 3AG
L1 2mH, 4A I
Core: Ferroxcube 4229-3CB
150 Turns #24 AWG
0.150" gap
L2 10mH
Core: Spang OF 43019 UG00
8 Turns #15AWG gap 0.05"
Q1-Q3 IRF840
Q4, Q5 2N2222
Q6 IRF821
R1 330ký
PEAK
Reference Description
R4 12ký
R5, R7 357ký, 1%
R6 4.57ký, 1%
R8 4.53ký, 1%
R9 27ký
R10, R18 33ký
R11 91ý
R12, R22 10ý
R13, R14 4.7ký
R15 4.3ký
R16 15ký
R17 3 ý
R20 7.5ý
R21,R19 3 k ý
R23 100ý
R24, R25 1 ý
R26 1.5ký
R27 1.2ký
R28 8.66ký, 1%
R29 2.26ký, 1%
R30 2ký, 1W
R32, R33 2ký
T1 Spang F41206-TC or
Siemens B64290-K45-X27 or X830 or
Ferroxcube 768T188-38
NS = 80, NP = 1
T2 Same core as T1
NS = NP = 15 bifilar
T3 Core: Ferroxcube 4229-3C8
Pri. 44 Turns #18 Litz wire
Sec. 4 Turns of copper strip
Aux. 2 Turns #24 AWG
U2 MOC8102
U3 TL431
R2, R31 510ký
R3 5.6ký
14
Page 15
PHYSICAL DIMENSIONS inches (millimeters)
Package: P20
20-Pin PDIP
1.010 - 1.035
(25.65 - 26.29)
20
ML4819
0.060 MIN
(1.52 MIN)
(4 PLACES)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
PIN 1 ID
1
0.055 - 0.065
(1.40 - 1.65)
0.016 - 0.022
(0.40 - 0.56)
0.100 BSC
(2.54 BSC)
SEATING PLANE
0.240 - 0.260
(6.09 - 6.61)
0.015 MIN
(0.38 MIN)
0.295 - 0.325
(7.49 - 8.26)
0º - 15º
0.008 - 0.012
(0.20 - 0.31)
ORDERING INFORMATION
PART NUMBER TEMPERATURE RANGE PACKAGE
ML4819CP 0°C to 70°C Molded DIP (P20)
ML4819CS (Obsolete) 0°C to 70°C Molded SOIC (S20)
© Micro Linear 1997 is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
DS4819-01
15
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