Datasheet ML4812CP Datasheet (Fairchild Semiconductor)

April 1998

ML4812

Power Factor Controller

GENERAL DESCRIPTION

The ML4812 is designed to optimally facilitate a peak

FEATURES

■ Precision buffered 5V reference (±0.5%)

current control boost type power factor correction system.
Special care has been taken in the design of the ML4812
to increase system noise immunity. The circuit includes a

■ Current-input gain modulator reduces external

components and improves noise immunity
precision reference, gain modulator, error amplifier, over­voltage protection, ramp compensation, as well as a high

■ Programmable ramp compensation circuit

current output. In addition, start-up is simplified by an
under-voltage lockout circuit with 6V hysteresis.

In a typical application, the ML4812 functions as a
current mode regulator. The current which is necessary to

■ 1A peak current totem-pole output drive

■ Overvoltage comparator helps prevent output

voltage “runaway”
terminate the cycle is a product of the sinusoidal line
voltage times the output of the error amplifier which is
regulating the output DC voltage. Ramp compensation is

■ Wide common mode range in current sense

comparators for better noise immunity
programmable with an external resistor, to provide stable
operation when the duty cycle exceeds 50%.

■ Large oscillator amplitude for better noise immunity

BLOCK DIAGRAM (Pin Configuration Shown is for DIP Version)

OVP

5

I

SENSE

1

GM OUT

2

EA OUT

3

EA–

4

5V

5V

5V

+
–

+
–
–

ERROR

AMP

+
–

I

EA

SRQ

Q

UNDER
VOLTAGE
LOCKOUT

SHDN

OUT

V

V

32V

REF

CC

10

12

11

14

13

V

CC

PWR GND

I

SINE

6

RAMP COMP

7

C

T

16

R

T

8

GAIN MODULATOR

OSC

GND

15

5V

CLOCK

9

1kΩ

REV. 1.0 10/10/2000

ML4812

PIN CONFIGURATION

ML4812

16-Pin PDIP (P16)

1

I

SENSE

OVP

I

SINE

EA–

R

T

2

3

4

5

6

7

8

TOP VIEW

GM OUT

EA OUT

RAMP COMP

PIN DESCRIPTION

PIN NAME FUNCTION

ML4812

20-Pin PLCC (Q20)

16

C

T

15

GND

14

V

REF

13

V

CC

12

OUT

11

PWR GND

10

SHDN

9

CLOCK

EA OUT

PIN NAME FUNCTION

OVP

I

SINE

EA–

NC

4
5
6
7
8

SENSE

GM OUT

I

NC

CTGND

3212019

910111213

T

R

NC

SHDN

CLOCK

RAMP COMP

TOP VIEW

18
17
16
15
14

V

REF

V

CC

NC
OUT
PWR GND

1 I

SENSE

Input from the current sense
transformer to the non-inverting input
of the PWM comparator.

2 GM OUT Output of gain modulator.

A resistor to ground on this pin
converts the current to a voltage.
This pin is clamped to 5V and tied
to the inverting input of the PWM
comparator.

3 EA OUT Output of error amplifier.

4 EA– Inverting input to error amplifier.

5 OVP Input to over voltage comparator.

6 I

SINE

Current gain modulator input.

7 RAMP

COMP Buffered output from the oscillator

ramp (C

). A resistor to ground sets the

T

current which is internally subtracted
from the product of I

and IEA in

SINE

the gain modulator.

8R

T

Oscillator timing resistor pin. A 5V
source sets a current in the external
resistor which is mirrored to charge
C

.

T

9 CLOCK Digital clock output.

10 SHDN A TTL compatible low level on this pin

turns off the output.

11 PWR GND Return for the high current totem pole

output.

12 OUT High current totem pole output.

13 V

14 V

CC

REF

Positive Supply for the IC.

Buffered output for the 5V voltage
reference.

15 GND Analog signal ground.

16 C

T

Timing capacitor for the oscillator.

2 REV. 1.0 10/10/2000

ABSOLUTE MAXIMUM RATINGS

ML4812

Absolute maximum ratings are those values beyond
which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and
functional device operation is not implied.

Junction Temperature ............................................. 150°C

Storage Temperature Range ..................... –65°C to 150°C

Lead Temperature (soldering 10 sec.) ..................... 260°C

Thermal Resistance (θ

)

JA

20-Pin PLCC .................................................... 60°C/W

Supply Current (I

) ............................................... 30mA

CC

16-Pin PDIP .................................................... 65°C/W

Output Current Source or Sink (OUT) DC................ 1.0A

Output Energy (capacitive load per cycle) .................. 5µJ

Gain Modulator I

SINE

Input (I

) ......................... 1.2mA

SINE

Error Amp Sink Current (EA OUT).......................... 10mA

Oscillator Charge Current ........................................ 2mA

Analog Inputs (I

, EA–, OVP) ............... –0.3V to 5.5V

SENSE

OPERATING CONDITIONS

Temperature Range

ML4812CX ................................................ 0°C to 70°C

ML4812IX ............................................. –40°C to 85°C

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, VCC = 15V , RT = 14kΩ, CT = 1000pF, TA = Operating Temperature Range (Notes 1, 2).

PARAMETER CONDITIONS MIN TYP MAX UNITS

OSCILLATOR

Initial Accuracy TJ = 25°C 91 98 105 kHz
Voltage Stability 12V < VCC < 18V 0.3 %
Temperature Stability 2%
Total Variation Line, temperature 90 108 kHz
Ramp Valley to Peak 3.3 V
RT Voltage 4.8 5.0 5.2 V
Discharge Current (RT open) TJ = 25°C, VCT= 2V 7.8 8.4 9.0 mA

VCT = 2V 7.3 8.4 9.3 mA
Clock Out Voltage Low RL = 16kΩ 0.2 0.5 V
Clock Out Voltage High RL = 16kΩ 3.0 3.5 V

REFERENCE

Output Voltage TJ = 25°C, IO = 1mA 4.95 5.00 5.05 V
Line Regulation 12V < VCC < 25V 2 20 mV
Load Regulation 1mA < IO < 20mA 2 20 mV
Temperature Stability 0.4 %
Total Variation Line, load, temp. 4.9 5.1 V
Output Noise Voltage 10Hz to 10kHz 50 µV
Long Term Stability TJ = 125°C, 1000 hours 5 25 mV
Short Circuit Current V

ERROR AMPLIFIER

Input Offset Voltage ±15 mV
Input Bias Current –0.1 –1.0 µA
Open Loop Gain 1 < V
PSRR 12V < VCC < 25V 60 75 dB
Output Sink Current V
Output Source Current V
Output High Voltage I
Output Low Voltage I
Unity Gain Bandwidth 1.0 MHz

= 0V –30 –85 –180 mA

REF

< 5V 60 75 dB

EA OUT

EA OUT

EA OUT

EA OUT

EA OUT

= 1.1V, V
= 5.0V, V

= –0.5mA, V

= 1mA, V

= 6.2V 2 12 mA

EA–

= 4.8V –0.5 –1.0 mA

EA–

= 4.8V 5.3 5.5 V

EA–

= 6.2V 0.5 1.0 V

EA–

REV. 1.0 10/10/2000 3

ML4812

ELECTRICAL CHARACTERISTICS (Continued)

PARAMETER CONDITIONS MIN TYP MAX UNITS

GAIN MODULATOR

I

Input Voltage I

SINE

Output Current (GM OUT) I

Bandwidth 200 kHz
PSRR 12V < VCC < 25V 70 dB

OVP COMPARATOR

Input Offset Voltage Output Off –25 +5 mV
Hysteresis Output On 95 105 115 mV
Input Bias Current –0.3 –3 µA
Propagation Delay 150 ns

PWM COMPARATOR: I

SENSE

Input Offset Voltage ±15 mV
Input Offset Current ±1 µA
Input Common Mode Range –0.2 5.5 V
Input Bias Current –2 –10 µA
Propagation Delay 150 ns
I

Trip Point V

LIMIT

OUTPUT

Output Voltage Low I

Output Voltage High I

Output Voltage Low in UVLO I
Output Rise/Fall Time CL = 1000pF 50 ns
Shutdown V

UNDER-VOLTAGE LOCKOUT

Startup Threshold 15 16 17 V
Shutdown Threshold 9 10 11 V
V

Good Threshold 4.4 V

REF

SUPPLY

Supply Current Start-Up, VCC = 14V, TJ = 25°C 0.8 1.2 mA

Internal Shunt Zener Voltage ICC = 30mA 25 30 34 V

= 500µA 0.4 0.7 0.9 V

SINE

= 500µA, EA– = V

SINE

I

= 500µA, EA– = V

SINE

I

= 1mA, EA– = V

SINE

I

= 500µA, EA– = V

SINE

I

RAMP COMP

GM OUT

OUT

I

OUT

OUT

I

OUT

OUT

IH

V

IL

IIL, V

IIH, V

= 50µA

= 5.5V 4.8 5 5.2 V

= –20mA 0.1 0.4 V
= –200mA 1.6 2.2 V
= 20mA 13 13.5 V
= 200mA 12 13.4 V
= –5mA, VCC = 8V 0.1 0.8 V

= 0V –1.5 mA

SHDN

= 5V 10 µA

SHDN

–20mV 430 470 510 µA

REF

+ 20mV 3 10 µA

REF

– 20mV 860 940 1020 µA

REF

– 20mV, 455 µA

REF

2.0 V

0.8 V

Operating, TJ = 25°C2025mA

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: V

is raised above the Startup Threshold first to activate the IC, then returned to 15V.

CC

4 REV. 1.0 10/10/2000

FUNCTIONAL DESCRIPTION

ML4812

OSCILLATOR

The ML4812 oscillator charges the external capacitor (C
with a current (I

) equal to 5/R

SET

. When the capacitor

SET

T

voltage reaches the upper threshold, the comparator
changes state and the capacitor discharges to the lower
threshold through Q1. While the capacitor is discharging,
Q2 provides a high pulse.

The Oscillator period can be described by the following
relationship:

EXTERNAL

CLOCK

C

SYNC

R

SYNC

I

SET

R

C

SYNC

10

R

T

9

T

C

T

16

T

8.4mA

I

SET

5.6V

Q

2

+

-

TT T

=+

OSC RAMP DEADTIME

)

where:

V

OUT

V

IN

=

-

D

1

ON

and:

´

CV

T RAM P VA LLEY TO PE AK

T

DEADTIME

(kΩ)

T

R

=

10

8

5

3

2

1

10 100 1000

5nF 2nF

10nF

20nF

OSCILLATOR FREQUENCY (kHz)

84.

-

mA I

SET

90%

1nF

85%

MAXIMUM DUTY CYCLE (%)

80%

70%

Figure 2. Oscillator Timing Resistance vs. Frequency

15

V

CC

14

13

SOURCE SATURATION

LOAD TO GROUND

SINK SATURATION

LOAD TO V

3

2

1

OUTPUT SATURATION VOLTAGE (V)

0

0 200 400 800

CC

OUTPUT CURRENT (mA)

VCC = 15V

80µs PULSED LOAD

120Hz RATE

GND

600

CLOCK

RAMP PEAK

RAMP VALLEY

Figure 1. Oscillator Block Diagram

V(CT)

Q

1

t

D

Figure 3. Output Saturation Voltage vs. Output Current

REV. 1.0 10/10/2000 5

ML4812

FUNCTIONAL DESCRIPTION (Continued)

OUTPUT DRIVER STAGE

The ML4812 output driver is a 1A peak output high speed
totem pole circuit designed to quickly drive capacitive
loads, such as power MOSFET gates. (Figure 3)

ERROR AMPLIFIER

The ML4812 error amplifier is a high open loop gain,
wide bandwidth, amplifier.(Figures 4-5)

GAIN MODULATOR

The ML4812 gain modulator is of the current-input type
to provide high immunity to the disturbances caused by
high power switching. The rectified line input sine wave is
converted to a current via a dropping resistor. In this way,
small amounts of ground noise produce an insignificant
effect on the reference to the PWM comparator. The
output of the gain modulator is a current of the form: I
is proportional to I
the dropping resistor, and I

SINE

5V

↔ I

where I

EA,

is a current proportional to

EA

+

is the current in

SINE

0.5mA

8V

OUT

the output of the error amplifier. When the error amplifier
is saturated high, the output of the gain modulator is
approximately equal to the I

input current. The gain

SINE

modulator output current is converted into the reference
voltage for the PWM comparator through a resistor to
ground on the gain modulator output. The gain modulator
output is clamped to 5V to provide current limiting.

Ramp compensation is accomplished by subtracting 1/2
of the current flowing out of RAMP COMP through a
buffer transistor driven by C

which is set by an external

T

resistor.

UNDER VOLTAGE LOCKOUT

On power-up the ML4812 remains in the UVLO
condition; output low and quiescent current low. The IC
becomes operational when V

reaches 16V. When V

CC

CC

drops below 10V, the UVLO condition is imposed.
During the UVLO condition, the 5V V

pin is “off”,

REF

making it usable as a “flag” for starting up a downstream
PWM converter.

ERROR CURRENT

I

SINE

6

9V

I
– I

ERROR CURRENT

SINE ×

RAMP COMP

/2

EA–

4

EA OUT

3

–

Figure 4. Error Amplifier Configuration

100

80

60

40

20

, OPEN LOOP GAIN (dB)

VOL

A

0

-20
100 10k 10M100k

10 1k 1M

GAIN

FREQUENCY (Hz)

PHASE

0

-30

-60

-90

-120

-150

-180

EXCESS PHASE (degrees)

GM OUT

2

RAMP COMP

7

C

T

16

I

RAMP COMP

5V

Figure 6. Gain Modulator Block Diagram

500

400

300

200

100

MULTIPLE OUTPUT CURRENT (µA)

0

0 200 300 500400100

SINE INPUT CURRENT (µA)

4.5

4.0

3.5

3.0

2.5

2.0

1.5

ERROR AMP OUTPUT VOLTAGE (V)

Figure 5. Error Amplifier Open-Loop Gain and

Figure 7. Gain Modulator Linearity

Phase vs Frequency

6 REV. 1.0 10/10/2000

TYPICAL APPLICATIONS

INPUT INDUCTOR (L1) SELECTION

ML4812

25

The central component in the regulator is the input boost
inductor. The value of this inductor controls various
critical operational aspects of the regulator. If the value is
too low, the input current distortion will be high and will
result in low power factor and increased noise at the
input. This will require more input filtering. In addition,
when the value of the inductor is low the inductor dries
out (runs out of current) at low currents. Thus the power
factor will decrease at lower power levels and/or higher
line voltages. If the inductor value is too high, then for a
given operating current the required size of the inductor
core will be large and/or the required number of turns
will be high. So a balance must be reached between
distortion and core size.

One more condition where the inductor can dry out is
analyzed below where it is shown to be maximum duty
cycle dependent.

For the boost converter at steady state:

V

V

OUT

Where D

Where D

input boost inductor will dry out when the following

input boost inductor will dry out when the following

condition is satisfied:

condition is satisfied:

IN

=

D

-1

ON

is the duty cycle [TON/(TON + T

is the duty cycle [TON/(TON + T

ON

ON

OFF

OFF

)]. The

)]. The

(1)

(1)

20

15

(mA)

CC

I

10

5

0

0

VCC (V)

3020 4010

Figure 9a. Total Supply Current vs. Supply Voltage

25

20

15

10

OPERATING CURRENT

(2)

Vt V D

() ( )<´-1

IN OUT ON

or

or

VD V

V

INDRY

V

OUT

=- ´

INDRY O N OUT

[(max)]1

: voltage where the inductor dries out.

: output DC voltage.

(2)

(3)

(3)

Effectively, the above relationship shows that the resetting
volt-seconds are more than setting volt-seconds. In energy
transfer terms this means that less energy is stored in the
inductor during the ON time than it is asked to deliver
during the OFF time. The net result is that the inductor
dries out.

ENABLE

V

REF

V

REF

GEN.

9V

–

+

INTERNAL

BIAS

5V V

V

REF

CC

SUPPLY CURRENT (mA)

5

STARTUP

0

–60 20 60 140100–20

–40 40 80 1200

TEMPERATURE (degrees)

Figure 9b. Supply Current (ICC) vs. Temperature

0

-4

-8

(mV)

-12

REF

∆V

-16

-20

-24
20 60 12080

0 40 100

I

(mA)

REF

Figure 10. Reference Load RegulationFigure 8. Under-Voltage Lockout Block Diagram

REV. 1.0 10/10/2000 7

ML4812

TYPICAL APPLICATIONS (Continued)

The recommended maximum duty cycle is 95% at
100KHz to allow time for the input inductor to dump its
energy to the output capacitors. For example, if: V

OUT

=
380V and DON (max) = 0.95, then substituting in (3)
yields V

= 20V. The effect of drying out is an

INDRY

increase in distortion at low voltages.

For a given output power, the instantaneous value of the
input current is a function of the input sinusoidal voltage
waveform, i.e. as the input voltage sweeps from zero volts
to a maximum value equal to its peak so does the current.

The load of the power factor regulator is usually a
switching power supply which is essentially a constant
power load. As a result, an increase in the input voltage
will be offset by a decrease in the input current.

By combining the ideas set forth above, some ground
rules can be obtained for the selection and design of the
input inductor:

Step 1: Find minimum operating current.

I

(min)

IN PEAK

.(min)

=

V

IN

IN

(max)

(4)

´1414

P

VIN(max) = 260V

PIN(min) = 50W

then:

IIN(min)

PEAK

= 0.272A

Step 2: Choose a minimum current at which point the

inductor current will be on the verge of drying
out. For this example 40% of the peak current
found in step 1 was chosen.

then:

I

= 100mA

LDRY

Step 3: The value of the inductance can now be found

using previously calculated data.

VD

=

L

1

=

100 100

´

INDRY ON

´

If

LDRY OSC

´

V

20 0 95

mA KHz

.

´

(max)

=

(5)

mH

2

The inductor can be allowed to decrease in value when
the current sweeps from minimum to maximum value.
This allows the use of smaller core sizes. The only
requirement is that the ramp compensation must be
adequate for the lower inductance value of the core so
that there is adequate compensation at high current.

Step 4: The presence of the ramp compensation will

change the dry out point, but the value found
above can be considered a good starting point.
Based on the amount of power factor correction
the above value of L1 can be optimized after a
few iterations.

Gapped Ferrites, Molypermalloy, and Powdered Iron
cores are typical choices for core material. The core
material selected should have a high saturation point and
acceptable losses at the operating frequency.

One ferrite core that is suitable at around 200W is the
#4119PL00-3C8 made by Philips Components
(Ferroxcube). This ungapped core will require a total gap
of 0.180" for this application.

OSCILLATOR COMPONENT SELECTION

The oscillator timing components can be calculated by
using the following expression:

OSC

´

RC

TT

(6)

136.

=

f

For example:

Step 1: At 100kHz with 95% duty cycle T

= 500ns

OFF

calculate CT using the following formula:

=

C

T

V

OSC

=

1000

pF

(7)

´

TI

OFF DIS

Step 2: Calculate the required value of the timing

resistor.

136 136

..

=

R

T

fC KHz pF

OSC T

=W =W

136 14

.

k choose R k

=

´

100 1000

´

T

(8)

8 REV. 1.0 10/10/2000

TYPICAL APPLICATIONS (Continued)

ML4812

CURRENT SENSE AND SLOPE (RAMP) COMPENSATION
COMPONENT SELECTION

Slope compensation in the ML4812 is provided internally.
Rather than adding slope to the noninverting input of the
PWM comparator, it is actually subtracted from the
voltage present at the inverting input of the PWM
comparator. The amount of slope compensation should be
at least 50% of the downslope of the inductor current
during the off time, as reflected to the inverting input of
the PWM comparator. Note that slope compensation is
required only when the inductor current is continuous
and the duty cycle is more than 50%. The downslope of
the inductor current at the verge of discontinuity can be
found using the expression given below:

di

dt

L

=

OUT INDRY

L

=

-

380 20

VV

2

mH

=m

018./

(9)

As

-

VV

The downslope as reflected to the input of the PWM
comparator is given by:

S

S

VV

=

PWM

380 202100

=

PWM

OUT INDRY

L

-

V

mH

R

S

´

N

C

´= m

0 225./

80

Vs

(10)

-

Where RS is the current sense resistor and NC is the turns
ratio of the current transformer (T1) used. In general,
current transformers simplify the sensing of switch
currents (especially at high power levels where the use of
sense resistors is complicated by the amount of power
they have to dissipate). Normally the primary side of the
transformer consists of a single turn and the secondary
consists of several turns of either enameled magnet wire
or insulated wire. The diameter of the ferrite core used in
this example is 0.5" (SPANG/Magnetics F41206-TC). The
rectifying diode at the output of the current transformer
can be a 1N4148 for secondary currents up to 75mA
average.

Sense FETs or resistive sensing can also be used to sense
the switch current. The sensed signal has to be amplified
to the proper level before it is applied to the ML4812.

The value of the ramp compensation (SC

) as seen at

PWM

the inverting terminal of the PWM comparator is:

´

25.

R

SC

=

PWM

RCR

TTSC

M

´´

(11)

The required value for RSC can therefore be found by
equating: SC

PWM

= A

SC

× S

where ASC is the amount

PWM,

of slope compensation and solving for RSC. The value of
GM OUT depends on the selection of RAMP COMP.

(max)

V

IN PEAK

==´=

R

P

ImA

()

SINE PEAK

260 1414

.

05

.

750

Ω

k

(12)

VR

=

R

M

´

CLAMP P

V

()

IN PEAK

.

4 9 750

=

90 1414

Ω

´

k

´

.

=

28 8

Ω

.

k

(13)

The peak of the inductor current can be found
approximately by:

I

LPE AK

P

V

IN RM S

OUT

()

=

=

´

1414 200

.

90

=

314

.

A

(14)

´

1414

.

Selection of NC which depends on the maximum switch
current, assume 4A for this example is 80 turns.

VN

=

R

S

Where RS is the sense resistor, and V

´

CLAMP C

I

LPE AK

49 80

.

=

´

4

=W

100

is the current

CLAMP

(15)

clamp at the inverting input of the PWM comparator. This
clamp is internally set to 5V. In actual application it is a
good idea to assume a value less than 5V to avoid
unwanted current limiting action due to component
tolerances. In this application, V

was chosen as

CLAMP

4.9V.

Having calculated RS, the value S

and of RSC can

PWM

now be calculated:

´

25

R

.

=

R

SC

R

SC

´´´

AS RC

SC PWM T T

=

´´´´

0 7 0 225 10 14 1

.(. )

M

´

25 288

..

k

6

Ω

KnF

=

Ω

33

k

(16)

The following values were used in the calculation:

R

= 28.8kΩ A

M

R

= 14kΩ C

T

= 0.7

SC

= 1nF

T

VOLTAGE REGULATION COMPONENTS

The values of the voltage regulation loop components are
calculated based on the operating output voltage. Note
that voltage safety regulations require the use of sense
resistors that have adequate voltage rating. As a rule of
thumb if 1/4W resistors are chosen, two of them should
be used in series. The input bias current of the error
amplifier is approximately 0.5µA, therefore the current
available from the voltage sense resistors should be
significantly higher than this value. Since two 1/4W
resistors have to be used the total power rating is 1/2W.
The operating power is set to be 0.4W then with 380V
output voltage the value can be calculated as follows:

==

RVWk

1

2

380 0 4 360

()/.

Ω

(17)

Choose two 178kΩ, 1% connected in series. Then R2 can
be calculated using the formula below:

´

VR

REF

=

R

2

VV

OUT REF

1

-

´

5356

Vk

=

-

380 5

VV

Ω

=

4747

.

Ω

k

(18)

REV. 1.0 10/10/2000 9

ML4812

TYPICAL APPLICATIONS (Continued)

Choose 4.75kΩ, 1%. One more critical component in the
voltage regulation loop is the feedback capacitor for the
error amplifier. The voltage loop bandwidth should be set
such that it rejects the 120Hz ripple which is present at
the output. If this ripple is not adequately attenuated it
will cause distortion on the input current waveform.
Typical bandwidths range anywhere from a few Hertz to
15Hz. The main compromise is between transient
response and distortion. The feedback capacitor can be
calculated using the following formula:

=

C

F

=

C

F

1

´´

RBW

3142

.

1

1

´´

Ω

3142 356 2

.

kHz

=m

044

.

F

(19)

OVERVOLTAGE PROTECTION (OVP) COMPONENTS

The OVP loop should be set so that there is no interaction
with the voltage control loop. Typically it should be set to
a level where the power components are safe to operate.
Ten to fifteen volts above V

is generally a good

OUT

setpoint. This sets the maximum transient output voltage
to about 395V. By choosing the high voltage side resistor
of the OVP circuit the same way as above i.e. R
then R

Choose 4.53kΩ, 1%. Note that R

can be calculated as:

5

´

VR

REF

=

R

5

VV

OVP REF

4

-

´

5356

Vk

=

-

395 5

VV

Ω

=

, R2, R4 and R5 should

1

4564

.

Ω

k

= 356K

4

(20)

be tight tolerance resistors such as 1% or better.

CONTROLLER SHUTDOWN

The ML4812 provides a shutdown pin which could be
used to shutdown the IC. Care should be taken when this
pin is used because power supply sequencing problems
could arise if another regulator with its own bootstrapping
follows the ML4812. In such a case a special circuit
should be used to allow for orderly start up. One way to
accomplish this is by using the reference voltage of the
ML4812 to inhibit the other controller IC or to shut down
its bias supply current.

OFF-LINE START-UP AND BIAS SUPPLY GENERATION

The ML4812 can be started using a “bleed resistor” from
the high voltage bus. After the voltage on V

exceeds

CC

16V, the IC starts up. The energy stored on the 330µF,
C15, capacitor supplies the IC with running power until
the supplemental winding on L1 can provide the power to
sustain operation.

The values of the start-up resistor R10 and capacitor C15
may need to be optimized depending on the application.
The charging waveform for the secondary winding of L1 is
an inverted chopped sinusoid which reaches its peak
when the line voltage is at its minimum. In this example,
C9 = 0.1µF, C15 = 330µF, D8 = 1N4148, R10 = 39kΩ,
2W.

ENHANCEMENT CIRCUIT

The power factor enhancement circuit shown in Figure 12
is described in detail in Application Note 11. It improves
the power factor and lowers the input current harmonics.
Note that the circuit meets IEC 1000-3-2 specifications
(with the enhancement) on the harmonics by a large
margin while correcting the input power factor to better
than 0.99 under most steady state operating conditions.

CONSTRUCTION AND LAYOUT TIPS

High frequency power circuits require special care during
breadboard construction and layout. Double sided printed
circuit boards with ground plane on one side are highly
recommended. All critical switching leads (power FET,
output diode, IC output and ground leads, bypass
capacitors) should be kept as small as possible. This is to
minimize both the transmission and pick-up of switching
noise.

There are two kinds of noise coupling; inductive and
capacitive. As the name implies inductive coupling is due
to fast changing (high di/dt) circulating switching currents.
The main source is the loop formed by Q1, D5, and
C3–C4. Therefore this loop should be as small as possible,
and the above capacitors should be good high frequency
types.

The second form of noise coupling is due to fast changing
voltages (high dv/dt). The main source in this case is the
drain of the power FET. The radiated noise in this case can
be minimized by insulating the drain of the FET from the
heatsink and then tying the heatsink to the source of the
FET with a high frequency capacitor (C

in Figure 12).

H

The IC has two ground pins named PWR GND and Signal
GND. These two pins should be connected together with
a very short lead at the printed circuit board exit point. In
general grounding is very important and ground loops
should be avoided. Star grounding or ground plane
techniques are preferred.

10 REV. 1.0 10/10/2000

TYPICAL APPLICATIONS (Continued)

MATERIAL MANUFACTURER PART # TURNS (#24AWG)

Powdered Iron Micrometals T225-8/90 200
Powdered Iron Micrometals T184-40 120

Molypermalloy SPANG (Mag. Inc.) 58076-A2 (high flux) 180

Table 1. Toroidal Cores (L1)

ML4812

MAGNETICS TIPS

L1 — Main Inductor

As shown in Table 1, one of several toroidal cores can be
used for L1. The T184-40 core above is the most
economical, but has lower inductance at high current.
This would yield higher ripple current and require more
line EMI filtering. The value for R

(slope compensation

SC

resistor on RAMP COMP) was calculated for the T225-8/
90 and should be recalculated for other inductor
characteristics. The various core manufacturers have a
range of applications literature available. A gapped ferrite
core can also be used in place of the powdered iron core.
One such core is a Philips Components (Ferroxcube) core
#4229PL00-3C8. This is an ungapped core. Using 145
turns of #24 AWG wire, a total air gap of 0.180" is
required to give a total inductance of about 2mH. Since
1/2 of the gap will be on the outside of the core and 1/2
the gap on the inside, putting a 0.09" spacer in the center
will yield a 0.180" total gap. To prevent leakage fields
from generating RFI, a shorted turn of copper tape should
be wrapped around the gap as shown in Figure 11. For
production, a gapped center leg can be ordered from most
core vendors, eliminating the need for the external
shorted copper turn when using a potentiometer core.

T1 — Sense Transformer

In addition to the core type mentioned in the parts list, the
following Siemens cores should be suitable for
substitution and may be more readily available in Europe.

MATERIAL SIZE CODE PART #

N27 R16/6.3 B64290-K45-X27
N30 R16/6.3 B64290-K45-X830

The N27 material is for high frequency and will work
better above 100KHz but both are adequate. In addition,
Philips Components (Ferroxcube) core 768T188-3C8 can
be used. Please also refer to the list of core vendors below

SPANG/Magnetics Inc. 1 [phone], or

[phone]
Micrometals 1 [phone]
Philips Components [phone]

COPPER FOIL

SHORTED TURN

0.09" GAP

Figure 11. Copper Foil Shorted Turn

REV. 1.0 10/10/2000 11

ML4812

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

90 TO

260 VAC

AC IN

P

1

FUSE F1

5A 250V

L

N

C

1

1µF

630V

D

1

1N5406

D

2

1N5406

D

3

1N5406

R

GMOUT

27kΩ

D

10

1N5406

OPTIONAL

ENHANCEMENT

CKT.

R

12

1K

C

17

Q

3

C

19

+

D

13

D

12

D

11

R

3

22kΩ

C

F

D

4

1N5406

R

2A

10kΩ

R

2B

3.9kΩ

R

5B

3.9kΩ

R

5A

10kΩ

R

1B

180kΩ

R

4B

180kΩ

R

PB

150kΩ

R

PA

360kΩ

R

4A

180kΩ

1

2

N

P

N

S

R

10

39kΩ

2W

R

SC

33kΩ

R

T

7.5kΩ

ML4812

IC

1

C

16

100µF

25V

+

D

9

D

8

Q

2

7812

C

T

2nF

C15

P3*

C10

1µF

330µF

25V

V

CC

D

5

MUR850

OFF-LINE START-UP

AND BIAS SUPPLY

C

18

R

11

33kΩ

C

11

1nF

D

6

T

1

A

B

R

S

100

C

9

0.1µF

C

8

0.1µF

R

G

10

+

–

Q

1

IRF840

HEATSINK

C

H

6.8nF

R

7

150kΩ

1W

R

6

150kΩ

1W

C

3

6.8nF

1kV

C

4

1µF

630V

C

5

680µF

200V

C

6

680µF

200V

P

2

V

OUT

380 VDC

** SEE NOTES BELOW

NOTES:

1. ALL UNSPECIFIED DIODES ARE 1N4148.

2. ALL UNSPECIFIED RESISTORS ARE 1/4 WATT.

3. ALL UNSPECIFIED CAPACITOR VOLTAGE RATINGS ARE 50V.

4. ADJUST R

2A

AND R

5A

WITH CAUTION TO AVOID OVER VOLTAGE CONDITIONS.

Q

3

= 2N2222 OR EQUIVALENT.

P3 IS USED AT INITAL TURN-ON TO

CHECK THE IC FOR PROPER OPERATION.

APPLY ≈ 16VDC.

FIXED RESISTORS CAN BE USED FOR THE SENSING

COMPONENTS. BELOW ARE 1% STANDARD

RESISTORS THAT WILL FORCE THE CORRECT

OUTPUT VOLTAGES R1A, R1B, R4A, R4B = 178k

Ω 1%,

R2B = 4.75 1%, R5B = 4.53k

Ω 1%.

USE JUMPERS INSTEAD OF R2A AND R5A (POTS).

FOR HIGHER POWER USE MORE V

CC

DECOUPLING.

2µF OR MORE BE REQUIRED AT 1KW LEVELS.

*

**

***

R

13

22kΩ

R

1A

180kΩ

L

1

***

+

–

+

12 REV. 1.0 10/10/2000

Figure 12. Typical Application, 200W Power Factor Correction Circuit

ML4812

REFERENCE DESCRIPTION

C1, C4 1µF, 630V Film (250VAC)
C3, C

H

6.8nF, 1KV Ceramic disk

C5, C6 680µF, 200V Electrolytic
C8, C9 0.1µF, 50V Ceramic
C10, C19 1µF, 50V Ceramic
C11 0.001µF, 50V Ceramic
C15 330µF, 25V Electrolytic
C16 100µF, 25V Electrolytic
C17 10µF, 25V Electrolytic
C

F

C

T

0.47µF, 50V Ceramic

0.002µF, 50V Ceramic

D1, D2, D3, D4, D10 1N5406 (Motorola)
D5 MUR850 (Motorola)
D6, D8, D9 1N4148

D11, D12, D13
F1 5A, 250V 3AG with clips
IC1 ML4812CP (Micro Linear)
L1 2mH, 4A I

PEAK

(see note)
Q1 IRF840 or MTPN8N50
Q2 LM7815CT
Q3 2N2222 or equivalent

REFERENCE DESCRIPTION

R1A, R1B, R4A, R4B 180kΩ
R2A, R5A 10kΩ TRIMPOT BOURNS

3299 or equivalent

R2B, R5B 3.9kΩ
R3, R13 22kΩ
R6, R7, RPB 150kΩ
R10 39kΩ, 2W
R11 33kΩ
R12 1kΩ
RG 10Ω
RM 27kΩ
RPA, R15 360kΩ
RS 100kΩ
RSC 33kΩ
RT 7.5kΩ
T1 SPANG F41206-TC

NS = 80, NP = 1 (see note)

Notes: All resistors 1/4W unless otherwise specified. Some reference designators

are skipped (e.g. C2, C12, etc.) and do not appear on the schematic.
These designators were used in previous revisions of the board and are
not used on this revision. Additional information on key components is
included in the attached appendix.

Table 2. Component Values/Bill of Materials for Figure 12

REV. 1.0 10/10/2000 13

ML4812

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

+

C12

1µF

630V

C10

680µF

250V

C11

680µF

250V

GND

V

OUT

C9

15µF

630V

C8

15µF

630V

D5 MUR3050

R4

150K

1W

R5

150K

1W

–

APT5025

GND

1T

Q2

APT5025

Q1

T1

D4

80T

C14

1µF

***

RG1

3

RG2

3

C7

0.1µF

C4

0.1µF

RS

22Ω

C5

1nF

V

CC

CT 2.2nF

R3

33K

R722K

IC1

ML4812

RT

6.2K

RSC

51K

L1

566µH

RPA

360K

RPB

150K

R4A

360K

R4B

180K

R1B

180K

R1A

180K

CF

R5A

5K

R5B

3K

R2B

3K

R2A

5K

RM

27K

D1

1N5406

BRIDGE

RECTIFIER

C3

1µF

500V

C2

1µF

500V

C1

1µF

500V

FUSE F1

15A 250V

L

AC

IN

N

R1 R2

330K 22K R6

C13

10µF

GND

V

CC

Q3

D2

V

Z

3.5V

+

ENHANCEMENT CIRCUIT SEE TEXT

2N2222

**

C6

1µF

NOTES:

1. ALL UNSPECIFIED DIODES ARE 1N4148.

2. ALL UNSPECIFIED RESISTORS ARE 1/4 WATT.

3. ALL UNSPECIFIED CAPACITOR VOLTAGE RATINGS ARE 50V.

4. ADJUST R

2A

AND R

5A

WITH CAUTION TO AVOID OVER VOLTAGE CONDITIONS.

Q

3

= 2N2222 OR EQUIVALENT.

AT INITIAL TURN-ON TO CHECK

THE IC FOR PROPER OPERATION,

APPLY ≈ 16VDC.

FIXED RESISTORS CAN BE USED FOR THE SENSING

COMPONENTS. BELOW ARE 1% STANDARD

RESISTORS THAT WILL FORCE THE CORRECT

OUTPUT VOLTAGES R1A, R1B, R4A, R4B = 178k

Ω 1%,

R2B = 4.75Ω 1%, R5B = 4.53k

Ω 1%.

USE JUMPERS INSTEAD OF R2A AND R5A (POTS).

FOR HIGHER POWER USE MORE V

CC

DECOUPLING.

*

**

***

14 REV. 1.0 10/10/2000

Figure 13. 1kW Input Power, Power Factor Correction Circuit

PHYSICAL DIMENSIONS inches (millimeters)

0.740 - 0.760

(18.79 - 19.31)

16

ML4812

Package: P16

16-Pin PDIP

0.02 MIN
(0.50 MIN)
(4 PLACES)

0.170 MAX
(4.32 MAX)

0.125 MIN
(3.18 MIN)

PIN 1 ID

1

0.055 - 0.065
(1.40 - 1.65)

0.016 - 0.022
(0.40 - 0.56)

0.385 - 0.395

(8.89 - 10.03)

0.350 - 0.356
(8.89 - 9.04)

1

0.100 BSC
(2.54 BSC)

SEATING PLANE

Package: Q20

20-Pin PLCC

0.240 - 0.260
(6.09 - 6.61)

0.015 MIN
(0.38 MIN)

0.295 - 0.325
(7.49 - 8.26)

0º - 15º

0.042 - 0.056
(1.07 - 1.42)

0.008 - 0.012
(0.20 - 0.31)

0.025 - 0.045
(0.63 - 1.14)

(RADIUS)

0.042 - 0.048
(1.07 - 1.22)

PIN 1 ID

6

0.050 BSC
(1.27 BSC)

0.026 - 0.032
(0.66 - 0.81)

0.013 - 0.021
(0.33 - 0.53)

11

SEATING PLANE

0.350 - 0.356

16

(8.89 - 9.04)

0.165 - 0.180
(4.19 - 4.57)

0.385 - 0.395

(8.89 - 10.03)

0.146 - 0.156
(3.71 - 3.96)

0.200 BSC
(5.08 BSC)

0.009 - 0.011
(0.23 - 0.28)

0.100 - 0.110
(2.54 - 2.79)

0.290 - 0.330
(7.36 - 8.38)

REV. 1.0 10/10/2000 15

ML4812

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE

ML4812CP 0°C to 70°C Molded PDIP (P16)

ML4812CQ 0°C to 70°C Molded PLCC (Q20)

ML4812IP –40°C to 85°C Molded PDIP (P16)

ML4812IQ –40°C to 85°C Molded PLCC (Q20)

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

www.fairchildsemi.com © 2000 Fairchild Semiconductor Corporation

2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

16 REV. 1.0 10/10/2000