Datasheet ML4805IS, ML4805CS, ML4805IP Datasheet (Fairchild Semiconductor)

November 1998

PRELIMINARY

ML4805

Variable Feedforward PFC/PWM Controller Combo

GENERAL DESCRIPTION

The ML4805 is a controller for power factor corrected, switched mode power supplies. Similar to the ML4801, the ML4805 may be used for voltage mode operation. Key features of this combined PFC and PWM controller are low start-up and operating currents. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-2-3 specifications. The ML4805 includes circuits for the implementation of a leading edge, average current “boost” type power factor correction and a trailing edge pulse width modulator.

The PFC frequency of the ML4805 is automatically set at half that of the PWM frequency generated by the internal oscillator. This technique allows the user to design with smaller output components while maintaining the optimum operating frequency for the PFC. An overvoltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brownout protection.

BLOCK DIAGRAM

17

2

4

3

8

7

9

6

5

11

V

FB

2.5V

I

AC

V

RMS

I

SENSE

RAMP 1

RTC

T

RAMP 2

V

DC

V

SS

AGND

CC

VEAO

VEA

-

+

8V

25µA

8V

18

GAIN

MODULATOR

1.25V

1.6kΩ

IEA

+

–

1.6kΩ

-

+

IEAO

-

+

1

POWER FACTOR CORRECTOR

+

-

OSCILLATOR

V

-

FB

2.5V

+

PULSE WIDTH MODULATOR

FEATURES

■ Internally synchronized PFC and PWM in one IC

■ Low start-up current (200µA typ.)

■ Low operating current (5.5mA typ.)

■ Low total harmonic distortion

■ Reduces ripple current in the storage capacitor

between the PFC and PWM sections

■ Average current continuous boost leading edge PFC

■ High efficiency trailing edge PWM optimized for

voltage mode operation

■ Current fed gain modulator for improved noise

immunity

■ Brown-out control, overvoltage protection, UVLO, and

soft start

15

V

7.5V

REFERENCE

÷2

DUTY CYCLE

VIN OK

LIMIT

2.75V

-1V

1.5V

OVP

+

PFC I

+

-

LIMIT

DC I

LIMIT

V

CC

V

CC

SRQ

Q

SRQ

Q

SRQ

Q

UVLO

CC

V

REF

PFC OUT

PGND

PWM OUT

I

LIM

16

14

12

13

10

REV. 1.1 3/9/2001

ML4805

PIN CONFIGURATION

ML4805

18-Pin PDIP (P18)

18-Pin SOIC (S18)

IEAO

1

18

VEAO

I

SENSE

V

RMS

V

RTC

RAMP 1

RAMP 2

PIN DESCRIPTION

PIN NAME FUNCTION

1 IEAO PFC transconductance current error

amplifier output

2I

AC

3I

SENSE

PFC gain control reference input

Current sense input to the PFC current limit comparator

I

AC

SS

DC

2

3

4

5

6

7

T

8

9

TOP VIEW

V

17

FB

V

16

REF

V

15

CC

PFC OUT

14

PWM OUT

13

PGND

12

AGND

11

I

10

LIM

PIN NAME FUNCTION

9 RAMP 2 PWM ramp sense input

10 ILIM PWM current limit sense input

11 AGND Analog ground

12 PGND Power ground

4V

RMS

Input for PFC RMS line voltage

13 PWM OUT PWM driver output

compensation

14 PFC OUT PFC driver output

5 SS Connection point for the PWM soft start

capacitor

15 V

CC

Positive supply (connected to an internal shunt regulator).

6V

7R

DC

TCT

PWM voltage feedback input

Connection for oscillator frequency

16 V

REF

Buffered output for the internal 7.5V reference

setting components

8 RAMP 1 PFC ramp input

17 V

FB

PFC transconductance voltage error amplifier input

18 VEAO PFC transconductance voltage error

amplifier output

2 REV. 1.1 3/9/2001

ABSOLUTE MAXIMUM RATINGS

ML4805

Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.

Junction Temperature ............................................. 150°C

Storage Temperature Range ...................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ..................... 260°C

Thermal Resistance (θ

)

JA

Plastic DIP ........................................................70°C/W

V

..............................................................................................

CC

Voltage .................................................. -3V to 5V

I

SENSE

Voltage on Any Other Pin ...... GND - 0.3V to V

I

...........................................................................................

REF

I

Input Current .....................................................10mA

AC

+ 0.3V

CC

18V

20mA

Peak PFC OUT Current, Source or Sink ................. 500mA

Peak PWM OUT Current, Source or Sink............... 500mA

PFC OUT, PWM OUT Energy Per Cycle ................... 1.5µJ

Plastic SOIC ...................................................100°C/W

OPERATING CONDITIONS

Temperature Range

ML4805CX ................................................. 0°C to 70°C

ML4805IX ............................................... -40°C to 85°C

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, VCC = 15V, RT = 29.4kΩ, R T

= Operating Temperature Range (Note 1)

A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOLTAGE ERROR AMPLIFIER

Input Voltage Range 0 5 V

Transconductance V

Feedback Reference Voltage 2.43 2.50 2.57 V

Input Bias Current Note 2 -0.5 -1.0 µA

Output High Voltage 6.0 6.7 V

Output Low Voltage 0.1 0.4 V

Source Current ∆VIN = ±0.5V, V

Sink Current ∆VIN = ±0.5V, V

Open Loop Gain 60 70 dB

PSRR 11V < VCC < 16.5V 60 70 dB

CURRENT ERROR AMPLIFIER

Input Voltage Range -1.5 2 V

Transconductance V

Input Offset Voltage 0 8 15 mV

Input Bias Current -0.5 -1.0 µA

Output High Voltage 6.0 6.7 V

Output Low Voltage 0.65 1.0 V

Source Current ∆VIN = ±0.5V, V

Sink Current ∆VIN = ±0.5V, V

Open Loop Gain 55 65 dB

PSRR 11V < VCC < 16.5V 60 75 dB

NON INV

= 15.4kΩ, CT = 270pF, C

RAMP1

= V

, VEAO = 3.75V 40 65 80 µ

INV

= 6V -40 -70 -150 µA

OUT

= 1.5V 40 70 150 µA

OUT

= V

, VEAO = 3.75V 60 100 120 µ

INV

= 6V -40 -70 -150 µA

OUT

= 1.5V 40 70 150 µA

OUT

RAMP1

= 620pF,

Ω

REV. 1.1 3/9/2001 3

ML4805

ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

OVP COMPARATOR

Threshold Voltage 2.65 2.75 2.85 V

Hysteresis 175 250 325 mV

PFC I

DC I

VIN OK COMPARATOR

GAIN MODULATOR

OSCILLATOR

COMPARATOR

LIMIT

Threshold Voltage -0.9 -1.0 -1.1 V

∆PFC I

Threshold - Gain Modulator Output 120 220 mV

LIMIT

Delay to Output 150 300 ns

COMPARATOR

LIMIT

Threshold Voltage 1.4 1.5 1.6 V

Input Bias Current ±0.3 ±1 µA

Delay to Output 150 300 ns

Threshold Voltage 2.4 2.5 2.6 V

Hysteresis 0.8 1.0 1.2 V

Gain (Note 3) IAC = 100µA, V

IAC = 50µA, V

IAC = 100µA, V

= VFB = 0V 0.65 0.85 1.05

RMS

= 1V, VFB = 0V 1.90 2.20 2.40

RMS

= 1.8V, VFB = 0V 0.90 1.05 1.25

RMS

= 3.3V, VFB = 0V 0.20 0.30 0.40

RMS

Bandwidth IAC = 100µA 10 MHz

Output Voltage I

= 350µA, V

AC

= 1V, 0.65 0.75 0.85 V

RMS

VFB = 0V

Initial Accuracy TA = 25ºC 188 200 212 kHz

Voltage Stability 11V < VCC < 16.5V 1 %

Temperature Stability 2%

Total Variation Line, Temp 182 218 kHz

Ramp Valley to Peak Voltage 2.5 V

PFC Dead Time 350 470 600 ns

CT Discharge Current V

RAMP 2

= 0V, V

= 2.5V 3.5 5.5 7.5 mA

RAMP 1

4 REV. 1.1 3/9/2001

ML4805

ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

REFERENCE

Output Voltage TA = 25ºC, I(V

Line Regulation 11V < VCC < 16.5V 10 25 mV

Load Regulation 1mA < I(V

Temperature Stability 0.4 %

Total Variation Line, Load, Temp 7.35 7.65 V

Long Term Stability TJ = 125ºC, 1000 Hours 5 25 mV

PFC

Minimum Duty Cycle V

Maximum Duty Cycle V

Output Low Voltage I

Output High Voltage I

> 6.7V 0 %

IEAO

< 1.2V 90 95 %

IEAO

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.7 2.0 V

OUT

I

= -10mA, VCC = 9V 0.4 0.8 V

OUT

= 20mA VCC - 0.8 V

OUT

I

= 100mA VCC - 2.0 V

OUT

Rise/Fall Time CL = 1000pF 50 ns

PWM

DC Duty Cycle Range 0-44 0-47 0-50 %

V

Output Low Voltage I

OL

Output High Voltage I

OH

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.7 2.0 V

OUT

I

= -10mA, VCC = 9V 0.4 0.8 V

OUT

= 20mA VCC - 0. 8 V

OUT

I

= 100mA VCC - 2.0 V

OUT

Rise/Fall Time CL = 1000pF 50 ns

SUPPLY

) = 1mA 7.4 7.5 7.6 V

REF

) < 10mA 10 20 mV

REF

Start-up Current VCC = 12V, CL = 0 200 350 µA

Operating Current VCC = 14V, CL = 0 5.5 7.0 mA

Undervoltage Lockout Threshold 12.4 13.0 13.6 V

Undervoltage Lockout Hysteresis 2.7 3.0 3.3 V

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

Note 2: Includes all bias currents to other circuits connected to the V

- I

Note 3: Gain = K x 5.3V; K = (I

MULO

) x IAC x (VEAO - 0.625V)-1.

OFFSET

pin.

FB

REV. 1.1 3/9/2001 5

ML4805

FUNCTIONAL DESCRIPTION

The ML4805 consists of a combined average-currentcontrolled, continuous boost Power Factor Corrector (PFC) front end and a synchronized Pulse Width Modulator (PWM) back end. It is distinguished from earlier combo controllers by its dramatically reduced start-up and operating currents. The PWM section can be used in either current or voltage mode. In voltage mode, feedforward from the PFC output buss can be used to improve the PWM’s line regulation. In either mode, the PWM stage uses conventional trailing-edge duty cycle modulation, while the PFC uses leading-edge modulation. This patented leading/trailing edge modulation technique results in a higher useable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC buss capacitor.

The synchronization of the PWM with the PFC simplifies the PWM compensation due to the reduced ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the ML4805 runs at twice the frequency of the PFC, which allows the use of smaller PWM output magnetics and filter capacitors while holding down the losses in the PFC stage power components.

In addition to power factor correction, a number of protection features have been built into the ML4805. These include soft-start, PFC over-voltage protection, peak current limiting, brown-out protection, duty cycle limit, and under-voltage lockout.

POWER FACTOR CORRECTION

Power factor correction makes a non-linear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with, and proportional to, the line voltage, so the power factor is unity (one). A common class of non-linear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peakcharging effect which occurs on the input filter capacitor in such a supply causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such a supply presents a power factor to the line of less than one (another way to state this is that it causes significant current harmonics to appear at its input). If the input current drawn by such a supply (or any other non-linear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved.

To maintain the input current of a device drawing power from the AC line in phase with, and proportional to, the input voltage, a way must be found to cause that device to load the line in proportion to the instantaneous line voltage. The PFC section of the ML4805 uses a boostmode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage.

No filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges, at twice line frequency, from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current which the converter draws from the power line matches the instantaneous line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VAC

. The other condition is that the

rms

current which the converter is allowed to draw from the line at any given instant must be proportional to the line voltage. The first of these requirements is satisfied by establishing a suitable voltage control loop for the converter, which sets an average operating current level for a current error amplifier and switching output driver. The second requirement is met by using the rectified AC line voltage to modulate the input of the current control loop. Such modulation causes the current error amplifier to command a power stage current which varies directly with the input voltage. In order to prevent ripple which will necessarily appear at the output of the boost circuit (typically about 10VAC on a 385V DC level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/V

2

,

IN

which linearizes the transfer function of the system as the AC input voltage varies.

Since the boost converter topology in the ML4805 PFC is of the current-averaging type, no slope compensation is required.

PFC SECTION

Gain Modulator

Figure 1 shows a block diagram of the PFC section of the ML4805. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltage. There are three inputs to the gain modulator. These are:

1) A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via an external resistor and is then fed into the gain modulator at I

. Sampling current in this way

AC

minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current.

2) A voltage proportional to the long-term rms AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at V

. The gain modulator’s output is

RMS

6 REV. 1.1 3/9/2001

FUNCTIONAL DESCRIPTION (Continued)

ML4805

17

2

4

3

8

7

V

FB

2.5V

I

AC

V

RMS

I

SENSE

RAMP 1

RTC

T

VEAO

VEA

-

+

MODULATOR

18

GAIN

1.6kΩ

IEA

+

–

1.6kΩ

IEAO

8V

1

POWER FACTOR CORRECTOR

PFC

CONTROLLER

OSCILLATOR

÷2

DUTY CYCLE

LIMIT

Figure 1. PFC Section Block Diagram

2

inversely proportional to V low values of V

where special gain contouring

RMS

(except at unusually

RMS

takes over to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between V

and gain is designated as K.

RMS

3) The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage.

The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general form for the output of the gain modulator is:

´

IVEAO

AC

I

GAINMOD

More exactly, the output current of the gain modulator is

given by:

=

V

RMS

´

V

1

2

15

V

7.5V

REFERENCE

PFC

CC

PFC OUT

V

REF

16

14

2.75V

-1V

+

PFC I

+

OVP

-

LIMIT

-

OUTPUT

DRIVER

Current Error Amplifier

The current error amplifier’s output controls the PFC duty cycle to keep the current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the I pin (current into I voltage on I

SENSE

≅ V

/1.6kΩ). The negative

SENSE

represents the sum of all currents

SENSE

flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. In higher power applications, two current transformers are sometimes used, one to monitor the I

of the boost diode. As stated above, the inverting

the I

F

of the boost MOSFET(s) and one to monitor

D

input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on I

is adequately negative to cancel this increased

SENSE

current. Similarly, if the gain modulator’s output decreases, the output duty cycle will decrease to achieve a less negative voltage on the I

SENSE

pin.

I K VEAO V I

GAINMOD AC

where K is in units of V

=× − ×(.)0625

-1

.

(1)

Cycle-By-Cycle Current Limiter

The I

pin, as well as being a part of the current

SENSE

feedback loop, is a direct input to the cycle-by-cycle

Note that the output current of the gain modulator is limited to ≅ 500µA.

current limiter for the PFC section. Should the input voltage at this pin ever be more negative than -1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle.

REV. 1.1 3/9/2001 7

ML4805

FUNCTIONAL DESCRIPTION (Continued)

Overvoltage Protection

The OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to V voltage on V

exceeds 2.75V, the PFC output driver is

FB

. When the

FB

shut down. The PWM section will continue to operate. The OVP comparator has 250mV of hysteresis, and the PFC will not restart until the voltage at V

drops below 2.5V.

FB

The OVP trip level should be set at a level where the active and passive external power components and the ML4805 are within their safe operating voltages, but not so low as to interfere with the regular operation of the boost voltage regulation loop.

Error Amplifier Compensation

The PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to V

to produce a soft-start characteristic on

REF

the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter.

There are two major concerns when compensating the voltage loop error amplifier; stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier’s open-loop crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). Rapid perturbations in line or load conditions will cause the input to the voltage error amplifier (V

) to deviate from

FB

its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will increase significantly. This increases the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. The current amplifier compensation is similar to that of the voltage error amplifier with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g.

16.7kHz for a 100kHz switching frequency.

There is also a degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. However, the boost inductor will usually be

the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier.

For more information on compensating the current and voltage control loops, see Application Notes 33, 34, and

55. Application Note 16 also contains valuable information for the design of this class of PFC.

Oscillator (R

TCT

)

The oscillator frequency is determined by the values of R and CT, which determine the ramp and off-time of the ML4805's master oscillator:

=

f

OSC

tt

RAMP DEADTIME

The deadtime of the oscillator is derived from the

following equation:

tCR

=´´

RAM P T T

at V

= 7.5V:

at V

= 7.5V:

REF

=´´051.

tCR

RAMP T T

The ramp of the oscillator may be determined using:

t

DEADTIME T T

The deadtime is so small (t

PFC

OUTPUT

V

FB

17

2.5V

I

AC

2

V

RMS

4

I

SENSE

3

1

+

F

V

REF

ln

G

V

H

REF

V

25

.

=´=´

55

.

CC

mA

RAMP

GND

18

VEAO

VEA

-

+

GAIN

MODULATOR

-

455

>> t

..125

375

I J

K

DEADTIME

IEAO

IEA

+

-

) that the

V

REF

1

+

-

(2)

(3)

(4)

Figure 2. Compensation Network Connections for the

Voltage and Current Error Amplifiers

T

8 REV. 1.1 3/9/2001

FUNCTIONAL DESCRIPTION (Continued)

ML4805

operating frequency can typically be approximated by:

1

=

f

OSC

t

RAMP

EXAMPLE:

For the application circuit shown in the data sheet, with

the oscillator running at:

==100

fkHz

OSC

=´´=´

tRC

RAMP T T

Solving for RT x CT yields 2 x 10-4. Selecting standard

components values, C

PWM SECTION

Pulse Width Modulator

The PWM section of the ML4805 is straightforward, but

there are several points which should be noted. Foremost

among these is its inherent synchronization to the PFC

section of the device. The PWM is capable of current-

mode or voltage mode operation. In current-mode

applications, the PWM ramp (RAMP 2) is usually derived

directly from a current sensing resistor or current

transformer in the primary of the output stage, and is

thereby representative of the current flowing in the

converter’s output stage. DC I

cycle-by-cycle current limiting, is typically connected to

RAMP 2 in such applications. For voltage-mode operation

or certain specialized applications, RAMP 2 can be

connected to a separate RC timing network to generate a

voltage ramp against which V

these conditions, the use of voltage feedforward from the

PFC buss can assist in line regulation accuracy and

response. As in current mode operation, the DC I

input is used for output stage overcurrent protection.

051 1 10

.

1

t

RAMP

-

5

= 270pF, and RT = 36.5kΩ.

T

, which provides

LIMIT

DC will be compared. Under

DC

will be compared. Under

LIMIT

(5)

V

OK Comparator

V

IN

The V

PFC and inhibits the PWM if this voltage on V

than its nominal 2.5V. Once this voltage reaches 2.5V,

which corresponds to the PFC output capacitor being

charged to its rated boost voltage, the soft-start

commences.

PWM Control (RAMP 2)

When the PWM section is used in current mode, RAMP 2

is generally used as the sampling point for a voltage

representing the current in the primary of the PWM’s

output transformer, derived either by a current sensing

resistor or a current transformer. In voltage mode, it is the

input for a ramp voltage generated by a second set of

timing components (R

minimum value of zero volts and should have a peak

value of approximately 5V. In voltage mode operation,

feedforward from the PFC output buss is an excellent way

to derive the timing ramp for the PWM stage.

Soft Start

Start-up of the PWM is controlled by the selection of the

external capacitor at SS. A current source of 25µA

supplies the charging current for the capacitor, and start-

up of the PWM begins at 1.25V. Start-up delay can be

programmed by the following equation:

where C

t

DELAY

It is important that the time constant of the PWM soft-start

allow the PFC time to generate sufficient output power for

the PWM section. The PWM start-up delay should be at

least 5ms.

OK comparator monitors the DC output of the

IN

, C

RAMP2

A

µ

=×

Ct

SS DELAY

is the required soft start capacitance, and

SS

is the desired start-up delay.

25

.

125

V

), which will have a

RAMP2

(6)

FB

is less

No voltage error amplifier is included in the PWM stage

of the ML4805, as this function is generally performed on

the output side of the PWM’s isolation boundary. To

facilitate the design of optocoupler feedback circuitry, an

offset has been built into the PWM’s RAMP 2 input which

allows V

input voltages below 1.25V.

PWM Current Limit

The DC I

current limiter for the PWM section. Should the input

voltage at this pin ever exceed 1.5V, the output of the

PWM will be disabled until the output flip-flop is reset by

the clock pulse at the start of the next PWM power cycle.

REV. 1.1 3/9/2001 9

to command a zero percent duty cycle for

DC

pin is a direct input to the cycle-by-cycle

LIMIT

Solving for the minimum value of C

25

µ

=× =5

Cms

SS

In the ML4805, the operating frequency of the PFC

section is fixed at 1/2 of the PWM's operating frequency.

This is done through the use of a 2:1 digital frequency

divider ("T" flip-flop) linking the two functional sections of

the IC.

125

.

A

100

V

nF

:

SS

ML4805

FUNCTIONAL DESCRIPTION (Continued)

Generating V

The ML4805 is a voltage-fed part. It requires an external 15V±10% or better Zener shunt voltage regulator, or some other controlled supply, to regulate the voltage supplied to the part at 15V nominal. This allows a low power dissipation while at the same time delivering 13V nominal of gate drive at the PWM OUT and PFC OUT outputs. If using a Zener diode, it is important to limit the current through the Zener to avoid overheating or destroying it. This can be easily done with a single resistor in series with the Vcc pin, returned to a bias supply of typically 18V to 20V. The resistor’s value must be chosen to meet the operating current requirement of the ML4805 itself (8.5mA max.) plus the current required by the two gate driver outputs.

EXAMPLE: With a V driving a total gate charge of 110nC at 100kHz (1 IRF840 MOSFET and 2 IRF830 MOSFETs), the gate driver current required is:

IkHznCmA

GATEDRIVE

R

BIAS

The ML4805 should be locally bypassed with a 10nF and a 1µF ceramic capacitor. In most applications, an electrolytic capacitor of between 100µF and 330µF is also required across the part, both for filtering and as part of the start-up bootstrap circuitry.

CC

of 20V, a VCC limit of 16.5V (max) and

BIAS

=´=100 110 11

-

VV

20 165

=

75 11

.

+

mA mA

=

180

Ω

LEADING/TRAILING MODULATION

Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 3 shows a typical trailing edge control scheme.

In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 4 shows a leading edge control scheme.

One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary “no-load” period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using this method.

SW2

SW1

I2 I3

VEAO

+

–

C1

CMP

U1

I4

RL

RAMP

VEAO

DFF

R

Q

D

U2

Q

CLK

VSW1

TIME

+

DC

VIN

REF

OSC

U4

L1

I1

U3

+

EA

–

RAMP

CLK

SW2

SW1

+

–

I2 I3

U1

C1

L1

I4

RL

RAMP

VEAO

DFF

R

Q

U2

D

Q

CLK

VSW1

TIME

+

DC

VIN

REF

OSC

U4

I1

U3

+

EA

–

RAMP

CLK

Figure 4. Leading/Trailing Edge Control SchemeFigure 3. Typical Trailing Edge Control Scheme

10 REV. 1.1 3/9/2001

ML4805

160

(µA)

0

VEAO

I

–160

024

13

VFB (V)

Figure 5. I

VEAO

vs. V

FB

180

Ω

90

µ

0

5

024

13

VFB (V)

Figure 6. gM of V

OTA

5

200

160

120

Ω

µ

80

40

0

024

13

V

(V)

FB

Figure 7. gM of I

OTA

500

K

0

5

024

13

VFB (V)

5

Figure 8. K of Multiplier

REV. 1.1 3/9/2001 11

ML4805

PHYSICAL DIMENSIONS inches (millimeters)

Package: P18

18-Pin PDIP

0.890 - 0.910

(22.60 - 23.12)

18

0.045 MIN (1.14 MIN) (4 PLACES)

0.170 MAX

(4.32 MAX)

0.125 MIN (3.18 MIN)

18

PIN 1 ID

1

0.449 - 0.463

(11.40 - 11.76)

0.050 - 0.065 (1.27 - 1.65)

0.016 - 0.022 (0.40 - 0.56)

0.100 BSC (2.54 BSC)

SEATING PLANE

Package: S18

18-Pin SOIC

0.240 - 0.260 (6.09 - 6.61)

0.015 MIN (0.38 MIN)

0.295 - 0.325 (7.49 - 8.26)

0º - 15º

0.008 - 0.012 (0.20 - 0.31)

0.024 - 0.034 (0.61 - 0.86)

(4 PLACES)

0.090 - 0.094 (2.28 - 2.39)

0.291 - 0.301 (7.39 - 7.65)

PIN 1 ID

1

0.050 BSC (1.27 BSC)

0.012 - 0.020 (0.30 - 0.51)

0.095 - 0.107 (2.41 - 2.72)

SEATING PLANE

0.398 - 0.412

(10.11 - 10.47)

0.005 - 0.013 (0.13 - 0.33)

0º - 8º

0.022 - 0.042 (0.56 - 1.07)

0.009 - 0.013 (0.22 - 0.33)

12 REV. 1.1 3/9/2001

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE

ML4805CP 0°C to 70°C 18-Pin Plastic DIP (P18) ML4805CS 0°C to 70°C 18-Pin Wide SOIC (S18)

ML4805IP -40°C to 85°C 18-Pin Plastic DIP (P18) ML4805IS -40°C to 85°C 18-Pin Wide SOIC (S18)

ML4805

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

REV. 1.1 3/9/2001 13

2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Datasheet ML4805IS, ML4805CS, ML4805IP Datasheet (Fairchild Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual