Datasheet ML4805CP Datasheet (Micro Linear Corporation)

November 1998

PRELIMINARY

ML4805

Variable Feedforward PFC/PWM Controller Combo

GENERAL DESCRIPTION

The ML4805 is a controller for power factor corrected,
switched mode power supplies. Similar to the ML4801,
the ML4805 may be used for voltage mode operation. Key
features of this combined PFC and PWM controller are
low start-up and operating currents. P ower Factor
Correction (PFC) allows the use of smaller, lower cost
bulk capacitors, reduces power line loading and stress on
the switching FETs, and results in a power supply that
fully complies with IEC1000-2-3 specifications. The
ML4805 includes circuits for the implementation of a
leading edge, average current “boost” type power factor
correction and a trailing edge pulse width modulator.

The PFC frequency of the ML4805 is automatically set at
half that of the PWM frequency generated by the internal
oscillator. This technique allows the user to design with
smaller output components while maintaining the
optimum operating frequency for the PFC. An over­voltage comparator shuts down the PFC section in the
event of a sudden decrease in load. The PFC section also
includes peak current limiting and input voltage brown­out protection.

BLOCK DIAGRAM

17

2

4

3

8

7

9

6

5

11

V

FB

2.5V

I

AC

V

RMS

I

SENSE

RAMP 1

RTC

T

RAMP 2

V

DC

V

SS

AGND

CC

VEAO

VEA

­+

8V

25µA

8V

18

GAIN

MODULATOR

1.25V

1.6kΩ

IEA

+
–

1.6kΩ

­+

IEAO

­+

1

POWER FACTOR CORRECTOR

+

-

OSCILLATOR

V

-

FB

2.5V

+

PULSE WIDTH MODULATOR

FEATURES

■ Internally synchronized PFC and PWM in one IC

■ Low start-up current (200µA typ.)

■ Low operating current (5.5mA typ.)

■ Low total harmonic distortion

■ Reduces ripple current in the storage capacitor

between the PFC and PWM sections

■ Average current continuous boost leading edge PFC

■ High efficiency trailing edge PWM optimized for

voltage mode operation

■ Current fed gain modulator for improved noise

immunity

■ Brown-out control, overvoltage protection, UVLO, and

soft start

15

V

7.5V

REFERENCE

÷2

DUTY CYCLE

VIN OK

LIMIT

2.75V

-1V

1.5V

OVP

+

+

PFC I

+

-

-

-

LIMIT

DC I

LIMIT

V

CC

V

CC

SRQ

Q

SRQ

Q

SRQ

Q

UVLO

CC

V

REF

PFC OUT

PGND

PWM OUT

I

LIM

16

14

12

13

10

1

ML4805

PIN CONFIGURATION

ML4805

18-Pin PDIP (P18)

18-Pin SOIC (S18)

IEAO

1

18

VEAO

I

SENSE

V

RMS

V

RTC

RAMP 1

RAMP 2

PIN DESCRIPTION

PIN NAME FUNCTION

1 IEAO PFC transconductance current error

amplifier output

2I

AC

3I

SENSE

PFC gain control reference input
Current sense input to the PFC current

limit comparator

I

AC

SS

DC

2

3

4

5

6

7

T

8

9

TOP VIEW

17

V

FB

16

V

REF

15

V

CC

14

PFC OUT

13

PWM OUT

12

PGND

11

AGND

10

I

LIM

PIN NAME FUNCTION

9 RAMP 2 PWM ramp sense input

10 ILIM PWM current limit sense input
11 A G ND Analog ground
12 PGND Power ground

4V

RMS

Input for PFC RMS line voltage
compensation

5 SS Connection point for the PWM soft start

capacitor
6V
7RTC

DC

T

PWM voltage feedback input

Connection for oscillator frequency

setting components
8 RAMP 1 PFC ramp input

2

13 PWM OUT PWM driver output
1 4 PFC OUT PFC driver output
15 V

CC

Positive supply (connected to an
internal shunt regulator).

16 V

REF

Buffered output for the internal 7.5V
reference

17 V

FB

PFC transconductance voltage error
amplifier input

18 VEAO PFC transconductance voltage error

amplifier output

ABSOLUTE MAXIMUM RATINGS

ML4805

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.

Junction T emperature..............................................150°C

Storage Temperature Range ..................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) .....................260°C

Thermal Resistance (θJA)

Plastic DIP ....................................................... 70°C/W

V

............................................................................................... 18V

CC

I

Voltage.................................................. -3V to 5V

SENSE

Plastic SOIC .................................................. 100°C/W

Voltage on Any Other Pin ...... GND - 0.3V to VCC + 0.3V

I

............................................................................................20mA

REF

OPERATING CONDITIONS

IAC Input Current ....................................................10mA

Peak PFC OUT Current, Source or Sink ................ 500mA

Peak PWM OUT Current, Source or Sink.............. 500mA

PFC OUT, PWM OUT Energy Per Cycle .................. 1.5µJ

Temperature Range

ML4805CX.................................................0°C to 70°C

ML4805IX ...............................................-40°C to 85°C

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, VCC = 15V, RT = 29.4kΩ, R
TA = Operating Temperature Range (Note 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOLTAGE ERROR AMPLIFIER

Input Voltage Range 0 5 V
Transconductance V
Feedback Reference Voltage 2.43 2.50 2.57 V
Input Bias Current Note 2 -0.5 -1.0 µA

NON INV

= 15.4kΩ, CT = 270pF, C

RAMP1

= V

, VEAO = 3.75V 40 65 80 µ

INV

RAMP1

= 620pF,

Ω

Output High Voltage 6.0 6.7 V
Output Low Voltage 0.1 0.4 V
Source Current ∆VIN = ±0.5V, V
Sink Current ∆VIN = ±0.5V, V
Open Loop Gain 60 7 0 dB
PSRR 11V < VCC < 16.5V 60 70 dB

CURRENT ERROR AMPLIFIER

Input Voltage Range -1.5 2 V
Transconductance V
Input Offset Voltage 0 8 15 m V
Input Bias Current -0.5 -1.0 µA
Output High Voltage 6.0 6.7 V
Output Low Voltage 0.65 1.0 V
Source Current ∆VIN = ±0.5V, V
Sink Current ∆VIN = ±0.5V, V
Open Loop Gain 55 6 5 dB
PSRR 11V < VCC < 16.5V 60 75 dB

NON INV

= 6V -40 -70 -150 µA

OUT

= 1.5V 40 70 150 µA

OUT

= V

, VEAO = 3.75V 60 100 120 µ

INV

= 6V -40 -70 -150 µA

OUT

= 1.5V 40 70 150 µA

OUT

Ω

3

ML4805

ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

OVP COMPARATOR

Threshold Voltage 2.65 2.75 2.85 V
Hysteresis 175 250 325 mV

PFC I

COMPARATOR

LIMIT

Threshold Voltage -0.9 -1.0 -1.1 V

∆PFC I

LIMIT

Delay to Output 150 300 ns

DC I

COMPARATOR

LIMIT

Threshold Voltage 1.4 1.5 1.6 V
Input Bias Current ±0.3 ±1 µA
Delay to Output 150 300 ns

VIN OK COMPARATOR

Threshold Voltage 2.4 2.5 2.6 V
Hysteresis 0.8 1.0 1.2 V

GAIN MODULATOR

Gain (Note 3) IAC = 100µA, V

Bandwidth IAC = 100µA 10 MHz
Output Voltage IAC = 350µA, V

OSCILLATOR

Initial Accuracy TA = 25ºC 188 200 212 kHz

Threshold - Gain Modulator Output 120 220 mV

= VFB = 0V 0.65 0.85 1.05

RMS

IAC = 50µA, V
IAC = 50µA, V
IAC = 100µA, V

= 1V, VFB = 0V 1.90 2.20 2.40

RMS

= 1.8V, VFB = 0V 0.90 1.05 1.25

RMS

= 3.3V, VFB = 0V 0.20 0.30 0.40

RMS

= 1V, 0.65 0.75 0.85 V

RMS

VFB = 0V

Voltage Stability 11V < VCC < 16.5V 1 %
Temperature Stability 2%
Total Variation Line, Temp 182 218 k Hz
Ramp Valley to Peak Voltage 2.5 V
PFC Dead Time 350 470 600 ns
CT Discharge Current V

RAMP 2

= 0V, V

= 2.5V 3.5 5.5 7.5 mA

RAMP 1

4

ML4805

ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

REFERENCE

Output Voltage TA = 25ºC, I(V

) = 1mA 7.4 7.5 7.6 V

REF

Line Regulation 11V < VCC < 16.5V 10 25 mV
Load Regulation 1mA < I(V

) < 10mA 10 20 mV

REF

Temperature Stability 0.4 %
Total Variation Line, Load, Temp 7.35 7.65 V
Long Term Stability TJ = 125ºC, 1000 Hours 5 25 mV

PFC

Minimum Duty Cycle V
Maximum Duty Cycle V
Output Low Voltage I

Output High Voltage I

> 6.7V 0 %

IEAO

< 1.2V 90 95 %

IEAO

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.7 2.0 V

OUT

I

= -10mA, VCC = 9V 0.4 0.8 V

OUT

= 20mA VCC - 0.8 V

OUT

I

= 100mA VCC - 2.0 V

OUT

Rise/Fall Time CL = 1000pF 50 ns

PWM

DC Duty Cycle Range 0-44 0-47 0-50 %

V

V

Output Low Voltage I

OL

Output High Voltage I

OH

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.7 2.0 V

OUT

I

= -10mA, VCC = 9V 0.4 0.8 V

OUT

= 20mA VCC - 0. 8 V

OUT

I

= 100mA VCC - 2.0 V

OUT

Rise/Fall Time CL = 1000pF 50 ns

SUPPLY

Start-up Current VCC = 12V, CL = 0 200 350 µA
Operating Current VCC = 14V, CL = 0 5.5 7.0 mA
Undervoltage Lockout Threshold 12.4 13.0 13.6 V
Undervoltage Lockout Hysteresis 2.7 3.0 3.3 V

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Includes all bias currents to other circuits connected to the V
Note 3: Gain = K x 5.3V; K = (I

MULO

- I

) x IAC x (VEAO - 0.625V)-1.

OFFSET

FB

pin.

5

ML4805

FUNCTIONAL DESCRIPTION

The ML4805 consists of a combined a verage-current­controlled, continuous boost Power F actor Corrector (PFC)
front end and a synchronized Pulse Width Modulator
(PWM) back end. It is distinguished from earlier combo
controllers by its dramatically reduced start-up and
operating currents. The PWM section can be used in either
current or voltage mode. In voltage mode, feedforward
from the PFC output buss can be used to improve the
PWM’s line regulation. In either mode, the PWM stage
uses conventional trailing-edge duty cycle modulation,
while the PFC uses leading-edge modulation. This
patented leading/trailing edge modulation technique
results in a higher useable PFC error amplifier bandwidth,
and can significantly reduce the size of the PFC DC buss
capacitor.

The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the reduced ripple on the
PFC output capacitor (the PWM input capacitor). The
PWM section of the ML4805 runs at twice the frequency
of the PFC, which allows the use of smaller PWM output
magnetics and filter capacitors while holding down the
losses in the PFC stage power components.

In addition to power factor correction, a number of
protection features have been built into the ML4805.
These include soft-start, PFC over-voltage protection, peak
current limiting, brown-out protection, duty cycle limit,
and under-voltage lockout.

POWER FACTOR CORRECTION

Power factor correction makes a non-linear load look like
a resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with, and proportional to,
the line voltage, so the power factor is unity (one). A
common class of non-linear load is the input of most
power supplies, which use a bridge rectifier and
capacitive input filter fed from the line. The peak­charging effect which occurs on the input filter capacitor
in such a supply causes brief high-amplitude pulses of
current to flow from the power line, rather than a
sinusoidal current in phase with the line voltage. Such a
supply presents a power factor to the line of less than one
(another way to state this is that it causes significant
current harmonics to appear at its input). If the input
current drawn by such a supply (or any other non-linear
load) can be made to follow the input voltage in
instantaneous amplitude, it will appear resistive to the AC
line and a unity power factor will be achieved.

To maintain the input current of a device drawing power
from the AC line in phase with, and proportional to, the
input voltage, a way must be found to cause that device
to load the line in proportion to the instantaneous line
voltage. The PFC section of the ML4805 uses a boost­mode DC-DC converter to accomplish this. The input to
the converter is the full wave rectified AC line voltage.

No filtering is applied following the bridge rectifier, so the
input voltage to the boost converter ranges, at twice line
frequency, from zero volts to the peak value of the AC
input and back to zero. By forcing the boost converter to
meet two simultaneous conditions, it is possible to ensure
that the current which the converter draws from the power
line matches the instantaneous line voltage. One of these
conditions is that the output voltage of the boost converter
must be set higher than the peak value of the line
voltage. A commonly used value is 385VDC, to allow for
a high line of 270VAC
current which the converter is allowed to draw from the
line at any given instant must be proportional to the line
voltage. The first of these requirements is satisfied by
establishing a suitable voltage control loop for the
converter, which sets an average operating current level
for a current error amplifier and switching output driver.
The second requirement is met by using the rectified AC
line voltage to modulate the input of the current control
loop. Such modulation causes the current error amplifier
to command a power stage current which varies directly
with the input voltage. In order to prevent ripple which
will necessarily appear at the output of the boost circuit
(typically about 10VAC on a 385V DC level), from
introducing distortion back through the voltage error
amplifier, the bandwidth of the voltage loop is
deliberately kept low. A final refinement is to adjust the
overall gain of the PFC such to be proportional to 1/V
which linearizes the transfer function of the system as the
AC input voltage varies.

Since the boost converter topology in the ML4805 PFC is
of the current-averaging type, no slope compensation is
required.

PFC SECTION

Gain Modulator

Figure 1 shows a block diagram of the PFC section of the
ML4805. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the
current loop to line voltage waveform and frequency, rms
line voltage, and PFC output voltage. There are three
inputs to the gain modulator. These are:

1) A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectified
AC input sine wave is converted to a proportional
current via an external resistor and is then fed into the
gain modulator at IAC. Sampling current in this way
minimizes ground noise, as is required in high power
switching power conversion environments. The gain
modulator responds linearly to this current.

2) A voltage proportional to the long-term rms AC line
voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the
gain modulator at V

. The other condition is that the

rms

. The gain modulator’s output is

RMS

2

,

IN

6

FUNCTIONAL DESCRIPTION (Continued)

ML4805

17

2

4

3

8

7

V

FB

2.5V

I

AC

V

RMS

I

SENSE

RAMP 1

RTC

T

VEAO

VEA

­+

MODULATOR

18

GAIN

1.6kΩ

IEA

+
–

1.6kΩ

IEAO

8V

1

POWER FACTOR CORRECTOR

PFC

CONTROLLER

OSCILLATOR

÷2

DUTY CYCLE

LIMIT

Figure 1. PFC Section Block Diagram

inversely proportional to V
low values of V

where special gain contouring

RMS

2

(except at unusually

RMS

takes over to limit power dissipation of the circuit
components under heavy brownout conditions). The
relationship between V

and gain is designated as K.

RMS

3) The output of the voltage error amplifier, VEAO. The
gain modulator responds linearly to variations in this
voltage.

The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way
the gain modulator forms the reference for the current
error loop, and ultimately controls the instantaneous
current draw of the PFC from the power line. The general
form for the output of the gain modulator is:

I

GAINMOD

=

V

RMS

´

V

1

2

´

IVEAO

AC

More exactly, the output current of the gain modulator is
given by:

15

V

7.5V

REFERENCE

PFC

CC

PFC OUT

V

REF

16

14

2.75V

-1V

OVP

+

-

PFC I

+

-

LIMIT

OUTPUT

DRIVER

Current Error Amplifier

The current error amplifier’s output controls the PFC duty
cycle to keep the current through the boost inductor a
linear function of the line voltage. At the inverting input
to the current error amplifier, the output current of the
gain modulator is summed with a current which results
from a negative voltage being impressed upon the I
pin (current into I
voltage on I

SENSE

SENSE

≅ V

/1.6kΩ). The negative

SENSE

represents the sum of all currents

SENSE

flowing in the PFC circuit, and is typically derived from a
current sense resistor in series with the negative terminal
of the input bridge rectifier. In higher power applications,
two current transformers are sometimes used, one to
monitor the ID of the boost MOSFET(s) and one to monitor
the IF of the boost diode. As stated above, the inverting
input of the current error amplifier is a virtual ground.
Given this fact, and the arrangement of the duty cycle
modulator polarities internal to the PFC, an increase in
positive current from the gain modulator will cause the
output stage to increase its duty cycle until the voltage on
I

is adequately negative to cancel this increased

SENSE

current. Similarly, if the gain modulator’s output
decreases, the output duty cycle will decrease to achieve
a less negative voltage on the I

SENSE

pin.

I K VEAO V I

GAINMOD AC

=× − ×(.)0625

where K is in units of V-1.
Note that the output current of the gain modulator is

limited to ≅ 500µA.

(1)

Cycle-By-Cycle Current Limiter

The I

pin, as well as being a part of the current

SENSE

feedback loop, is a direct input to the cycle-by-cycle
current limiter for the PFC section. Should the input
voltage at this pin ever be more negative than -1V, the
output of the PFC will be disabled until the protection
flip-flop is reset by the clock pulse at the start of the next
PFC power cycle.

7

ML4805

FUNCTIONAL DESCRIPTION (Continued)

Overvoltage Protection

The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load
should suddenly change. A resistor divider from the high
voltage DC output of the PFC is fed to VFB. When the
voltage on VFB exceeds 2.75V, the PFC output driver is
shut down. The PWM section will continue to operate. The
OVP comparator has 250mV of hysteresis, and the PFC
will not restart until the voltage at VFB drops below 2.5V.
The OVP trip level should be set at a level where the
active and passive external power components and the
ML4805 are within their safe operating voltages, but not
so low as to interfere with the regular operation of the
boost voltage regulation loop.

Error Amplifier Compensation

The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the
types of compensation networks most commonly used for
the voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to V

to produce a soft-start characteristic on

REF

the PFC: as the reference voltage comes up from zero
volts, it creates a differentiated voltage on IEAO which
prevents the PFC from immediately demanding a full duty
cycle on its boost converter.

There are two major concerns when compensating the
voltage loop error amplifier; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest
anticipated international power frequency). Rapid
perturbations in line or load conditions will cause the
input to the voltage error amplifier (VFB) to deviate from
its 2.5V (nominal) value. If this happens, the
transconductance of the voltage error amplifier will
increase significantly. This increases the gain-bandwidth
product of the voltage loop, resulting in a much more
rapid voltage loop response to such perturbations than
would occur with a conventional linear gain
characteristic. The current amplifier compensation is
similar to that of the voltage error amplifier with the
exception of the choice of crossover frequency. The
crossover frequency of the current amplifier should be at
least 10 times that of the voltage amplifier, to prevent
interaction with the voltage loop. It should also be limited
to less than 1/6th that of the switching frequency, e.g.

16.7kHz for a 100kHz switching frequency.

There is also a degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be

the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier.

For more information on compensating the current and
voltage control loops, see Application Notes 33, 34, and

55. Application Note 16 also contains valuable
information for the design of this class of PFC.

Oscillator (RTCT)

The oscillator frequency is determined by the values of R
and CT, which determine the ramp and off-time of the
ML4805's master oscillator:

=

f

OSC

tt

RAMP DEADTIME

1

+

(2)

The deadtime of the oscillator is derived from the
following equation:

tCR

=´´

RAM P T T

at V

= 7.5V:

REF

=´´051.

tCR

RAMP T T

F

V

ln

G

V

H

REF

REF

-

..125

-

375

I
J

K

(3)

The ramp of the oscillator may be determined using:

V

25

.

t

DEADTIME T T

The deadtime is so small (t

PFC

OUTPUT

=´=´

55

.

V

FB

17

2

4

3

2.5V

I

AC

V

I

SENSE

+

RMS

CC

mA

RAMP

GND

18

VEAO

VEA

-

GAIN

MODULATOR

455

>> t

DEADTIME

V

IEAO

IEA

+

-

(4)

) that the

REF

1

+

-

Figure 2. Compensation Network Connections for the

Voltage and Current Error Amplifiers

T

8

FUNCTIONAL DESCRIPTION (Continued)

ML4805

operating frequency can typically be approximated by:

OSC

t

RAMP

(5)

1

=

f

EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:

==100

fkHz

OSC

=´´=´

tRC

RAMP T T

051 1 10

.

1

t

RAMP

-

5

Solving for RT x CT yields 2 x 10-4. Selecting standard
components values, CT = 270pF, and RT = 36.5kΩ.

PWM SECTION

Pulse Width Modulator

The PWM section of the ML4805 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device. The PWM is capable of current­mode or voltage mode operation. In current-mode
applications, the PWM ramp (RAMP 2) is usually derived
directly from a current sensing resistor or current
transformer in the primary of the output stage, and is
thereby representative of the current flowing in the
converter’s output stage. DC I

, which provides

LIMIT

cycle-by-cycle current limiting, is typically connected to
RAMP 2 in such applications. For voltage-mode operation
or certain specialized applications, RAMP 2 can be
connected to a separate RC timing network to generate a
voltage ramp against which V DC will be compared. Under
these conditions, the use of voltage feedforward from the
PFC buss can assist in line regulation accuracy and
response. As in current mode operation, the DC I

LIMIT

input is used for output stage overcurrent protection.

VIN OK Comparator

The V

OK comparator monitors the DC output of the

IN

PFC and inhibits the PWM if this voltage on VFB is less
than its nominal 2.5V. Once this voltage reaches 2.5V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start
commences.

PWM Control (RAMP 2)

When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
timing components (R

RAMP2

, C

), which will have a

RAMP2

minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,
feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.

Soft Start

Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 25µA
supplies the charging current for the capacitor, and start­up of the PWM begins at 1.25V. Start-up delay can be
programmed by the following equation:

A

µ

=×

Ct

SS DELAY

25

.

125

V

(6)

where CSS is the required soft start capacitance, and
t

is the desired start-up delay.

DELAY

It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.

No voltage error amplifier is included in the PWM stage
of the ML4805, as this function is generally performed on
the output side of the PWM’s isolation boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into the PWM’s RAMP 2 input which
allows VDC to command a zero percent duty cycle for
input voltages below 1.25V.

PWM Current Limit

The DC I

pin is a direct input to the cycle-by-cycle

LIMIT

current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1.5V, the output of the
PWM will be disabled until the output flip-flop is reset by
the clock pulse at the start of the next PWM power cycle.

Solving for the minimum value of CSS:

25

A

=× =5

Cms

SS

125

.

µ

V

100

nF

In the ML4805, the operating frequency of the PFC
section is fixed at 1/2 of the PWM's operating frequency.
This is done through the use of a 2:1 digital frequency
divider ("T" flip-flop) linking the two functional sections of
the IC.

9

ML4805

FUNCTIONAL DESCRIPTION (Continued)

Generating V

The ML4805 is a voltage-fed part. It requires an external
15V±10% or better Zener shunt voltage regulator, or some
other controlled supply, to regulate the voltage supplied
to the part at 15V nominal. This allows a low power
dissipation while at the same time delivering 13V
nominal of gate drive at the PWM OUT and PFC OUT
outputs. If using a Zener diode, it is important to limit the
current through the Zener to avoid overheating or
destroying it. This can be easily done with a single resistor
in series with the Vcc pin, returned to a bias supply of
typically 18V to 20V. The resistor’s value must be chosen
to meet the operating current requirement of the ML4805
itself (8.5mA max.) plus the current required by the two
gate driver outputs.

EXAMPLE:
With a V
driving a total gate charge of 110nC at 100kHz (1 IRF840
MOSFET and 2 IRF830 MOSFETs), the gate driver current
required is:

IkHznCmA

GATEDRIVE

R

BIAS

The ML4805 should be locally bypassed with a 10nF and
a 1µF ceramic capacitor. In most applications, an
electrolytic capacitor of between 100µF and 330µF is also
required across the part, both for filtering and as part of
the start-up bootstrap circuitry.

CC

of 20V, a VCC limit of 16.5V (max) and

BIAS

=´=100 110 11

-

VV

20 16 5

=

mA mA

75 11

.

.

=

180

+

Ω

LEADING/TRAILING MODULATION

Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 3 shows a typical trailing edge
control scheme.

In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 4
shows a leading edge control scheme.

One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC’s output
ripple voltage can be reduced by as much as 30% using
this method.

+

VIN

DC

10

REF

OSC

U4

L1

I1

U3

+

EA

–

RAMP

CLK

SW2

SW1

+

–

U1

I2 I3

I4

C1

D

SW2

SW1

I2 I3

VEAO

+
–

C1

CMP

U1

I4

RL

RAMP

VEAO

DFF

R

Q

D

U2

Q

CLK

VSW1

TIME

TIME

L1
I1

+

DC

VIN

REF

OSC

U4

U3

+

EA

–

RAMP

CLK

RL

RAMP

VEAO

DFF

R

Q

U2

Q

CLK

VSW1

TIME

TIME

Figure 4. Leading/Trailing Edge Control SchemeFigure 3. Typical Trailing Edge Control Scheme

ML4805

160

(µA)

0

VEAO

I

–160

024

13

VFB (V)

Figure 5. I

VEAO

vs. V

FB

5

180

90

µS

0

024

13

VFB (V)

Figure 6. gM of V

OTA

5

200

160

120

µS

80

40

0

024

13

V

(V)

FB

Figure 7. gM of I

OTA

5

500

K

0

024

13

VFB (V)

Figure 8. K of Multiplier

5

11

PHYSICAL DIMENSIONS inches (millimeters)

Package: P18

18-Pin PDIP

0.890 - 0.910

(22.60 - 23.12)

18

ML4805

0.045 MIN
(1.14 MIN)
(4 PLACES)

0.170 MAX

(4.32 MAX)

0.125 MIN
(3.18 MIN)

18

PIN 1 ID

1

0.449 - 0.463

(11.40 - 11.76)

0.050 - 0.065
(1.27 - 1.65)

0.016 - 0.022
(0.40 - 0.56)

0.100 BSC
(2.54 BSC)

SEATING PLANE

Package: S18

18-Pin SOIC

0.240 - 0.260
(6.09 - 6.61)

0.015 MIN
(0.38 MIN)

0.295 - 0.325
(7.49 - 8.26)

0º - 15º

0.008 - 0.012
(0.20 - 0.31)

0.024 - 0.034
(0.61 - 0.86)

(4 PLACES)

0.090 - 0.094
(2.28 - 2.39)

0.291 - 0.301
(7.39 - 7.65)

PIN 1 ID

1

0.050 BSC
(1.27 BSC)

0.012 - 0.020
(0.30 - 0.51)

0.095 - 0.107
(2.41 - 2.72)

SEATING PLANE

0.398 - 0.412

(10.11 - 10.47)

0.005 - 0.013
(0.13 - 0.33)

0º - 8º

0.022 - 0.042
(0.56 - 1.07)

0.009 - 0.013
(0.22 - 0.33)

15

ML4805

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE

ML4805CP 0°C to 70°C 18-Pin Plastic DIP (P18)
ML4805CS 0°C to 70°C 18-Pin Wide SOIC (S18)

ML4805IP -40°C to 85°C 18-Pin Plastic DIP (P18)
ML4805IS -40°C to 85°C 18-Pin Wide SOIC (S18)

© Micro Linear 1998. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502;

5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897;
5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669;
5,825,165; 5,825,223; 5,838,723. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability
arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits
contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits
infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult
with appropriate legal counsel before deciding on a particular application.

13

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T el: [phone]

Fax: [phone]

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DS4805-01