Datasheet ML4804CP Datasheet (Fairchild Semiconductor)

March 2001

PRELIMINARY

ML4804

Power Factor Correction and PWM Controller Combo

GENERAL DESCRIPTION

The ML4804 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk
capacitors, reduces power line loading and stress on the
switching FETs, and results in a power supply that fully
complies with IEC1000-3-2 specification. Intended as a
BiCMOS enhancement of the industry-standard ML4824,
the ML4804 includes circuits for the implementation of
leading edge, average current, “boost” type power factor
correction and a trailing edge, pulse width modulator
(PWM). It also includes a TriFault Detect™ function to
help ensure that no unsafe conditions will result from
single component failure in the PFC. 1A gate-drive
outputs minimize the need for external driver circuits.
Low power requirements improve efficiency and reduce
component costs.

An over voltage comparator shuts down the PFC section
in the event of a sudden decrease in load. The PFC
section also includes peak current limiting and input
voltage brownout protection. The PWM section can be
operated in current or voltage mode, at up to 250kHz,
and includes an accurate 50% duty cycle limit to prevent
transformer saturation.

FEATURES

■ Internally synchronized leading-edge modulated PFC

and trailing-edge modulated PWM in one IC

■ TriFault Detect

enhanced safety

■ V

OVP provides additonal PFC fault protection

CC

■ Slew rate enhanced transconductance error amplifier

for ultra-fast PFC response

■ Low power: 200µA startup current, 5.5mA operating

current

■ Low total harmonic distortion, high PF

■ Reduces ripple current in the storage capacitor

between the PFC and PWM sections

■ Average current, continuous boost leading edge PFC

■ PWM configurable for current-mode or voltage mode

operation

■ Overvoltage and brown-out protection, UVLO, and soft

start

TM

for UL1950 compliance and

BLOCK DIAGRAM

VEAO

15

2

4

3

7

8

6

5

9

V

2.5V

I

AC

V

I

SENSE

RAMP 1

RAMP 2

V

SS

DC I

FB

RMS

DC

V

CC

LIMIT

VEA

-

+

25µA

V

GAIN

MODULATOR

1.25V

REF

16

1.6kΩ

1.6kΩ

1

IEAO

IEA

+

-

-

+

-

+

POWER FACTOR CORRECTOR

0.5V

OSCILLATOR

TRI-FAULT

+

–

V

CC

16.4V

+

-

V

-

FB

2.45V

+

PULSE WIDTH MODULATOR

VCCOVP

+

–

DUTY CYCLE

VIN OK

LIMIT

2.75V

-1V

1.0V

PFC I

-

+

OVP

+

-

+

-

LIMIT

DC I

LIMIT

V

CC

V

CC

17V

SRQ

SRQ

SRQ

UVLO

13

7.5V

REFERENCE

Q

Q

Q

V

CC

V

PFC OUT

PWM OUT

REF

14

12

11

REV. 1.0.2 3/9/2001

ML4804

PIN CONFIGURATION

ML4804

16-Pin PDIP (P16)

16-Pin Narrow SOIC (S16N)

PIN DESCRIPTION

PIN NAME FUNCTION

1 IEAO Slew rate enhanced PFC

transconductance error amplifier output

2I

AC

3I

SENSE

PFC AC line reference input to Gain
Modulator

Current sense input to the PFC Gain
Modulator

IEAO

I

AC

I

SENSE

V

RMS

SS

V

DC

RAMP 1

RAMP 2

1

2

3

4

5

6

7

8

TOP VIEW

16

VEAO

15

V

FB

14

V

REF

13

V

CC

12

PFC OUT

11

PWM OUT

10

GND

9

DC I

LIMIT

PIN NAME FUNCTION

9 DC I

LIMIT

PWM cycle-by-cycle current
limit comparator input

10 GND Ground

11 PWM OUT PWM driver output

12 PFC OUT PFC driver output

4V

RMS

PFC Gain Modulator RMS line voltage
compensation input

5 SS Connection point for the PWM soft start

capacitor

6V

DC

PWM voltage feedback input

7 RAMP 1 Oscillator timing node; timing set

by R

TCT

8 RAMP 2 When in current mode, this pin

functions as the current sense input;
when in voltage mode, it is the PWM
modulation ramp input.

13 V

14 V

CC

REF

Positive supply

Buffered output for the internal

7.5V reference

15 V

FB

PFC transconductance voltage
error amplifier input

16 VEAO PFC transconductance voltage

error amplifier output

2 REV. 1.0.2 3/9/2001

ABSOLUTE MAXIMUM RATINGS

ML4804

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.

Junction Temperature ............................................. 150°C

Storage Temperature Range ....................... -65°C to 150°C

Lead Temperature (Soldering, 10 sec)..................... 260°C

Thermal Resistance (θ

)

JA

Plastic DIP ...........................................................80°C/W

V

..............................................................................................

CC

Voltage ............................................... -5V to 0.7V

I

SENSE

Voltage on Any Other Pin .....GND - 0.3V to V

I

...........................................................................................

REF

I

Input Current .....................................................10mA

AC

CCZ

18V

+ 0.3V

10mA

Peak PFC OUT Current, Source or Sink ....................... 1A

Peak PWM OUT Current, Source or Sink..................... 1A

Plastic SOIC ...................................................... 105°C/W

OPERATING CONDITIONS

Temperature Range

ML4804CX .................................................... 0°C to 70°C

ML4804IX .................................................. -40°C to 85°C

PFC OUT, PWM OUT Energy Per Cycle................... 1.5µJ

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOLTAGE ERROR AMPLIFIER

Input Voltage Range 0 5 V

Transconductance V

Feedback Reference Voltage 2.43 2.5 2.57 V

NON INV

= V

, VEAO = 3.75V 30 65 90 µ

INV

Ω

Input Bias Current Note 2 -0.5 -1.0 µA

Output High Voltage 6.0 6.7 V

Output Low Voltage 0.1 0.4 V

Source Current VIN = 2.5V ± 0.5V, V

Sink Current VIN = 2.5V ± 0.5V , V

Open Loop Gain 50 60 dB

Power Supply Rejection Ratio 11V < VCC < 16.5V 50 60 dB

CURRENT ERROR AMPLIFIER

Input Voltage Range -1.5 2 V

Transconductance V

Input Offset Voltage 0 4 15 mV

Input Bias Current -0.5 -1.0 µA

Output High Voltage 6.0 6.7 V

Output Low Voltage 0.65 1.0 V

Source Current VIN = ±0.5V, V

Sink Current VIN = ±0.5V, V

Open Loop Gain 60 70 dB

Power Supply Rejection Ratio 11V < VCC < 16.5V 60 75 dB

OVP COMPARATOR

NON INV

= 6V -40 -140 µA

OUT

= 1.5V 40 140 µA

OUT

= V

, VEAO = 3.75V 50 100 150 µ

INV

= 6V -40 -104 µA

OUT

= 1.5V 40 160 µA

OUT

Ω

Threshold Voltage 2.65 2.75 2.85 V

Hysteresis 180 280 350 mV

REV. 1.0.2 3/9/2001 3

ML4804

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

TRI-FAULT DETECT

Fault Detect HIGH 2.65 2.75 2.85 V

Time to Fault Detect HIGH V

Fault Detect LOW 0.4 0.5 0.6 V

VCCOVP COMPARATOR

Threshold Voltage TA = Operation Temp Range 16.4 V

Hysteresis TA = Operation Temp Range 1.7 2.0 2.3 V

= V

FB

FAULT DETECT LOW

to VFB =OPEN; 470pF from VFB to GND

24ms

PFC I

COMPARATOR

LIMIT

Threshold Voltage -0.9 -1.0 -1.1 V

(PFC I

LIMIT VTH

Delay to Output 150 300 ns

DC I

COMPARATOR

LIMIT

Threshold Voltage 0.95 1.0 1.05 V

Input Bias Current ±0.3 ± 1 µA

Delay to Output 150 300 ns

VIN OK COMPARATOR

Threshold Voltage 2.35 2.45 2.55 V

Hysteresis 0.8 1.0 1.2 V

GAIN MODULATOR

Gain (Note 3) IAC = 100µA, V

Bandwidth IAC = 100µA 10 MHz

Output Voltage I

- Gain Modulator Output) 120 220 mV

= VFB = 0V 0.60 0.80 1.05

RMS

IAC = 50µA, V

IAC = 50µA, V

IAC = 100µA, V

= 350µA, V

AC

= 1.2V, VFB = 0V 1.8 2.0 2.40

RMS

= 1.8V, VFB = 0V 0.85 1.0 1.25

RMS

= 3.3V, VFB = 0V 0.20 0.30 0.40

RMS

= 1V, 0.60 0.75 0.9 V

RMS

VFB = 0V

OSCILLATOR

Initial Accuracy TA = 25°C 717681kHz

Voltage Stability 11V < VCC < 16.5V 1 %

Temperature Stability 2%

Total Variation Line, Temp 68 84 kHz

Ramp Valley to Peak Voltage 2.5 V

PFC Dead Time 520 600 ns

f

= 250kHz, RT = 75.0kΩ, CT = 100pF 250 3 30 n s

OSC

CT Discharge Current V

RAMP 2

= 0V, V

= 2.5V 3.5 5.5 7.5 mA

RAMP 1

4 REV. 1.0.2 3/9/2001

ML4804

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

REFERENCE

PFC

PWM

Output Voltage TA = 25°C, I(V

) = 1mA 7.4 7.5 7.6 V

REF

Line Regulation 11V < VCC < 16.5V 10 25 mV

Load Regulation 0mA < I(V

) < 10mA; 10 20 mV

REF

TA = 0ºC to 70ºC

0mA <I(V

) <5mA: 10 20 mV

REF

TA = –40ºC to 85ºC

Temperature Stability 0.4 %

Total Variation Line, Load, Temp 7.35 7.65 V

Long Term Stability TJ = 125°C, 1000 Hours 5 25 mV

Minimum Duty Cycle V

Maximum Duty Cycle V

Output Low Voltage I

Output High Voltage I

> 4.0V 0 %

IEAO

< 1.2V 90 95 %

IEAO

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.7 2.0 V

OUT

I

= 10mA, VCC = 9V 0.4 0.8 V

OUT

= 20mA V

OUT

I

= 100mA V

OUT

– 0.8V V

CC

- 2V V

CC

Rise/Fall Time CL = 1000pF 50 ns

Duty Cycle Range 0-44 0-47 0-49 %

Output Low Voltage I

Output High Voltage I

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.7 2.0 V

OUT

I

= 10mA, VCC = 9V 0.4 0.8 V

OUT

= 20mA V

OUT

I

= 100mA V

OUT

Rise/Fall Time CL = 1000pF 50 ns

SUPPLY

Start-up Current VCC = 12V, CL = 0 200 350 µA

Operating Current 14V, CL = 0 5.5 7 mA

Undervoltage Lockout Threshold 12.4 13 13.6 V

Undervoltage Lockout Hysteresis (Note 4) 2.5 2.8 3.1 V

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

Note 2: Includes all bias currents to other circuits connected to the V

Note 3: Gain = K x 5.3V; K = (I

Note 4: UVLO Hysteresis

GAINMOD

- I

) x [IAC (VEAO - 0.625)]-1; VEAO

OFFSET

pin.

FB

MAX

=5V.

– 0.8V V

CC

- 2V V

CC

REV. 1.0.2 3/9/2001 5

ML4804

VARIABLE GAIN BLOCK CONSTANT (K)

VRMS(V)

0245

13

480

420

360

300

240

180

120

60

0

K

IA

IV V

GAINMOD

AC

=

×.

84

5 0 625

µ

bg

af

TYPICAL PERFORMANCE CHARACTERISTICS

180

160

Ω

140

120

100

80

60

40

TRANSCONDUCTANCE (µ )

20

0

053

142

VFB (V)

Voltage Error Amplifier (VEA) Transconductance (gm)

180

160

Ω

140

120

100

80

60

40

TRANSCONDUCTANCE (µ )

20

0
–500 5000

IEA INPUT VOLTAGE (mV)

Current Error Amplifier (IEA) Transconductance (g

Gain Modulator Transfer Characteristic (K)

)

m

6 REV. 1.0.2 3/9/2001

FUNCTIONAL DESCRIPTION

ML4804

The ML4804 consists of an average current controlled,
continuous boost Power Factor Corrector (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM can be used in either current or voltage
mode. In voltage mode, feedforward from the PFC output
buss can be used to improve the PWM’s line regulation. In
either mode, the PWM stage uses conventional trailing­edge duty cycle modulation, while the PFC uses leading­edge modulation. This patented leading/trailing edge
modulation technique results in a higher useable PFC
error amplifier bandwidth, and can significantly reduce
the size of the PFC DC buss capacitor.

The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the controlled ripple on
the PFC output capacitor (the PWM input capacitor). The
PWM section of the ML4804 runs at the same frequency
as the PFC.

In addition to power factor correction, a number of
protection features have been built into the ML4804.
These include soft-start, PFC over-voltage protection, peak
current limiting, brownout protection, duty cycle limiting,
and under-voltage lockout.

POWER FACTOR CORRECTION

Power factor correction makes a non-linear load look like
a resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with and proportional to
the line voltage, so the power factor is unity (one). A
common class of non-linear load is the input of most
power supplies, which use a bridge rectifier and
capacitive input filter fed from the line. The peak­charging effect, which occurs on the input filter capacitor
in these supplies, causes brief high-amplitude pulses of
current to flow from the power line, rather than a
sinusoidal current in-phase with the line voltage. Such
supplies present a power factor to the line of less than one
(i.e. they cause significant current harmonics of the power
line frequency to appear at their input). If the input
current drawn by such a supply (or any other non-linear
load) can be made to follow the input voltage in
instantaneous amplitude, it will appear resistive to the AC
line and a unity power factor will be achieved.

output voltage of the boost converter must be set higher
than the peak value of the line voltage. A commonly
used value is 385VDC, to allow for a high line of
270VAC

. The other condition is that the current drawn

rms

from the line at any given instant must be proportional to
the line voltage. Establishing a suitable voltage control
loop for the converter, which in turn drives a current error
amplifier and switching output driver satisfies the first of
these requirements. The second requirement is met by
using the rectified AC line voltage to modulate the output
of the voltage control loop. Such modulation causes the
current error amplifier to command a power stage current
that varies directly with the input voltage. In order to
prevent ripple, which will necessarily appear at the
output of the boost circuit (typically about 10VAC on a
385V DC level), from introducing distortion back through
the voltage error amplifier, the bandwidth of the voltage
loop is deliberately kept low. A final refinement is to
adjust the overall gain of the PFC such to be proportional
to 1/V

2

, which linearizes the transfer function of the

IN

system as the AC input voltage varies.

Since the boost converter topology in the ML4804 PFC is
of the current-averaging type, no slope compensation is
required.

PFC SECTION

Gain Modulator

Figure 1 shows a block diagram of the PFC section of the
ML4804. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the
current loop to line voltage waveform and frequency, rms
line voltage, and PFC output voltage. There are three
inputs to the gain modulator. These are:

1) A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectified
AC input sine wave is converted to a proportional
current via a resistor and is then fed into the gain
modulator at I

. Sampling current in this way

AC

minimizes ground noise, as is required in high power
switching power conversion environments. The gain
modulator responds linearly to this current.

To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the
input voltage, a way must be found to prevent that device
from loading the line except in proportion to the
instantaneous line voltage. The PFC section of the
ML4804 uses a boost-mode DC-DC converter to
accomplish this. The input to the converter is the full
wave rectified AC line voltage. No bulk filtering is
applied following the bridge rectifier, so the input voltage
to the boost converter ranges (at twice line frequency)

2) A voltage proportional to the long-term RMS AC line
voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the gain
modulator at V
inversely proportional to V
low values of V

. The gain modulator’s output is

RMS

where special gain contouring

RMS

2

(except at unusually

RMS

takes over, to limit power dissipation of the circuit
components under heavy brownout conditions). The
relationship between V

and gain is called K, and is

RMS

illustrated in the Typical Performance Characteristics.

from zero volts to the peak value of the AC input and
back to zero. By forcing the boost converter to meet two
simultaneous conditions, it is possible to ensure that the
current drawn from the power line is proportional to the

3) The output of the voltage error amplifier, VEAO. The
gain modulator responds linearly to variations in this
voltage.

input line voltage. One of these conditions is that the

REV. 1.0.2 3/9/2001 7

ML4804

FUNCTIONAL DESCRIPTION (Continued)

The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way
the gain modulator forms the reference for the current
error loop, and ultimately controls the instantaneous
current draw of the PFC from the power line. The general
form for the output of the gain modulator is:

I

GAINMOD

=

V

RMS

×

V

1

2

(1)

(1)

×

IVEAO

AC

More exactly, the output current of the gain modulator is
given by:

I K VEAO V I

GAINMOD AC

where K is in units of V

=× − ×(.)0 625

-1

.

Note that the output current of the gain modulator is
limited to 500µA.

Current Error Amplifier

The current error amplifier’s output controls the PFC duty
cycle to keep the average current through the boost
inductor a linear function of the line voltage. At the
inverting input to the current error amplifier, the output
current of the gain modulator is summed with a current
which results from a negative voltage being impressed
upon the I

pin. The negative voltage on I

SENSE

SENSE

represents the sum of all currents flowing in the PFC
circuit, and is typically derived from a current sense
resistor in series with the negative terminal of the input
bridge rectifier. In higher power applications, two current
transformers are sometimes used, one to monitor the I
the boost MOSFET(s) and one to monitor the I

of the

F

of

D

boost diode. As stated above, the inverting input of the
current error amplifier is a virtual ground. Given this fact,
and the arrangement of the duty cycle modulator
polarities internal to the PFC, an increase in positive
current from the gain modulator will cause the output
stage to increase its duty cycle until the voltage on
I

is adequately negative to cancel this increased

SENSE

current. Similarly, if the gain modulator’s output
decreases, the output duty cycle will decrease, to
achieve a less negative voltage on the I

SENSE

pin.

Cycle-By-Cycle Current Limiter

The I

pin, as well as being a part of the current

SENSE

feedback loop, is a direct input to the cycle-by-cycle
current limiter for the PFC section. Should the input
voltage at this pin ever be more negative than -1V, the
output of the PFC will be disabled until the protection
flip-flop is reset by the clock pulse at the start of the next
PFC power cycle.

TriFault Detect

TM

To improve power supply reliability, reduce system
component count, and simplify compliance to UL 1950
safety standards, the ML4800 (ML4804) includes TriFault
Detect. This feature monitors VFB (Pin 15) for certain PFC
fault conditions.

In the case of a feedback path failure, the output of the
PFC could go out of safe operating limits. With such a
failure, VFB will go outside of its normal operating area.
Should VFB go too low, too high, or open, TriFault Detect
senses the error and terminates the PFC output drive.

TriFault detect is an entirely internal circuit. It requires no
external components to serve its protective function.

15

2

4

3

7

V

FB

2.5V

I

AC

V

RMS

I

SENSE

RAMP 1

VEAO

VEA

–

+

MODULATOR

16

GAIN

1.6kΩ

IEA

+

–

1.6kΩ

IEAO

1

0.5V

16.4V

+

–

OSCILLATOR

+

–

V

CC

TRI-FAULT

VCCOVP

+

–

2.75V

–1V

OVP

+

–

+

–

PFC I

LIMIT

SRQ

SRQ

Q

PFC OUT

12

Q

Figure 1. PFC Section Block Diagram

8 REV. 1.0.2 3/9/2001

FUNCTIONAL DESCRIPTION (Continued)

ML4804

Overvoltage Protection

The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load
should suddenly change. A resistor divider from the high
voltage DC output of the PFC is fed to V
voltage on V

exceeds 2.75V, the PFC output driver is

FB

. When the

FB

shut down. The PWM section will continue to operate. The
OVP comparator has 250mV of hysteresis, and the PFC
will not restart until the voltage at V
The V

should be set at a level where the active and

FB

drops below 2.50V.

FB

passive external power components and the ML4804 are
within their safe operating voltages, but not so low as to
interfere with the boost voltage regulation loop.

V

OVP

CC

The V
TriFault

OVP feature of the ML4804 works along with the

CC

TM

Detect as a redundant PFC buss voltage limiter,
to prevent a damaged and broken connection or
component from causing an unsafe fault condition.

V

OVP assumes that VCC is generated from a bootstrap

CC

winding on the PFC boost inductor, or by some other
means whereby V
proportionality is exact, then a nominal V
V

= 15.0V will cause the VCCOVP comparator to shut

CC

the PFC down when V
The PFC will then remain in the shutdown state until V

is proportional to V

CC

= [(16.4/15.0) x 385V] = 444V.

BUSS

BUSS

BUSS

. If the

of 385V at

CC

declines to 13.0V, at which time the PFC will restart. If
the PFC V

again encounters an over voltage condition,

CC

the protection cycle will repeat. Note that the PWM stage
of the ML4804 remains operational even when the PFC
goes into V

OVP shutdown.

CC

For a real-world example, assume that the bootstrap
supply is derived from a conventional boost inductor
winding and rectified using Shottky diodes. Then it follows

that the voltage from the bootstrap winding must equal

15.8V during regular circuit operation, and will increase
to 17.2V at the point of V

OVP shutdown. Then the

CC

output voltage from the PFC will have increased from a
noninal V
419VDC. When V

of 385VDC to (17.2/15.8) x 385V =

BUSS

reaches 419V, the PFC will shut

BUSS

off, thereby protecting the output (BUSS) capacitor and
the semiconductors in both the PFC and PWM stages.

To assure reasonable headroom in which to operate this
device, V

OVP tracks with UVLO. The VCCOVP

CC

threshold is always at least 2V above that of the UVLO.

To assure reliable operation of the ML4804, V

must be

CC

operated from a bootstrap winding on the PFC’s inductor,
or from an external power supply whose output is
regulated to 15.0V (nominal). In the case of a regulated
power supply powering the ML4804, the V

OVP function

CC

will be rendered non-operational.

Error Amplifier Compensation

The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the PFC's two
transconductance error amplifiers. Figure 2 shows the
types of compensation networks most commonly used for
the voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to V

to produce a soft-start characteristic on

REF

the PFC: as the reference voltage comes up from zero
volts, it creates a differentiated voltage on IEAO which
prevents the PFC from immediately demanding a full duty
cycle on its boost converter.

There are two major concerns when compensating the

V

REF

V

PFC

OUTPUT

16

VEAO

V

FB

15

2.5V

I

AC

2

V

RMS

4

I

SENSE

3

VEA

–

+

MODULATOR

+

–

GAIN

1

IEAO

IEA

+

–

BIAS

V

CC

ML4804

GND

R

BIAS

0.22µF

CERAMIC

15V

ZENER

Figure 2. Compensation Network Connections for the

Voltage and Current Error Amplifiers

REV. 1.0.2 3/9/2001 9

Figure 3. External Component Connections to V

CC

ML4804

FUNCTIONAL DESCRIPTION (Continued)

voltage loop error amplifier; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest
anticipated international power frequency). The gain vs.
input voltage of the ML4804’s voltage error amplifier has
a specially shaped nonlinearity such that under steady­state operating conditions the transconductance of the
error amplifier is at a local minimum. Rapid perturbations
in line or load conditions will cause the input to the
voltage error amplifier (V
(nominal) value. If this happens, the transconductance of
the voltage error amplifier will increase significantly, as
shown in the Typical Performance Characteristics. This
raises the gain-bandwidth product of the voltage loop,
resulting in a much more rapid voltage loop response to
such perturbations than would occur with a conventional
linear gain characteristic.

The current amplifier compensation is similar to that of
the voltage error amplifier with the exception of the
choice of crossover frequency. The crossover frequency of
the current amplifier should be at least 10 times that of
the voltage amplifier, to prevent interaction with the
voltage loop. It should also be limited to less than 1/6th
that of the switching frequency, e.g. 16.7kHz for a
100kHz switching frequency.

There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be
the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier. This is illustrated in the
Typical Performance Characteristics.

For more information on compensating the current and
voltage control loops, see Application Notes 33 and 34.
Application Note 16 also contains valuable information
for the design of this class of PFC.

Oscillator (RAMP 1)

The oscillator frequency is determined by the values of R
and CT, which determine the ramp and off-time of the
oscillator output clock:

=

f

OSC

tt

RAMP DEADTIME

The deadtime of the oscillator is derived from the
following equation:

=××

tCRIn

RAMP T T

1

+

) to deviate from its 2.5V

FB

F

V

REF

G

V

H

REF

−

−

125

375..

I
J

K

(2)

(3)

at V

= 7.5V:

REF

=××051.

tCR

RAMP T T

The deadtime of the oscillator may be determined using:

V

25

.

t

DEADTIME T T

The deadtime is so small (t
operating frequency can typically be approximated by:

f

OSC

EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:

fkHz

OSC

Solving for R
components values, C

The deadtime of the oscillator adds to the Maximum
PWM Duty Cycle (it is an input to the Duty Cycle
Limiter). With zero oscillator deadtime, the Maximum
PWM Duty Cycle is typically 45%. In many applications,
care should be taken that C
extend the Maximum Duty Cycle beyond 50%. This can
be accomplished by using a stable 390pF capacitor for C

PWM SECTION

Pulse Width Modulator

The PWM section of the ML4804 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing. The PWM is capable of current-mode or voltage
mode operation. In current-mode applications, the PWM
ramp (RAMP 2) is usually derived directly from a current
sensing resistor or current transformer in the primary of the
output stage, and is thereby representative of the current

T

flowing in the converter’s output stage. DC I
provides cycle-by-cycle current limiting, is typically
connected to RAMP 2 in such applications. For voltage­mode operation or certain specialized applications,
RAMP 2 can be connected to a separate RC timing
network to generate a voltage ramp against which V
will be compared. Under these conditions, the use of
voltage feedforward from the PFC buss can assist in line
regulation accuracy and response. As in current mode
operation, the DC I
stage overcurrent protection.

=×=×

55

.

1

=

t

RAMP

==100

x CT yields 1.96 x 10-4. Selecting standard

T

CC

RAMP

450

>> t

DEADTIME

mA

1

t

RAMP

= 390pF, and RT = 51.1kΩ.

T

not be made so large as to

T

input would is used for output

LIMIT

) that the

, which

LIMIT

DC

(4)

(5)

.

T

10 REV. 1.0.2 3/9/2001

FUNCTIONAL DESCRIPTION (Continued)

ML4804

No voltage error amplifier is included in the PWM stage of
the ML4804, as this function is generally performed on the
output side of the PWM’s isolation boundary. To facilitate
the design of optocoupler feedback circuitry, an offset has
been built into the PWM’s RAMP 2 input which allows
V

to command a zero percent duty cycle for input

DC

voltages below 1.25V.

PWM Current Limit

The DC I

pin is a direct input to the cycle-by-cycle

LIMIT

current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output of the PWM
will be disabled until the output flip-flop is reset by the
clock pulse at the start of the next PWM power cycle.

V

OK Comparator

IN

The V
PFC and inhibits the PWM if this voltage on V

OK comparator monitors the DC output of the

IN

FB

is less
than its nominal 2.45V. Once this voltage reaches 2.45V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start begins.

PWM Control (RAMP 2)

When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
timing components (R

RAMP2

, C

), that will have a

RAMP2

minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,

feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.

Soft Start

Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 25µA
supplies the charging current for the capacitor, and start­up of the PWM begins at 1.25V. Start-up delay can be
programmed by the following equation:

A

µ

=×

Ct

SS DELAY

where C
t

DELAY

is the required soft start capacitance, and

SS

is the desired start-up delay.

25

.

125

V

(6)

It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.

Solving for the minimum value of C

25

A

=× =5

Cms

SS

125

.

µ

100

V

nF

:

SS

(6a)

Caution should be exercised when using this minimum
soft start capacitance value because premature charging of
the SS capacitor and activation of the PWM section can
result if V
comparator at start-up. The magnitude of V

is in the hysteresis band of the VIN OK

FB

FB

at start-up is
related both to line voltage and nominal PFC output
voltage. Typically, a 1.0µF soft start capacitor will allow
time for V

and PFC out to reach their nominal values

FB

prior to activation of the PWM section at line voltages
between 90Vrms and 265Vrms.

SW2

SW1

+

–

U1

I2 I3

I4

C1

RL

RAMP

VEAO

DFF

R

Q

U2

D

Q

CLK

VSW1

TIME

TIME

+

DC

VIN

L1

I1

REF

OSC

U4

U3

+

EA

–

RAMP

CLK

Figure 4. Typical Trailing Edge Control Scheme

REV. 1.0.2 3/9/2001 11

ML4804

FUNCTIONAL DESCRIPTION (Continued)

Generating V

CC

The ML4804 is a voltage-fed part. It requires an external
15V, ±10% (or better) shunt voltage regulator, or some
other V

regulator, to regulate the voltage supplied to

CC

the part at 15V nominal. This allows low power dissipation
while at the same time delivering 13V nominal gate drive
at the PWM OUT and PFC OUT outputs. If using a Zener
diode for this function, it is important to limit the current
through the Zener to avoid overheating or destroying it.
This can be easily done with a single resistor in series
with the Vcc pin, returned to a bias supply of typically
18V to 20V. The resistor’s value must be chosen to meet
the operating current requirement of the ML4804 itself
(8.5mA, max.) plus the current required by the two gate
driver outputs.

EXAMPLE:
With a V

of 20V, a VCC of 15V and the ML4804

BIAS

driving a total gate charge of 90nC at 100kHz (e.g., 1
IRF840 MOSFET and 2 IRF820 MOSFETs), the gate driver
current required is:

IkHznCmA

GATEDRIVE

R

BIAS

R

BIAS

Choose R

=×=100 90 9

−

VV

BIAS CC

=

++

IIIz

CC G

−

VV

20 15

=

++

mA mA mAIz

695

< 240Ω

BIAS

=

250Ω

(7)

(8)

LEADING/TRAILING MODULATION

Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 4 shows a typical trailing edge
control scheme.

In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 5
shows a leading edge control scheme.

One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC’s output
ripple voltage can be reduced by as much as 30% using
this method.

The ML4804 should be locally bypassed with a 1.0µF
ceramic capacitor. In most applications, an electrolytic
capacitor of between 47µF and 220µF is also required
across the part, both for filtering and as part of the start-up
bootstrap circuitry.

SW2

SW1

VEAO

+

–

CMP

U1

I2 I3

I4

C1

R

D

+

DC

VIN

L1

I1

REF

OSC

U4

U3

+

EA

–

RAMP

CLK

Figure 5. Typical Leading Edge Control Scheme

DFF

U2

CLK

TYPICAL APPLICATIONS

Figure 6 is the application circuit for a complete 100W
power factor corrected power supply, designed using the
methods and general topology detailed in Application
Note 33.

RAMP

RL

Q

Q

VEAO

TIME

VSW1

TIME

12 REV. 1.0.2 3/9/2001

ML4804

IEAO

I

AC

I

SENSE

V

RMS

SS

V

DC

RTCT

RAMP 1

VDC

V

FB

V

REF

V

CC

PFC OUT

PWM OUT

GND

RAMP 2

R12 68.1k

C6 1.5nF

C7 150pF

C3

0.22µF

C2

0.47µF

I

SENSE

C11

220pF

C18

390pF

U1

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

R16 10kΩ

R37 1kΩ

PRI GND

NOTE: D8, D10; IN5818

D3, D5, D6, D12; BYV26C

D11; MBR2545CT

L1; 3MHz

L2; PREMIER MAGNETICS VTP-05007

L3; PREMIER MAGNETICS TSD-904

T1; PREMIER MAGNETICS PMGD-03

T2; PREMIER MAGNETICS TSD-735

UNUSED DESIGNATORS; C14, C16, C17, C27, C29, C33, D9, R36, R35, R42, R43,

VDC

U2

R38

51.1kΩ

REF

VFB

C22

10µF

C10

10µF

J8

C23

10nF

C19

1.0µF

D15

1N914

D13

1N914

D14

1N914

RT/CT

D8

V

BUSS

Q2G

Q3G

V

CC

C31

330pF

PWM

ILIMIT

D4

5.1V

D10

U3

TL431C

D11B

D11A

T2

C28

220pF

R10

249kΩ

R9

249kΩ

R20

22Ω

Q1G

Q1

D1

8A

HFA08TB60

D2

0.22µF

L1B

C26

0.22µF

IN5820

IN5820

R1

357kΩ

R2

357kΩ

R3

100kΩ

R4

13.2kΩ

AC INPUT

85 TO 260V

C1

0.47µF

F1

3.15A

BR1

4A, 600V

KBL06

R5

1.2Ω

R8

1.2Ω

R7

1.2Ω

R25

10kΩ

R40

470Ω

R32

8.66kΩ

12V

RETURN

12V RET

R33

2.26kΩ

R29

1.2kΩ

R30

1.5kΩ

C30

1000µF

C32

0.47µF

C21

1500µF

R34

240Ω

C5

100µF

C4

4.7nF

C25

0.1µF

D7

16V

D5

600V

R39

33Ω

R13

383kΩ

R19

33Ω

R14

383kΩ

D6

600V

Q2

Q3

Q4

R18

33Ω

R21

2.2Ω

R17

3Ω

R22

2.2Ω

12V, 100W

12V

C24

0.47µF

R6

1.2Ω

R24

10kΩ

C20

0.47µF

R23

220Ω

T1A

R15

4.99kΩ

R26

10kΩ

R11

412kΩ

R31

10kΩ

R44

10kΩ

L1A

L2

L3

R27

82kΩ

T1B

C13

0.22µF

C15

1.0µF

C8

150nF

C9

15nF

D3

D12

16V

ML4804

REV. 1.0.2 3/9/2001 13

Figure 6. 100W Power Factor Corrected Power Supply, Designed Using Micro Linear Application Note 33

ML4804

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE

ML4804CP 0°C to 70°C 16-Pin PDIP (P16)
ML4804CS 0°C to 70°C 16-Pin Narrow SOIC (S16N)

ML4804IP -40°C to 85°C 16-Pin PDIP (P16)

ML4804IS -40°C to 85°C 16-Pin Narrow SOIC (S16N)

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

www.fairchildsemi.com © 2000 Fairchild Semiconductor Corporation

2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

14 REV. 1.0.2 3/9/2001