The MK2745-21 is a low cost, low jitter, high
performance clock synthesizer for DVD and other
MPEG 2 based applications. Using analog PhaseLocked Loop (PLL) techniques, the device accepts
a 27.00MHz fundamental mode crystal or clock
input to produce multiple output clocks including
the processor clock, the processor clock divided by
two, 27 MHz, 24.576 MHz, and a selectable
audio clock. The audio clocks are frequency
locked to the 27.00MHz input using our patented
zero ppm error techniques, allowing audio and
video to track exactly, thereby eliminating the
need for large buffer memory.
MicroClock manufactures the largest variety of
DVD, Set-Top Box, and multimedia clock
synthesizers for all applications. Consult
MicroClock to eliminate crystals and oscillators
from your board.
Block Diagram
VDD
GND
2
2
Features
• Packaged in 16 pin narrow (150 mil) SOIC
• Ideal for LuxSonor’s DVD solutions
• 3.3V upgrade to MK2744
• Patented zero ppm audio clock error for 256X and
384X sampling rates
• Selectable audio sampling frequencies support
32 kHz, 44.1 kHz, and 48 kHz in most DACs
• 27.00 MHz fundamental crystal or clock input
• Eight selectable processor frequencies
• Fixed clocks of 27 and 24.576 MHz
• Zero ppm error in all clocks
• Full CMOS outputs with 25mA output drive
capability at TTL levels
0 = connect directly to ground
1 = connect directly to VDD
PCLK
AS2
7
8
10
27M
9
AS0
16 pin (150 mil) SOIC
Pin Descriptions
NumberName TypeDescription
1PS1IProcessor clock Select 1. Selects processor clock outputs per table above.
2X2XOCrystal connection. Connect to 27 MHz crystal. Leave unconnected for clock input.
3X1/ICLKXICrystal connection. Connect to 27 MHz crystal or connect to 27 MHz input clock.
4VDDPConnect to +3.3 V or +5 V. Must be same as other VDD.
5GNDPConnect to ground.
6ACLKOAudio Clock output. Determined by status of AS2, AS1, AS0. See table above.
7PCLKOProcessor Clock output. Determined by status of PS1, PS0. See table above.
8AS2IAudio clock Select 2. Selects audio clock on pin 6 per table above.
9AS0IAudio clock Select 0. Selects audio clock on pin 6 per table above.
1027MO27.00 MHz clock output.
11GNDPConnect to ground.
12AS1IAudio clock Select 1. Selects audio clock on pin 6 per table above.
13VDDPConnect to +3.3 V or +5 V. Must be same as other VDD.
14PCLK/2OProcessor Clock divided by two output. Determined by status of PS1, PS0. See table above.
1524.576MO24.576 MHz clock output.
16PS0IProcessor clock Select 0. Selects processor clock outputs per table above.
Key: I = Input, O = output, P = power supply connection
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With Processor clock at 50MHz, and ACLK at 16.93MHz.
DVD/MPEG Clock Source
Electrical Specifications
ParameterConditionsMinimumTypicalMaximumUnits
Supply voltage, VDDReferenced to GND7V
Inputs and Clock OutputsReferenced to GND-0.5VDD+0.5V
Ambient Operating Temperature070°C
Soldering TemperatureMax of 20 seconds260°C
Storage temperature-65150°C
Operating Voltage, VDD 35.5V
Input High Voltage, VIH, X1/ICLK pin onlyVDD/2 + 1VDD/2V
Input Low Voltage, VIL, X1/ICLK pin onlyVDD/2VDD/2 - 1V
Input High Voltage, VIH2V
Input Low Voltage, VIL0.8V
Output High Voltage, VOHIOH=-25mA2.4V
Output Low Voltage, VOLIOL=25mA0.4V
Output High Voltage, VOH, CMOS levelIOH=-8mAVDD-0.4V
Operating Supply Current, IDD No Load, note 237mA
Short Circuit CurrentEach output±100mA
Input Capacitance7pF
Input Frequency27.000MHz
Output Clock Rise Time0.8 to 2.0V1.5ns
Output Clock Fall Time2.0 to 0.8V1.5ns
Output Clock Duty CycleAt VDD/24060%
Frequency error, all clocks01ppm
Absolute Jitter, short termVariation from mean200ps
Notes:1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
External Components
The MK2745-21 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1µF should be connected between VDD and GND, as close to the MK2745-21 as possible.
A series termination resistor of 33Ω may be used for each clock output. If a clock input is not used, the
27.00 MHz crystal must be connected as close to the chip as possible. The crystal should be a fundamental
mode (do not use third overtone), parallel resonant, 50ppm or better. Crystal capacitors should be
connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by the
following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-6) x 2. So for a crystal
with 16pF load capacitance, two 20pF caps should be used.
MK2745-21STRMK2745-21Stape and reel16 pin narrow SOIC0-70°C
Rev. 03318, version A . First publication, Preliminary.
Rev. 04218, version B. Corrected VDD, VIH/VIL under DC Characteristics. Preliminary.
While the information presented herein has been checked for both accuracy and reliability, MicroClock Incorporated assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in
normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by MicroClock. MicroClock reserves the right to change any circuitry or specifications without notice. MicroClock does not
authorize or warrant any MicroClock product for use in life support devices or critical medical instruments.