The MK2712 is the ideal way to generate clocks for
NTSC/PAL video encoders and decoders. Stored in
the device are two sets of popular frequencies for
NTSC and PAL. In an 8 pin SOIC, the chip can save
component count, board space, and cost over surface
mount crystals and oscillators, and increase reliability
by eliminating one or two mechanical devices from the
board. The power down pin turns off the device,
drawing less than 20µA.
ICS/MicroClock offers many other clocks for computers
and computer peripherals. Consult us when you need
to remove crystals and oscillators from your board.
Features
• Packaged in 8 pin SOIC
• Ideal for chips such as Analog Devices AD722
and Brooktree BT819
• Input clock frequency of 27.0000 MHz
• Power down turns off chip
• Output enable tri-states output for system testing
• Frequencies are within 1 ppm with accurate
input clock
• Low jitter
• Output clock frequencies of 14.31818MHz,
17.7345MHz, 28.6364MHz, or 35.46896MHz
• 25mA drive capability at TTL levels
• 3.3V or 5V supply voltage
• Advanced, low power CMOS process
• Insensitive to input clock duty cycle
Block Diagram
VDDGND
FS0, 1
PD
27.00 MHz
clock input
MDS 2712 C1Revision 061401
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com
2
PLL
Clock Synthesis
Circuitry
Output
Buffer
OE
NTSC/PALCL
OCK
Page 2
MK2712
Description
Input Clock. Connect to a 27.0000 MHz clock.
Connect to +3.3V or +5V.
Connect to ground.
NTSC or PAL output clock. Selected by FS1, FS0 per tables above.
Frequency Select pin #1. Selects NTSC or PAL frequency per table above.
Output Enable. Tri-states clock output when this input is low. Internal pull-up.
Power Down. Active low. Clocks stop low.
Frequency Select pin #0. Selects NTSC or PAL frequency per table above.
Key: I = Input, O = output, P = power supply connection
External Components/Crystal Selection
A minimum number of external components are required for proper oscillation. Connect a 27.000 MHz clock to
ICLK. A decoupling capacitor of 0.1µF should be connected between VDD and GND on pins 2 and 3, and a 33Ω
terminating resistor should be used on the clock output if the trace is longer than 1 inch.
Description
Input Clock. Connect to a 27.0000 MHz clock.
Connect to +3.3V or +5V.
Connect to ground.
NTSC or PAL output clock. Selected by FS1, FS0 per tables above.
Frequency Select pin #1. Selects NTSC or PAL frequency per table above.
Output Enable. Tri-states clock output when this input is low. Internal pull-up.
Power Down. Active low. Clocks stop low.
Frequency Select pin #0. Selects NTSC or PAL frequency per table above.
MDS 2712 C2Revision 061401
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com
Page 3
MK2712
ABSOLUTE MAXIMUM RATINGS (note 1)
DC CHARACTERISTICS (at 5.0V unless otherwise noted)
AC CHARACTERISTICS (at 5.0V unless otherwise noted)
NTSC/PAL Clock Source
Electrical Specifications
ParameterConditionsMinimumTypicalMaximumUnits
Supply Voltage, VDDReferenced to GND7V
InputsReferenced to GND-0.5VDD+.5VV
Clock OutputsReferenced to GND-0.5VDD+.5VV
Ambient Operating Temperature070°C
Soldering TemperatureMax of 10 seconds260°C
Storage temperature-65150°C
Operating Voltage, VDD 4.55.5V
Input High Voltage, VIH, input clock onlyICLK pin3.52.5V
Input Low Voltage, VIL, input clock onlyICLK pin2.51.5V
Input High Voltage, VIH2V
Input Low Voltage, VIL0.8V
Output High Voltage, VOHIOH=-4mAVDD-0.4V
Output High Voltage, VOHIOH=-25mA2.4V
Output Low Voltage, VOLIOL=25mA0.4V
Operating Supply Current, IDDNo Load, FS1=1. FS0=113mA
Power Down Supply Current, IDDPDNo Load10µA
Input Capacitance5pF
Actual Mean Frequency versus TargetWith exact ICLK0.30.3ppm
Input Clock Frequency27MHz
Input Clock Duty CycleTime above 2.5V2080%
Output Clock Rise Time0.8 to 2.0V1.5ns
Output Clock Fall Time2.0 to 0.8V1.5ns
Output Clock Duty CycleTime above 1.5V405060%
Absolute Maximum Clock Period Jitter, 15 pF Variation from mean± 90ps
One Sigma Clock Period Jitter, 15 pF load30ps
Absolute Maximum Clock Period Jitter, 15 pFVDD=3.3V± 180ps
One Sigma Clock Period Jitter, 15 pF loadVDD=3.3V50ps
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device.
Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device
reliability.
2. Typical values are at 25°C.
MDS 2712 C3Revision 061401
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits,
patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring
extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by
ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life
support devices or critical medical instruments.
MDS 2712 C4Revision 061401
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com
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