The MK2731-03 is a low cost, low jitter, high
performance PLL clock synthesizer designed to
replace oscillators and PLL circuits in set-top box
and multimedia systems. Using our proprietary
analog Phase-Locked Loop (PLL) techniques, the
device uses an inexpensive crystal or clock input to
produce up to three output clocks. All of the audio
frequencies are synthesized exactly, with zero ppm
error, and locked to the 27 MHz clock.
MicroClock manufactures the largest variety of
Set-Top Box and multimedia clock synthesizers
for all applications. Consult MicroClock to
eliminate VCXOs, crystals and oscillators from
your board.
Block Diagram
Features
• Packaged in 16 pin narrow SOIC
• Produces exact audio clocks from the video
• Uses a crystal or clock input
• Zero ppm synthesis error in all clocks
• All frequencies are frequency locked
• 25mA output drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 3.3V or 5V operating voltage
Crystal
3
PLL/Clock
Synthesis
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
CLK1
CLK2
REF
S2:0
27 MHz crystal
or clock
(Capacitors are required
for crystal tuning)
MDS 2731-03C D1Revision 011101
Integrated Circuit Systems, Inc.• 525 Race Street, San Jose, CA, 95126 • (408) 295-9800 tel • www.icst.com
X1
Oscillator
X2
Page 2
Pin Assignment
MK2731-03C
MPEG Audio Clock Synthesizer
MK2731-03C
Output Clock Select Table (MHz)
16
X2
X1
VDD
VDD
GND
GND
S2
GND
1
2
3
4
5
6
7
8
16 pin narrow (150 mil) SOIC
Pin Descriptions
NumberName TypeDescription
1X2XOCrystal connection to a 27 MHz fundamental crystal. Leave unconnected for clock input.
2X1XICrystal connection to a 27 MHz fundamental crystal. Can also be connected to input clock.
3VDDPVDD. Connect to VDD.
4VDDPVDD. Connect to VDD.
5GNDPConnect to ground.
6GNDPConnect to ground.
7S2IClock Select 2. Selects outputs per table above.
8GNDPConnect to ground.
9DC-Do not connect anything to this pin.
10CLK1OClock output 1 determined by status of S2, S1, S0. See table above.
11S1IClock Select 1. Selects outputs per table above.
12NC-No Connect. Nothing is connected internally to this pin.
13S0IClock Select 0. Selects outputs per table above.
14CLK2OClock output 2 determined by status of S2, S1, S0. See table above.
15NC-No Connect. Nothing is connected internally to this pin.
16REFOReference crystal output or off. See table above.
1 = connect pin directly to VDD
Off = clock stopped low
Key: I = Input, O = output, P = power supply connection
MDS 2731-03C D2Revision 011101
Integrated Circuit Systems, Inc.• 525 Race Street, San Jose, CA, 95126 • (408) 295-9800 tel • www.icst.com
Page 3
MK2731-03C
ABSOLUTE MAXIMUM RATINGS (note 1)
DC CHARACTERISTICS (VDD = 5.0V unless noted)
AC CHARACTERISTICS (VDD = 5.0V unless noted)
see table on following page
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
MPEG Audio Clock Synthesizer
Electrical Specifications
ParameterConditionsMinimumTypicalMaximumUnits
Supply voltage, VDDReferenced to GND7V
Inputs and Clock OutputsReferenced to GND-0.5VDD+0.5V
Ambient Operating Temperature070°C
Soldering TemperatureMax of 10 seconds260°C
Storage temperature-65150°C
Operating Voltage, VDD 3.135.50V
Input High Voltage, VIH, X1 pin only(VDD/2)+1VDD/2V
Input Low Voltage, VIL, X1 pin onlyVDD/2(VDD/2)-1V
Input High Voltage, VIH 2V
Input Low Voltage, VIL0.8V
Output High Voltage, VOHIOH=-25mA2.4V
Output Low Voltage, VOLIOL=25mA0.4V
Output High Voltage, VOH, CMOS levelIOH=-8mAVDD-0.4V
Operating Supply Current, IDD No Load25mA
Short Circuit CurrentEach output±100mA
Input CapacitanceS2, S1, S07pF
Frequency synthesis error All clocks0ppm
Input Crystal or Clock Frequency
Input Crystal Accuracy±30ppm
Output Clock Rise Time0.8 to 2.0V1.5ns
Output Clock Fall Time2.0 to 0.8V1.5ns
Output Clock Duty CycleAt 1.4V4060%
Maximum Absolute Jitter, short term
Notes:1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
27.00
MHz
External Components
The MK2731-03 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1µF should be connected between VDD and GND on pins 3 and 5, as close to the
MK2731-03 as possible. A series termination resistor of 33Ω may be used for each clock output. The input
crystal must be connected as close to the chip as possible. The input crystal should be a parallel resonant,
fundamental, AT cut 27 MHz. For accurate tuning of the output when a crystal input is used, capacitors
should be connected between X1 and ground, and X2 and ground. The value of these capacitors is given by
the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-10) x 2. So for a
crystal with 16 pF load capacitance, two 12 pF caps can be used.
MDS 2731-03C D3Revision 011101
Integrated Circuit Systems, Inc.• 525 Race Street, San Jose, CA, 95126 • (408) 295-9800 tel • www.icst.com
Page 4
MK2731-03C
Inches
Millimeters
MPEG Audio Clock Synthesizer
Jitter Measurements
S2S1S0CLK2 5V 3.3V
(MHz)one sigma (ps)typical max (± ps)one sigma (ps)typical max (± ps)
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated assumes no responsibility for either its use or
for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for
use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental
requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize
or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 2731-03C D4Revision 011101
Integrated Circuit Systems, Inc.• 525 Race Street, San Jose, CA, 95126 • (408) 295-9800 tel • www.icst.com