The MK2703 is a low cost, low jitter, high
performance PLL clock synthesizer designed to
replace oscillators and PLL circuits in set-top box
and multimedia systems. Using our patented
analog Phase-Locked Loop (PLL) techniques, the
device uses a 27 MHz crystal or clock input to
produce a buffered reference clock and a selectable
audio clock.
MicroClock manufactures the largest variety of
Set-Top Box and multimedia clock synthesizers
for all applications. Consult MicroClock to
eliminate VCXOs, crystals and oscillators from
your board.
PLL Audio Clock Synthesizer
Features
• Packaged in 8 pin SOIC
• Uses an inexpensive fundamental crystal, or clock
• Supports MPEG sampling rates of 32 kHz,
44.1 kHz, 48 kHz and 96 kHz
• Patented zero ppm synthesis error in all clocks
• All frequencies are frequency locked
• 25 mA output drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 3.3 V or 5 V operating voltage
• For audio clocks that require lower jitter, use the
MK2731-03C
• Industrial temperature version available
Block Diagram
S1:0
27 MHz crystal or
clock
(Capacitors are required
X1
X2
for crystal tuning)
VDD GND
2
PLL
Clock Synthesis
and Control
Circuitry
Crystal
Oscillator
Output
Buffer
Output
Buffer
Audio Clock
27.000 MHz
MDS 2703 C1Revision 062700 Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
Page 2
MK2703
Pin Assignment
MK2703
X1
VDD
GND
27M
18
2
3
4
8 pin SOIC
ICRO
7
6
5
C
LOCK
X2
S0
S1
CLK
PLL Audio Clock Synthesizer
Audio Clock Output Select Table (MHz)
S1S0CLK
008.192
0111.2896
1012.288
1124.576
Key: 0 = connect pin directly to ground
1 = connect pin directly to VDD
Pin Descriptions
NumberName Type Description
1X1XICrystal Connection. Connect to a 27.0 MHz fundamental crystal or clock.
2VDDPConnect to +3.3V or +5V.
3GNDPConnect to ground.
427MO27.00 MHz buffered reference clock output.
5CLKOAudio Clock Output per table above.
6S1I(PU) Audio Clock Frequency Select Input #1. Determines CLK output per table above.
7S0I(PU) Audio Clock Frequency Select Input #0. Determines CLK output per table above.
8X2XO Crystal Connection to a 27.0 MHz crystal, or leave unconnected for clock input.
Key: XI, XO = Crystal connections; I(PU)= Input with internal pull-up resistor; O = output;
P = power supply connection
MDS 2703 C2Revision 062700 Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
Page 3
MK2703
ABSOLUTE MAXIMUM RATINGS (note 1)
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
ICRO
C
LOCK
PLL Audio Clock Synthesizer
Electrical Specifications
ParameterConditionsMinimumTypicalMaximumUnits
Supply voltage, VDDReferenced to GND7V
Inputs and Clock OutputsReferenced to GND-0.5VDD+0.5V
Ambient Operating TemperatureMK2703S070°C
MK2703SI-4085°C
Soldering TemperatureMax of 10 seconds260°C
Storage temperature-65150°C
Operating Voltage, VDD 3.135.50V
Input High Voltage, VIH, X1 pin only(VDD/2)+1VDD/2V
Input Low Voltage, VIL, X1 pin onlyVDD/2(VDD/2)-1V
Input High Voltage, VIH 2V
Input Low Voltage, VIL0.8V
Output High Voltage, VOHIOH=-12mA2.4V
Output Low Voltage, VOLIOL=12mA0.4V
Output High Voltage, VOH, CMOS levelIOH=-4mAVDD-0.4V
Operating Supply Current, IDD No Load25mA
Short Circuit CurrentEach output±50mA
Input CapacitanceS1, S05pF
Frequency synthesis error All clocks0ppm
Input Crystal Frequency27.00MHz
Input Crystal Accuracy±30ppm
Output Clock Rise Time0.8 to 2.0V1.5ns
Output Clock Fall Time2.0 to 0.8V1.5ns
Output Clock Duty CycleAt VDD/24060%
Maximum Absolute Jitter, short term±190ps
Notes:1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
External Components
The MK2703 requires a minimum number of external components for proper operation. For a crystal input,
one load capacitor should be connected from each of the X1 and X2 pins to ground. The value (in pF) of
each crystal load capacitor should equal (CL-16)•2, where CL is the crystal’s load (correlation) capacitance
in pF. The input crystal must be connected as close to the chip as possible. The input crystal should be a
parallel resonant, fundamental, AT cut 27 MHz. For a clock input, connect to X1 and leave X2
unconnected. Decoupling capacitors of 0.01µF should be connected between VDD and GND on pins 2
and 3, as close to the MK2703 as possible. A series termination resistor of 33 Ω may be used for the clock
output.
MDS 2703 C3Revision 062700 Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
Page 4
MK2703
Inches
Millimeters
ICRO
C
LOCK
PLL Audio Clock Synthesizer
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
MK2703SITRMK2703Itape and reel8 pin SOIC-40 to 85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc. (ICS) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental
requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize
or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 2703 C4Revision 062700 Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
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