Datasheet MJ10016, MJ10015 Datasheet (Motorola)

1

Motorola Bipolar Power Transistor Device Data

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The MJ10015 and MJ10016 Darlington transistors are designed for high–voltage,
high–speed, power switching in inductive circuits where fall time is critical. They are
particularly suited for line–operated switchmode applications such as:

• Switching Regulators

• Motor Controls

• Inverters

• Solenoid and Relay Drivers

• Fast Turn–Off Times

1.0 µs (max) Inductive Crossover Time — 20 Amps

2.5 µs (max) inductive Storage Time — 20 Amps

• Operating Temperature Range –65 to +200_C

• Performance Specified for

Reversed Biased SOA with Inductive Load
Switching Times with Inductive Loads
Saturation Voltages
Leakage Currents

MAXIMUM RATINGS

Rating

Symbol

MJ10015

MJ10016

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Unit

Collector–Emitter Voltage

V

CEO

400

500

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Vdc

Collector–Emitter Voltage

V

CEV

600

700

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Vdc

Emitter Base Voltage

V

EB

8.0

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Vdc

Collector Current — Continuous

— Peak (1)

I

C

I

CM

50
75

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Adc

Base Current — Continous

— Peak (1)

I

B

I

BM

10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Adc

Total Power Dissipation @ TC = 25_C

@ TC = 100_C

Derate above 25_C

P

D

250
143

1.43

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Watts

W/_C

Operating and Storage Junction Temperature Range

TJ, T

stg

–65 to +200

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

_

C

THERMAL CHARACTERISTICS

Characteristic

Symbol

Max

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Unit

Thermal Resistance, Junction to Case

R

θJC

0.7

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

_

C/W

Maximum Lead Temperature for Soldering Purposes:

1/8″ from Case for 5 Seconds

T

L

275

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

_

C

(1) Pulse Test: Pulse Width = 5 ms, Duty Cycle v 10%.

SWITCHMODE is a trademark of Motorola, Inc.



SEMICONDUCTOR TECHNICAL DATA

Order this document

by MJ10015/D

 Motorola, Inc. 1995

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

50 AMPERE

NPN SILICON

POWER DARLINGTON

TRANSISTORS

400 AND 500 VOLTS

250 WATTS

CASE 197–05

TO–204AE TYPE

(TO–3 TYPE)

≈

50

≈

8

REV 1

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2

Motorola Bipolar Power Transistor Device Data

ELECTRICAL CHARACTERISTICS (T

C

= 25_C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

ÎÎÎ

ÎÎÎ

ÎÎÎ

Unit

OFF CHARACTERISTICS (1)

Collector–Emitter Sustaining Voltage (Table 1)

(IC = 100 mA, IB = 0, V

clamp

= Rated V

CEO

) MJ10015

MJ10016

V

CEO(sus)

400
500

—
—

—
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

Vdc

Collector Cutoff Current

(V

CEV

= Rated Value, V

BE(off)

= 1.5 Vdc)

I

CEV

—

—

0.25

ÎÎÎ

ÎÎÎ

ÎÎÎ

mAdc

Emitter Cutoff Current

(VEB = 2.0 Vdc, IC = 0)

I

EBO

—

—

350

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

mAdc

SECOND BREAKDOWN

Second Breakdown Collector Current with Base Forward Biased

I

S/b

See Figure 7

ÎÎÎ

ÎÎÎ

ÎÎÎ

Clamped Inductive SOA with Base Reverse Biased

RBSOA

See Figure 8

ÎÎÎ

ÎÎÎ

ÎÎÎ

ON CHARACTERISTICS (1)

DC Current Gain

(IC = 20 Adc, VCE = 5.0 Vdc)
(IC = 40 Adc, VCE = 5.0 Vdc)

h

FE

25
10

—
—

—
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—

Collector–Emitter Saturation Voltage

(IC = 20 Adc, IB = 1.0 Adc)
(IC = 50 Adc, IB = 10 Adc)

V

CE(sat)

—
—

—
—

2.2

5.0

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

Vdc

Base–Emitter Saturation Voltage

(IC = 20 Adc, IB = 1.0 Adc)

V

BE(sat)

—

—

2.75

ÎÎÎ

ÎÎÎ

ÎÎÎ

Vdc

Diode Forward Voltage (2)

(IF = 20 Adc)

V

f

—

2.5

5.0

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

Vdc

DYNAMIC CHARACTERISTIC

Output Capacitance

(VCB = 10 Vdc, IE = 0, f

test

= 100 kHz)

C

ob

—

—

750

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

pF

SWITCHING CHARACTERISTICS

Resistive Load (Table 1)

Delay Time

t

d

—

0.14

0.3

ÎÎÎ

ÎÎÎ

ÎÎÎ

µs

Rise Time

t

r

—

0.3

1.0

ÎÎÎ

ÎÎÎ

ÎÎÎ

µs

Storage Time

IB1 = 1.0 Adc, V

BE(off)

= 5 Vdc, tp = 25 µs

Duty Cycle v 2%).

t

s

—

0.8

2.5

ÎÎÎ

ÎÎÎ

ÎÎÎ

µs

Fall Time

v

2%).

t

f

—

0.3

1.0

ÎÎÎ

ÎÎÎ

ÎÎÎ

µs

Inductive Load, Clamped (Table 1)

Storage Time

C

= 20 A(pk), V

clamp

= 250 V, IB1 = 1.0 A,

t

sv

—

1.0

2.5

ÎÎÎ

ÎÎÎ

ÎÎÎ

µs

Crossover Time

(IC = 20 A(pk), V

clamp

= 250 V, IB1 = 1.0 A,

V

BE(off)

= 5.0 Vdc)

t

c

—

0.36

1.0

ÎÎÎ

ÎÎÎ

ÎÎÎ

µs

(1) Pulse Test: Pulse Width = 300 µs, Duty Cycle v 2%.
(2) The internal Collector–to–Emitter diode can eliminate the need for an external diode to clamp inductive loads.

(2) Tests have shown that the Forward Recovery Voltage (Vf) of this diode is comparable to that of typical fast recovery rectifiers.

(VCC = 250 Vdc, IC = 20 A,

(I

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3

Motorola Bipolar Power Transistor Device Data

V, VOLTAGE (VOLTS)

–0.2

VBE, BASE–EMITTER VOLTAGE (VOLTS)

0

2.8

IC, COLLECTOR CURRENT (AMP)

2.4

2.0

1.6

1.2

IC/IB = 10

100

0.5

Figure 1. DC Current Gain

IC, COLLECTOR CURRENT (AMPS)

5.0

1.0 2.0 5.0 10 20 50

50

10

20

Figure 2. Collector–Emitter Saturation Voltage

0.5
IC, COLLECTOR CURRENT (AMP)

0.4

2.0 5.0

1.2

0.8

h

FE

, DC CURRENT GAIN

TC = 25°C
VCE = 5.0 V

10 20 50

Figure 3. Base–Emitter Saturation Voltage

+0.20.5 1.0 2.0 10 50205.0

Figure 4. Collector Cutoff Region

2.4

2.0

1.6

Figure 5. Output Capacitance

1500

0.4
VR, REVERSE VOLTAGE (VOLTS)

100

10

1000

100 400

C

200

FORWARD

0.8

VCE = 250 V

75

°

C

100°C

REVERSE

25°C

TJ = 125°C

1.0 4.0 40

300

500

TJ = 150°C

TJ = 25°C

10

4

10

3

10

2

10

1

10

0

10

–1

, OUTPUT CAPACITANCE (pF)

ob

1.0

, COLLECTOR CURRENT ( A)

µ

I

C

V, VOLTAGE (VOLTS)

IC/IB = 10

TJ = 150°C

TJ = 25°C

+0.4 +0.6 +0.8

TJ = 25°C

TYPICAL CHARACTERISTICS

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4

Motorola Bipolar Power Transistor Device Data

Table 1. Test Conditions for Dynamic Performance

V

CEO(sus)

V

CEX

AND INDUCTIVE SWITCHING RESISTIVE SWITCHING

INPUT

CONDITIONS

CIRCUIT

VALUES

TEST CIRCUITS

20

Ω

1

0

PW Varied to Attain
IC = 100 mA

L

coil

= 10 mH, VCC = 10 V

R

coil

= 0.7 Ω

V

clamp

= V

CEO(sus)

L

coil

= 180 µH

R

coil

= 0.05 Ω

VCC = 20 V

VCC = 250 V
RL = 12.5 Ω
Pulse Width = 25 µs

INDUCTIVE TEST CIRCUIT

TURN–ON TIME

IB1 adjusted to

obtain the forced

hFE desired

TURN–OFF TIME

Use inductive switching

driver as the input to

the resistive test circuit.

t1 Adjusted to
Obtain I

C

Test Equipment

Scope — Tektronix

475 or Equivalent

RESISTIVE TEST CIRCUITOUTPUT WAVEFORMS

2

I

B1

1
2

5 V

INDUCTIVE TEST CIRCUIT

1

INPUT

2

R

coil

L

coil

V

CC

V

clamp

RS =

0.1

Ω

1N4937

OR

EQUIVALENT

TUT

SEE ABOVE FOR
DETAILED CONDITIONS

1

INPUT

2

R

coil

L

coil

V

CC

V

clamp

RS =

0.1

Ω

1N4937

OR

EQUIVALENT

TUT

SEE ABOVE FOR
DETAILED CONDITIONS

t

1

I

C(pk)

tf Clamped

t

f

t

t

t

2

TIME

VCE

or

V

clamp

1
2

TUT

R

L

V

CC

t1 ≈

L

coil (IC

pk

)

V

CC

t2 ≈

L

coil (IC

pk

)

V

Clamp

*Adjust –V such that V

BE(off)

= 5 V except as required for RBSOA (Figure 8).

Figure 6. Inductive Switching Measurements

t

rv

TIME

I

C

V

CE

90% I

B1

t

sv

IC pk

V

clamp

90% V

clamp

90% I

C

10% V

clamp

10%

IC pk

2% I

C

I

B

t

fi

t

ti

t

c

SWITCHING TIMES NOTE

In resistive switching circuits, rise, fall, and storage times
have been defined and a pply to both current and voltage
waveforms since they are in phase. However, for inductive
loads which are common to SWITCHMODE power supplies

and hammer drivers, current and voltage waveforms are not
in phase. Therefore, separate measurements must be made
on each waveform to determine the total switching time. For
this reason, the following new terms have been defined.

tsv = Voltage Storage Time, 90% IB1 to 10% V

clamp

trv = Voltage Rise Time, 10ā–ā90% V

clamp

tfi = Current Fall Time, 90ā–ā10% I

C

tti = Current Tail, 10ā–ā2% I

C

tc = Crossover Time, 10% V

clamp

to 10% I

C

For the designer, there is minimal switching loss during
storage time and the predominant switching power losses
occur during the crossover interval and can be obtained us­ing the standard equation from AN–222:

P

SWT

= 1/2 VCC IC (tc) f

In general, trv + tfi ^ tc. However, at lower test currents
this relationship may not be valid.

As is common with most switching transistors, resistive
switching is specified and has become a benchmark for de­signers. However, for designers of high frequency converter
circuits, the user oriented specifications which make this a
“SWITCHMODE” transistor are t he inductive switching
speeds (tc and tsv) which are guaranteed.

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5

Motorola Bipolar Power Transistor Device Data

The Safe Operating Area figures shown in Figures 7 and 8 are
specified ratings for these devices under the test conditions
shown.

1.0

Figure 7. Forward Bias Safe Operating Area

VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)

5.0 50

0.005

50
20

2.0

1.0

5.0

0.5

100010 100

0

Figure 8. Reverse Bias Switching Safe

Operating Area

VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)

0

200 300

40

20

50

400

TC = 25°C

I

C

, COLLECTOR CURRENT (AMPS)

0.1

200

dc

I

C

, COLLECTOR CURRENT (AMPS)

2.0 20 500

30

10

0.2

0.02

0.01

500

V

BE(off)

= 5.0 V

TC = 25

°

C

MJ10015

0.05

10

TURN–OFF LOAD LINE
BOUNDARY FOR MJ10016
THE LOCUS FOR MJ10015
IS 100 V LESS

10 µs

I

C

I

B1

u

10

BONDING WIRE LIMIT
THERMAL LIMIT (SINGLE PULSE)
SECOND BREAKDOWN LIMIT

MJ10016

100

SAFE OPERATING AREA INFORMATION

FORWARD BIAS

There are two Iimitations on the power handling ability of a
transistor: average junction temperature and second break­down. Safe operating area curves indicate IC – VCE limits of
the transistor that must be observed for reliable operation,
i.e., the transistor must not be subjected to greater dissipa­tion than the curves indicate.

The data of Figure 7 is based on TC = 25_C; T

J(pk)

is
variable depending on power level. Second breakdown pulse
limits are valid for duty cycles to 10% but must be derated
when TC ≥ 25_C. Second breakdown limitations do not der­ate the same as thermal limitations. Allowable current at the
voltages shown on Figure 7 may be found at any case tem­perature by using the appropriate curve on Figure 9.

REVERSE BIAS

For inductive loads, high voltage and high current must be
sustained simultaneously during turn–off, in most cases, with
the base to e mitter junction reverse b iased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping,
RC snubbing, load line shaping, etc. The safe level for these
devices is specified as Reverse Bias Safe Operating Area
and represents the voltage–current condition allowable dur­ing reverse biased turn–off. This rating is verified under
clamped conditions so that the device is never subjected to
an avalanche mode. Figure 8 gives the complete RBSOA
characteristics.

0

Figure 9. Power Derating

TC, CASE TEMPERATURE (°C)

0

40 80

80

40

100

120

POWER DERATING FACTOR (%)

160 200

60

20

THERMAL

DERATING

V

BE(off)

, REVERSE BASE VOLTAGE (VOLTS)

1 2 3 4 5 6

10

8

6
5
4
3
2

0

, BASE CURRENT (AMP)I

B2(pk)

0

SEE TABLE 1 FOR CONDITIONS,
FIGURE 6 FOR WAVESHAPE.

9

7

1

7 8

Figure 10. Typical Reverse Base Current

versus V

BE(off)

With No External Base

Resistance

IC = 20 A

FORWARD BIAS
SECOND BREAKDOWN
DERATING

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6

Motorola Bipolar Power Transistor Device Data

PACKAGE DIMENSIONS

CASE 197–05

TO–204AE TYPE

(TO–3 TYPE)

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

STYLE 1:

PIN 1. BASE

2. EMITTER

CASE: COLLECTOR

A

N

E

C

K

D

2 PL

SEATING
PLANE

–T–

U

L

M

Q

M

0.25 (0.010) Y

M

T

–Y–

H

G

B

–Q–

2

1

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 1.510 1.550 38.35 39.37
B 0.980 1.050 24.89 26.67
C 0.250 0.335 6.35 8.51
D 0.057 0.063 1.45 1.60
E 0.060 0.135 1.52 3.43

G 0.420 0.440 10.67 11.18

H 0.205 0.225 5.21 5.72
K 0.440 0.480 11.18 12.19
L 0.655 0.675 16.64 17.15
N 0.760 0.830 19.30 21.08

Q 0.151 0.175 3.84 4.19

U 1.177 1.197 29.90 30.40

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MJ10015/D

*MJ10015/D*

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