
1
Motorola Bipolar Power Transistor Device Data
The MJ10000 Darlington transistor is designed for high–voltage, high–speed,
power switching in inductive circuits where fall time is critical. It is particularly suited
for line operated switchmode applications such as:
• Switching Regulators
• Inverters
• Solenoid and Relay Drivers
• Motor Controls
• Deflection Circuits
100_C Performance Specified for:
Reversed Biased SOA with Inductive Loads
Switching Times With Inductive Loads —
210 ns Inductive Fall Time (Typ)
Saturation Voltages
Leakage Currents
Collector–Emitter Voltage
Collector–Emitter Voltage
Collector–Emitter Voltage
Collector Current — Continuous
— Peak (1)
Base Current — Continuous
— Peak (1)
Total Power Dissipation @ TC = 25_C
@ TC =100_C
Derate above 25_C
Operating and Storage Junction Temperature Range
Thermal Resistance, Junction to Case
Maximum Lead Temperature for Soldering
Purposes: 1/8″ from Case for 5 Seconds
_
C
(1) Pulse Test: Pulse Width = 5 ms, Duty Cycle v 10%.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MJ10000/D
20 AMPERE
NPN SILICON
POWER DARLINGTON
TRANSISTORS
350 VOLTS
175 WATTS
CASE 1–07
TO–204AA
(TO–3)
≈
100≈ 15
REV 4

MJ10000
2
Motorola Bipolar Power Transistor Device Data
ELECTRICAL CHARACTERISTICS (T
C
= 25_C unless otherwise noted)
Collector–Emitter Sustaining Voltage (Table 1)
(IC = 250 mA, IB = 0, V
clamp
= Rated V
CEO
) MJ10000
Collector–Emitter Sustaining Voltage (Table 1, Figure 12)
IC = 2 A, V
clamp
= Rated V
CEX
, TC = 100_C MJ10000
IC = 10 A, V
clamp
= Rated V
CEX
, TC = 100_C MJ10000
Collector Cutoff Current
(V
CEV
= Rated Value, V
BE(off)
= 1.5 Vdc)
(V
CEV
= Rated Value, V
BE(off)
= 1.5 Vdc, TC = 150_C)
Collector Cutoff Current
(VCE = Rated V
CEV
, RBE = 50 Ω, TC = 100_C)
Emitter Cutoff Current
(VEB = 8 Vdc, IC = 0)
Second Breakdown Collector Current with base forward biased
DC Current Gain
(IC = 5 Adc, VCE = 5 Vdc)
(IC = 10 Adc, VCE = 5 Vdc)
Collector–Emitter Saturation Voltage
(IC = 10 Adc, IB = 400 mAdc)
(IC = 20 Adc, IB = 1 Adc)
(IC = 10 Adc, IB = 400 mAdc, TC = 100_C)
Base–Emitter Saturation Voltage
(IC = 10 Adc, IB = 400 mAdc)
(IC = 10 Adc, IB = 400 mAdc, TC = 100_C)
Diode Forward Voltage (1)
(IF = 10 Adc)
Small–Signal Current Gain
(IC = 1.0 Adc, VCE = 10 Vdc, f
test
= 1 MHz)
Output Capacitance
(VCB = 10 Vdc, IE = 0, f
test
= 100 kHz)
SWITCHING CHARACTERISTICS
Resistive Load (Table 1)
Delay Time (VCC = 250 Vdc, IC = 10 A,
Rise Time IB1 = 400 mA, V
BE(off)
= 5 Vdc, tp = 50 µs,
Storage Time Duty Cycle v 2%)
Fall Time
Inductive Load, Clamped (Table 1)
Storage Time (IC = 10 A(pk), V
clamp
= Rated V
CEX
, IB1 = 400 mA,
Crossover Time V
BE(off)
= 5 Vdc, TC = 100_C)
Storage Time (IC = 10 A(pk), V
clamp
= Rated V
CEX
, IB1 = 400 mA,
Crossover Time V
BE(off)
= 5 Vdc, TC = 25_C)
µs
µs
(1) The internal Collector–to–Emitter diode can eliminate the need for an external diode to clamp inductive loads.
(1) Tests have shown that the Forward Recovery Voltage (Vf) of this diode Is comparable to that of typical fast recovery rectifiers.
(2) Pulse Test: Pulse Width = 300 µs, Duty Cycle v 2%.

MJ10000
3
Motorola Bipolar Power Transistor Device Data
Figure 1. DC Current Gain
IC, COLLECTOR CURRENT (AMP)
5
0.2 0.3 1 2 3
100
50
Figure 2. Collector Saturation Region
V, VOLTAGE (VOLTS)
3
IB, BASE CURRENT (ANP)
1
0.02 0.03 0.1 0.2 0.5 1 2
2.6
2.2
1.8
1.4
IC = 5 A
TJ = 25°C
10 A
VBE, BASE-EMITTER VOLTAGE (VOLTS)
10
4
10
3
10
2
10
1
500
70
h
FE
, DC CURRENT GAIN
TJ = 150°C
VCE = 5 V
, COLLECTOR CURRENT ( A)I
C
10
0
0 +0.2–0.2
VCE = 250 V
TJ = 125°C
100°C
25°C
30
20
10
7
0.5 0.7 5 7 20
Figure 3. Collector Emitter Saturation Voltages
2.4
0.2
IC, COLLECTOR CURRENT (AMPS)
0.4
0.3 0.5 0.7 1 2 5 20
2
1.6
1.2
0.8
IC/IB = 25
TJ = – 55°C
73
Figure 4. Base-Emitter Voltage
2.8
IC, COLLECTOR CURRENT (AMP)
0.8
0.2 0.3 0.5 0.7
2.4
2
1.6
1.2
Figure 5. Collector Cutoff Region
0.4
Figure 6. Output Capacitance
VR, REVERSE VOLTAGE (VOLTS)
50
1 2 20 60100.6
200
70
TJ = 25°C
C
ob
1000
500
100
100 200 400
25°C
–55°C
200
300
10
15 A 20 A
0.05 0.70.30.07
V, VOLTAGE (VOLTS)
10
25°C
150°C
2 5 2073 101
25°C
150°C
25°C
TJ = 55°C
V
BE(sat)
@ IC/IB = 25
V
BE(on)
@ VCE = 3 V
75°C
µ
10
–1
+0.4 +0.8+0.6
4 6 40
700
300
C
ob
, OUTPUT CAPACITANCE (pF)
DC CHARACTERISTICS
, COLLECTOR–EMITTER VOLTAGE (VOLTS)
CE
V

MJ10000
4
Motorola Bipolar Power Transistor Device Data
I
C(pk)
t
t
1
t
f
t
I
C
V
CE
TEST CIRCUITS
CIRCUIT
VALUES
INPUT
CONDITIONS
V
CEO(sus)
V
CEX(sus)
AND INDUCTIVE SWITCHING RESISTIVE SWITCHING
L
coil
= 10 mH, VCC = 10 V
R
coil
= 0.7 Ω
V
clamp
= V
CEO(sus)
L
coil
= 180 µH
R
coil
= 0.05 Ω
VCC = 20 V
V
clamp
= Rated V
CEX
Value
VCC = 250 V
RL = 25 Ω
Pulse Width = 50 µs
t
2
TIME
tf CLAMPED
VCE or
V
clamp
tf UNCLAMPED
[
t
2
20
1
0
PW Varied to Attain
IC = 250 mA
2
INDUCTIVE TEST CIRCUIT
INDUCTIVE TEST CIRCUIT
t1 Adjusted to
Obtain I
C
Test Equipment
Scope — Tektronix
475 or Equivalent
RESISTIVE TEST CIRCUITOUTPUT WAVEFORMS
1
INPUT
2
R
coil
L
coil
V
CC
V
clamp
RS =
0.1
Ω
1N4937
OR
EQUIVALENT
TUT
SEE ABOVE FOR
DETAILED CONDITIONS
1
2
TUT
R
L
V
CC
t1 ≈
L
coil (IC
pk
)
V
CC
t2 ≈
L
coil (IC
pk
)
V
Clamp
1
INPUT
2
R
coil
L
coil
V
CC
V
clamp
RS =
0.1
Ω
1N4937
OR
EQUIVALENT
TUT
SEE ABOVE FOR
DETAILED CONDITIONS
Table 1. Test Conditions for Dynamic Performance
Figure 7. Inductive Switching Measurements
TIME
t
sv
t
rv
t
fi
t
ti
90% V
clamp
t
c
90% I
B1
I
B
10%
I
C
2%
I
C
V
clamp
I
C
V
clamp
10%
V
clamp
SWITCHING TIMES NOTE
In resistive switching circuits, rise, fall, and storage times
have been defined and a pply to both current and voltage
waveforms since they are in phase. However, for inductive
loads which are common to SWITCHMODE power supplies
and hammer drivers, current and voltage waveforms are not
in phase. Therefore, separate measurements must be made
on each waveform to determine the total switching time. For
this reason, the following new terms have been defined.
tsv = Voltage Storage Time, 90% IB1 to 10% V
clamp
trv = Voltage Rise Time, 10–90% V
clamp
tfi = Current Fall Time, 90–10% I
C
tti = Current Tail, 10–2% I
C
tc = Crossover Time, 10% V
clamp
to 10% I
C
An enlarged portion of the turn–off waveforms is shown in
Figure 7 to aid in the visual identity of these terms.

MJ10000
5
Motorola Bipolar Power Transistor Device Data
SWITCHING TIMES NOTE (continued)
For the designer, there is minimal switching loss during
storage time and the predominant switching power losses
occur during the crossover interval and can be obtained using the standard equation from AN–222:
P
SWT
= 1/2 VCCIC(tc)f
In general, trv + tfi ] tc. However, at lower test currents this
relationship may not be valid.
As is common with most switching transistors, resistive
switching is specified at 25_C and has become a benchmark
for designers. However, for designers of high frequency converter circuits, the user oriented specifications which make
this a “SWITCHMODE” transistor are the inductive switching
speeds (tc and tsv) which are guaranteed at 100_C.
3
Figure 8. Turn–On Time
IC, COLLECTOR CURRENT (AMP)
t, TIME ( s)
µ
2
0.7
0.1
3 20
0.2
1 5
t
d
t
r
2 7
1
0.3
0.5
2
Figure 9. Turn–Off Time
IC, COLLECTOR CURRENT (AMP)
t, TIME ( s)
µ
0.7
0.2
0.1
V
BF(off)
= 5 V
VCC = 250 V
IC/IB = 25
TJ = 25
°
C
t
f
t
s
0.3
0.5
V
BE(off)
= 5 V
VCC = 250 V
IC/IB = 25
TJ = 25
°
C
10 3 201 52 7 10
1
RESISTIVE SWITCHING PERFORMANCE
Figure 10. Thermal Response
t, TIME (ms)
1.0
0.01
0.01
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 1.0 k500
Z
θ
JC
(t) = r(t) R
θ
JC
R
θ
JC
= 1.0
°
C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
– TC = P
(pk)
Z
θ
JC(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t1/t
2
D = 0.5
0.2
0.05
0.02
0.01
SINGLE PULSE
0.1
r(t), TRANSIENT THERMAL RESISTANCE
(NORMALIZED)

MJ10000
6
Motorola Bipolar Power Transistor Device Data
The Safe Operating Area figures shown in Figures 11 and 12 are
specified for these devices under the test conditions shown.
50
4.0
Figure 11. Forward Bias Safe Operating Area
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
10
3.0
1.0
0.5
0.1
0.02
7.0 10 20 30 70
400
BONDING WIRE LIMITED
THERMALLY LIMITED
SECOND BREAKDOWN LIMITED
50
0.005
I
C
, COLLECTOR CURRENT (AMPS)
TC = 25°C
dc
0.2
100 200
350
100 µs
10 µs
20
0
Figure 12. Reverse Bias Switching
Safe Operating Area
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
16
12
0
500
4
I
C
, COLLECTOR CURRENT (AMP)
8
300 400100 200
V
BE(off)
= 5 V
TURN OFF LOAD LINE
BOUNDARY FOR MJ10001.
THE LOCUS FOR MJ10000
IS 50 V LESS
1 ms
5 ms
CURVES APPLY BELOW RATED V
CEO
MJ10000
MJ10001
V
BE(off)
= 2 V
V
BE(off)
= 0 V
TJ v 100°C
0.01
0.05
20
SAFE OPERATING AREA INFORMATION
FORWARD BIAS
There are two limitations on the power handling ability of a
transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC – VCE limits of
the transistor that must be observed for reliable operation;
i.e., the transistor must not be subjected to greater dissipation than the curves indicate.
The data of Figure 11 is based on TC = 25_C; T
J(pk)
is
variable depending on power level. Second breakdown pulse
limits are valid for duty cycles to 10% but must be derated
when TC ≥ 25_C. Second b reakdown limitations do not
derate the same as thermal limitations. Allowable current at
the voltages shown on Figure 11 may be found at any case
temperature by using the appropriate curve on Figure 13.
T
J(pk)
may be calculated from the data in Figure 10. At high
case temperatures, thermal limitations will reduce the power
that can be handled to values less than the limitations imposed by second breakdown.
REVERSE BIAS
For inductive loads, high voltage and high current must be
sustained simultaneously during turn–off, in most cases, with
the base to e mitter junction reverse biased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping,
RC snubbing, load line shaping, etc. The safe level for these
devices is specified as V
CEX(sus)
at a given collector current
and represents a voltage–current condition that can be sustained during reverse biased turn–off. This rating is verified
under clamped conditions so that the device is never subjected to an avalanche mode. Figure 12 gives the complete
reverse bias safe operating area characteristics.
100
80
60
20
0
0 40 80 120 200
Figure 13. Power Derating
TC, CASE TEMPERATURE (°C)
POWER DERATING FACTOR (%)
THERMAL DERATING
SECOND BREAKDOWN
DERATING
160

MJ10000
7
Motorola Bipolar Power Transistor Device Data
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. ALL RULES AND NOTES ASSOCIATED WITH
REFERENCED TO–204AA OUTLINE SHALL APPLY.
STYLE 1:
PIN 1. BASE
2. EMITTER
CASE: COLLECTOR
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 1.550 REF 39.37 REF
B ––– 1.050 ––– 26.67
C 0.250 0.335 6.35 8.51
D 0.038 0.043 0.97 1.09
E 0.055 0.070 1.40 1.77
G 0.430 BSC 10.92 BSC
H 0.215 BSC 5.46 BSC
K 0.440 0.480 11.18 12.19
L 0.665 BSC 16.89 BSC
N ––– 0.830 ––– 21.08
Q 0.151 0.165 3.84 4.19
U 1.187 BSC 30.15 BSC
V 0.131 0.188 3.33 4.77
A
N
E
C
K
–T–
SEATING
PLANE
2 PLD
M
Q
M
0.13 (0.005) Y
M
T
M
Y
M
0.13 (0.005) T
–Q–
–Y–
2
1
U
L
G
B
V
H
CASE 1–07
TO–204AA (TO–3)
ISSUE Z

MJ10000
8
Motorola Bipolar Power Transistor Device Data
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MJ10000/D
*MJ10000/D*
◊